coreboot-gerrit January 2019

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Change in ...coreboot[master]: util/autoport: Fix include style
by Angel Pons (Code Review) 18 Jan '19

18 Jan '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30970 Change subject: util/autoport: Fix include style ...................................................................... util/autoport: Fix include style Change-Id: If0dfee38bd82b3c8e9b5173e520cb244787c0a9a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30970/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 887a520..b0045ce 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -313,9 +313,9 @@ #include <cpu/x86/lapic.h> #include <arch/acpi.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/30970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dfee38bd82b3c8e9b5173e520cb244787c0a9a Gerrit-Change-Number: 30970 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport: Break very long line
by Angel Pons (Code Review) 18 Jan '19

18 Jan '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30968 Change subject: util/autoport: Break very long line ...................................................................... util/autoport: Break very long line Change-Id: Id45b0970a457ad4a724b71b4887ce4a1332596be Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/sandybridge.go 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30968/1 diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 4f08ad9..41ac96d 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -10,7 +10,9 @@ /* FIXME:XX Move this somewhere else. */ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") MainboardEnable += (` /* FIXME: fix those values*/ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); `) pchLVDS := inteltool.IGD[0xe1180] -- To view, visit https://review.coreboot.org/c/coreboot/+/30968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id45b0970a457ad4a724b71b4887ce4a1332596be Gerrit-Change-Number: 30968 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport: Correct DSDT header
by Angel Pons (Code Review) 18 Jan '19

18 Jan '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30967 Change subject: util/autoport: Correct DSDT header ...................................................................... util/autoport: Correct DSDT header A previous change emoved model_206ax code to a common place, but forgot to update autoport. Correct this so resulting autoport errors less. Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/sandybridge.go 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30967/1 diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index cf2b859..4f08ad9 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -122,7 +122,7 @@ KconfigInt["MAX_CPUS"] = 8 DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "cpu/intel/model_206ax/acpi/cpu.asl", + File: "cpu/intel/common/acpi/cpu.asl", }) DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ -- To view, visit https://review.coreboot.org/c/coreboot/+/30967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493 Gerrit-Change-Number: 30967 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Access SMBUS through MMIO
by Richard Spiegel (Code Review) 18 Jan '19

18 Jan '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29258 ) Change subject: soc/amd/stoneyridge: Access SMBUS through MMIO ...................................................................... Patch Set 12: Build failure fixed. Please review. -- To view, visit https://review.coreboot.org/c/coreboot/+/29258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Gerrit-Change-Number: 29258 Gerrit-PatchSet: 12 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Jan 2019 16:42:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/skylake: Use common EMMC block code
by Subrata Banik (Code Review) 18 Jan '19

18 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23705 ) Change subject: soc/intel/skylake: Use common EMMC block code ...................................................................... Patch Set 3: (2 comments) We have unmark private this CL's because we are in process to make a White Paper on this emmc init over multi-thread environment in bios phase. I remember we had this discussion with you and Duncan. I will post document link once ready for public access. Looks like some customers would like to make use of the same https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/Kconfig File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/Kconfig@63 PS3, Line 63: select SOC_INTEL_COMMON_BLOCK_EMMC_INIT_OVER_AP > I'm not sure we should be doing this by default. […] agree. https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/include/soc/i… File src/soc/intel/skylake/include/soc/iomap.h: https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/include/soc/i… PS3, Line 79: #define EMMC_BASE_ADDRESS 0xfe601000 > How is this fixed? I thought the emmc controller is a normal pci device that gets resources assigned […] thats true but as we are doing emmc init in parallel to PCI enumeration hence we might need to maintain the same BAR for emmc controller. here is fixed BAR allocation logic https://review.coreboot.org/#/c/coreboot/+/23703/9/src/soc/intel/common/blo… -- To view, visit https://review.coreboot.org/c/coreboot/+/23705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd1ae0bacf3034a09313ff32d4197809b5397d1 Gerrit-Change-Number: 23705 Gerrit-PatchSet: 3 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 18 Jan 2019 16:36:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: spi/flash: Add interface to check software write protection
by Philipp Deppenwiese (Code Review) 18 Jan '19

18 Jan '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27987 ) Change subject: spi/flash: Add interface to check software write protection ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/27987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a2b75f5c0f183a74d42180dfc0c12d50b9780bb Gerrit-Change-Number: 27987 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Fri, 18 Jan 2019 16:35:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/stoneyridge: Access SMBUS through MMIO
by Richard Spiegel (Code Review) 18 Jan '19

18 Jan '19

Hello Marshall Dawson, Paul Menzel, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29258 to look at the new patch set (#12). Change subject: soc/amd/stoneyridge: Access SMBUS through MMIO ...................................................................... soc/amd/stoneyridge: Access SMBUS through MMIO Currently SMBUS registers are accessed through IO, but with stoneyridge they can be accessed through MMIO. This reduces the time of execution by a tiny amount (MMIO write is faster than IO write, though MMIO read is about as fast as IO read) as most of the time consumed is actually transaction time. Convert code to MMIO access. BUG=b:117754784 TEST=Used IO to write and MMIO to read, to confirm a one to one relationship between IO and MMIO. Then build and boot grunt. Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/smbus.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/smbus.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/southbridge.c 8 files changed, 135 insertions(+), 134 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29258/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/29258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Gerrit-Change-Number: 29258 Gerrit-PatchSet: 12 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/skylake: Use common EMMC block code
by Aaron Durbin (Code Review) 18 Jan '19

18 Jan '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23705 ) Change subject: soc/intel/skylake: Use common EMMC block code ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/Kconfig File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/Kconfig@63 PS3, Line 63: select SOC_INTEL_COMMON_BLOCK_EMMC_INIT_OVER_AP I'm not sure we should be doing this by default. It should be a choice by the mainboard at the very least. https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/include/soc/i… File src/soc/intel/skylake/include/soc/iomap.h: https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/include/soc/i… PS3, Line 79: #define EMMC_BASE_ADDRESS 0xfe601000 How is this fixed? I thought the emmc controller is a normal pci device that gets resources assigned to it. -- To view, visit https://review.coreboot.org/c/coreboot/+/23705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd1ae0bacf3034a09313ff32d4197809b5397d1 Gerrit-Change-Number: 23705 Gerrit-PatchSet: 3 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 18 Jan 2019 16:14:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/stoneyridge: Access SMBUS through MMIO
by Richard Spiegel (Code Review) 18 Jan '19

18 Jan '19

Hello Marshall Dawson, Paul Menzel, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29258 to look at the new patch set (#11). Change subject: soc/amd/stoneyridge: Access SMBUS through MMIO ...................................................................... soc/amd/stoneyridge: Access SMBUS through MMIO Currently SMBUS registers are accessed through IO, but with stoneyridge they can be accessed through MMIO. This reduces the time of execution by a tiny amount (MMIO write is faster than IO write, though MMIO read is about as fast as IO read) as most of the time consumed is actually transaction time. Convert code to MMIO access. BUG=b:117754784 TEST=Used IO to write and MMIO to read, to confirm a one to one relationship between IO and MMIO. Then build and boot grunt. Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/smbus.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/smbus.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/southbridge.c 8 files changed, 138 insertions(+), 134 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29258/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/29258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Gerrit-Change-Number: 29258 Gerrit-PatchSet: 11 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/haswell: Enable PCIe on the processor
by Iru Cai (vimacs) (Code Review) 18 Jan '19

18 Jan '19

Iru Cai (vimacs) has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30268 ) Change subject: nb/intel/haswell: Enable PCIe on the processor ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcb017eceef73553fc230c60d08b7d61a1796fce Gerrit-Change-Number: 30268 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit January 2019