coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet spec
by Dtrain Hsu (Code Review) 18 Jan '19

18 Jan '19

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30949 Change subject: mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet spec ...................................................................... mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet spec After adjustment on Sarien EVT TS: 380.7 KHz TP: 379.3 KHz H1: 392.2 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/30949/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b590bac..425881a 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -75,17 +75,19 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 190, + .fall_time_ns = 120, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 176, - .fall_time_ns = 15, + .rise_time_ns = 52, + .fall_time_ns = 110, }, .i2c[4] = { .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 280, - .fall_time_ns = 90, + .rise_time_ns = 36, + .fall_time_ns = 99, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/30949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f Gerrit-Change-Number: 30949 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Untangle CBFS microcode updates
by Subrata Banik (Code Review) 17 Jan '19

17 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29934 ) Change subject: Untangle CBFS microcode updates ...................................................................... Patch Set 9: > > Patch Set 9: > > > > > Patch Set 9: > > > > > > > This seems to have broken mb/googl/{sarien,arcada}. I'm not > sure what's the root cause, but I just wanted to note this in here. > We might need to flip a local config value in chromium. > > > > > > Hi Aaron, > > > > > > is it failing to build or to boot? > > > > boot > > > > > > > > Is that Cannon Lake or Coffee Lake? In the former case, you > > > still need an external microcode binary. The Kconfig symbol > > > for that case was renamed from CPU_MICROCODE_CBFS_GENERATE > > > to CPU_MICROCODE_CBFS_EXTERNAL_BINS. > > > > > > Might also still be needed for some Coffee Lake steppings. > > > > It's whiskey lake which is using one of those two. I can't > remember which honestly. I suspect it's an issue w/ an > uncoordinated flag setting change. Once hear exact root cause I'll > update. > > At least one report was an unsynchronized setting change. So we're > good so far there. this CL is required https://chromium-review.googlesource.com/c/chromiumos/overlays/chromiumos-o… -- To view, visit https://review.coreboot.org/c/coreboot/+/29934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Gerrit-Change-Number: 29934 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Jan 2019 02:33:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: aaaaaa
by wang qii (Code Review) 17 Jan '19

17 Jan '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30983 Change subject: aaaaaa ...................................................................... aaaaaa Change-Id: I1ab1f44b61731d3c38280fc3b9b5a859a4bb23fc Signed-off-by: Qii Wang <qii.wang(a)mediatek.com> --- A aaaa 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30983/1 diff --git a/aaaa b/aaaa new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/aaaa -- To view, visit https://review.coreboot.org/c/coreboot/+/30983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab1f44b61731d3c38280fc3b9b5a859a4bb23fc Gerrit-Change-Number: 30983 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [NOTFORMERGE] mb/lenovo/t400: Remove false docking events
by ycmwfexy (Code Review) 17 Jan '19

17 Jan '19

ycmwfexy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20908 ) Change subject: [NOTFORMERGE] mb/lenovo/t400: Remove false docking events ...................................................................... Patch Set 2: Probably not after those two changes here: https://review.coreboot.org/c/coreboot/+/29418 https://review.coreboot.org/c/coreboot/+/30397 In the second of those changes the Q37 and Q50 events are also removed. -- To view, visit https://review.coreboot.org/c/coreboot/+/20908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I327002f5626316948c806f4afcb6466575ffc55c Gerrit-Change-Number: 20908 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: ycmwfexy <ycmwfexy(a)sharklasers.com> Gerrit-Comment-Date: Thu, 17 Jan 2019 22:41:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/wilco: Turn on wake up from lid
by Lijian Zhao (Code Review) 17 Jan '19

17 Jan '19

Hello Subrata Banik, Duncan Laurie, Bora Guvendik, build bot (Jenkins), Hannah Williams, Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30824 to look at the new patch set (#6). Change subject: ec/google/wilco: Turn on wake up from lid ...................................................................... ec/google/wilco: Turn on wake up from lid Send required EC command to enable ACPI S3 wake up from lid switch. BUG=b:120748824 TEST=Put Sarien system into S3 and then wake up from lid switch successful. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/ec/google/wilco/commands.c M src/ec/google/wilco/commands.h M src/ec/google/wilco/smihandler.c 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/30824/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/30824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Gerrit-Change-Number: 30824 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [NOTFORMERGE]mb/lenovo/t400: Quick and dirty dock hotplug support
by ycmwfexy (Code Review) 17 Jan '19

17 Jan '19

ycmwfexy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/19552 ) Change subject: [NOTFORMERGE]mb/lenovo/t400: Quick and dirty dock hotplug support ...................................................................... Patch Set 7: Probably not after those two changes here: https://review.coreboot.org/c/coreboot/+/29418 https://review.coreboot.org/c/coreboot/+/30397 -- To view, visit https://review.coreboot.org/c/coreboot/+/19552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9676880540fe9e4c84c6fd47b8c85e76f54a8a68 Gerrit-Change-Number: 19552 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: ycmwfexy <ycmwfexy(a)sharklasers.com> Gerrit-Comment-Date: Thu, 17 Jan 2019 22:38:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by ycmwfexy (Code Review) 17 Jan '19

17 Jan '19

ycmwfexy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... Patch Set 12: Information for the future users: Be careful if you want to buy this board. I know of at least 5 different versions that look really familiar but are not the same and would maybe require changes to coreboot to run fine. The board that have now coreboot support is: https://www.asus.com/de/Motherboards/P5G41TM_LX/ The exact model number of the supported board is: 'ASUS P5G41T-M LX' Other boards that look and their model number looks similar but are probably untested/unsupported: 'ASUS P5G41T-M' (Its missing the parallel port but have a digital audio out) 'ASUS P5G41T-M LX2' (Its missing the parallel port) 'ASUS P5G41T-M LX3' (Its missing the parallel port) 'ASUS P5G41T-M LE' (Its missing the parallel and serial port, but have DVI output) 'ASUS P5G41T-M SI' (It differ more, have HDMI, DVI, 4 DIMM-slots (probably for 4 single sided dimms - recently unsupported by coreboot)) If the 'T' in the model name is missing, then its probably a DDR2 version. Coreboot images for the G41 chipset contain both DDR2 and DDR3 raminit. But its unknown if the only difference is DDR2/DDR3 slots. -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 12 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ycmwfexy <ycmwfexy(a)sharklasers.com> Gerrit-Comment-Date: Thu, 17 Jan 2019 22:30:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/wilco: Turn on wake up from lid
by Lijian Zhao (Code Review) 17 Jan '19

17 Jan '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30824 ) Change subject: ec/google/wilco: Turn on wake up from lid ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/30824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Gerrit-Change-Number: 30824 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 22:11:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/stoneyridge/gpio: Configure debounce for irq gpios
by Daniel Kurtz (Code Review) 17 Jan '19

17 Jan '19

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30921 to review the following change. Change subject: soc/amd/stoneyridge/gpio: Configure debounce for irq gpios ...................................................................... soc/amd/stoneyridge/gpio: Configure debounce for irq gpios FT4 has a strange property where whenever the debounce registers for any one gpio are changed, the FT4 disables interrupt propagation for ALL gpio irqs for ~4ms. In other words, if an edge interrupt of one gpio happens exactly during this debounce-irq-off window immediately following the configuration of another gpio, the interrupt will be lost. It is quite difficult to deal with this in the kernel, since during kernel boot time, drivers & devices are probed asynchronously, meaning it may happen that an already loaded driver may miss an interrupt when some later driver is being probed and configuring its gpio interrupt. To eliminate this possibility, we pre-configure the debounce registers in ram stage for all gpios that will be used as irqs later by the kernel using the same configuration as used by the kernel, as per this table: IRQ Debounce Edge Remove Glitch Level High Preserve Low Glitch Level Low Preserve High Glitch Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready Change-Id: I94c7ecfb14e5bb209b3598e10287c80eb19da25b --- M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30921/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 955cc6a..bca8f5d 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -219,12 +219,41 @@ return gpio; } +/* + * Returns the debounce type corresponding to a given interrupt type. + * + * This matches what the linux kernel will set during gpio configuration: + * + * Interrupt Debounce + * Edge Remove Glitch + * Level High Preserve Low Glitch + * Level Low Preserve High Glitch + */ +static uint32_t gpio_irq_debounce(uint32_t flag) +{ + uint32_t trigger; + + trigger = flag & FLAGS_TRIGGER_MASK; + switch (trigger) { + case GPIO_TRIGGER_LEVEL_LOW: + return GPIO_IN_PRESERVE_HIGH_GLITCH; + case GPIO_TRIGGER_LEVEL_HIGH: + return GPIO_IN_PRESERVE_LOW_GLITCH; + case GPIO_TRIGGER_EDGE_LOW: + return GPIO_IN_REMOVE_GLITCH; + case GPIO_TRIGGER_EDGE_HIGH: + return GPIO_IN_REMOVE_GLITCH; + default: + return GPIO_IN_NO_DEBOUNCE; + } +} + void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { uint8_t *mux_ptr; uint32_t *gpio_ptr; uint32_t control, control_flags, edge_level, direction; - uint32_t mask, bit_edge, bit_level; + uint32_t mask, bit_edge, bit_level, debounce; uint8_t mux, index, gpio; int gevent_num; @@ -273,6 +302,10 @@ case GPIO_SCI_FLAG: mem_read_write32(gpio_ptr, control, INT_SCI_SMI_MASK); + /* Always set debounce type for SCI gpio */ + debounce = gpio_irq_debounce(control_flags); + mem_read_write32(gpio_ptr, debounce, + GPIO_DEBOUNCE_MASK); get_sci_config_bits(control_flags, &bit_edge, &bit_level); edge_level |= bit_edge << gevent_num; diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 04eda49..422ee57 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -450,9 +450,11 @@ #define INT_SCI_SMI_MASK 0x00f40000 #define IN_GLITCH_SHIFT 5 +#define DEBOUNCE_NONE 0 #define GLITCH_LOW 1 #define GLITCH_HIGH 2 #define GLITCH_NONE 3 +#define GPIO_IN_NO_DEBOUNCE (DEBOUNCE_NONE << IN_GLITCH_SHIFT) #define GPIO_IN_PRESERVE_LOW_GLITCH (GLITCH_LOW << IN_GLITCH_SHIFT) #define GPIO_IN_PRESERVE_HIGH_GLITCH (GLITCH_HIGH << IN_GLITCH_SHIFT) #define GPIO_IN_REMOVE_GLITCH (GLITCH_NONE << IN_GLITCH_SHIFT) -- To view, visit https://review.coreboot.org/c/coreboot/+/30921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c7ecfb14e5bb209b3598e10287c80eb19da25b Gerrit-Change-Number: 30921 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: crossgcc/buildgcc: Mention parallel build options
by Angel Pons (Code Review) 17 Jan '19

17 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20449 ) Change subject: crossgcc/buildgcc: Mention parallel build options ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Nice idea. Sharing (compiling work between cores) is caring :) https://review.coreboot.org/#/c/20449/3/util/crossgcc/buildgcc File util/crossgcc/buildgcc: https://review.coreboot.org/#/c/20449/3/util/crossgcc/buildgcc@996 PS3, Line 996: with `CPUS` or `--jobs This doesn't make much sense https://review.coreboot.org/#/c/20449/3/util/crossgcc/buildgcc@997 PS3, Line 997: ( Unmatched parenthesis -- To view, visit https://review.coreboot.org/c/coreboot/+/20449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I934a45bd6eb978ee08caa55797254831f4ddfac2 Gerrit-Change-Number: 20449 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 21:29:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2019