coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by You-Cheng Syu (Code Review) 21 Jan '19

21 Jan '19

Hello Julius Werner, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Chun-ta Lin, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30331 to look at the new patch set (#6). Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... google/kukui: Move some initialization from bootblock to verstage MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/verstage.c 4 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30331/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 6 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mediatek/mt8183: Move some initialization to verstage if possible
by You-Cheng Syu (Code Review) 21 Jan '19

21 Jan '19

You-Cheng Syu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30330 ) Change subject: mediatek/mt8183: Move some initialization to verstage if possible ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d482f06a8cc97be0c390ed863aa3ac05d4a3459 Gerrit-Change-Number: 30330 Gerrit-PatchSet: 5 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: security/vboot: Add new hook function verstage_soc_init
by You-Cheng Syu (Code Review) 21 Jan '19

21 Jan '19

You-Cheng Syu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30351 ) Change subject: security/vboot: Add new hook function verstage_soc_init ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31a43ae42f828a9439c03433cba19631b96408ff Gerrit-Change-Number: 30351 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sb/intel/common: Show Add EC firmware only for boards that need it
by Jan Tatje (Code Review) 21 Jan '19

21 Jan '19

Jan Tatje has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30697 Change subject: sb/intel/common: Show Add EC firmware only for boards that need it ...................................................................... sb/intel/common: Show Add EC firmware only for boards that need it Most boards currently do not use EC firmware from SPI flash in the IFD, this hides this option by default and shows it only for boards that need it. A new config variable CAN_HAVE_EC_BIN is introduced to enable this option for boards that need it. Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7 Signed-off-by: Jan Tatje <jan(a)jnt.io> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/intel/cannonlake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/icelake_rvp/Kconfig M src/southbridge/intel/common/firmware/Kconfig 6 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/30697/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 711d2e9..8e185fa 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COFFEELAKE select SYSTEM_TYPE_LAPTOP + select CAN_HAVE_EC_BIN if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index c0bd1d8..f317886 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -22,6 +22,7 @@ select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP select TPM2 + select CAN_HAVE_EC_BIN if BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index 028d493..683e53c 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -11,6 +11,7 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select SOC_INTEL_CANNONLAKE + select CAN_HAVE_EC_BIN config MAINBOARD_DIR string diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 7597629..beb9cb9 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -16,6 +16,7 @@ select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP + select CAN_HAVE_EC_BIN config MAINBOARD_DIR string diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 0741bf8..788dae5 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -13,6 +13,7 @@ select DRIVERS_USB_ACPI select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_ICELAKE + select CAN_HAVE_EC_BIN config MAINBOARD_DIR string diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 97fb993..0fbb9b9 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -120,8 +120,11 @@ depends on HAVE_GBE_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" +config CAN_HAVE_EC_BIN + def_bool n + config HAVE_EC_BIN - bool "Add EC firmware" + bool "Add EC firmware" if CAN_HAVE_EC_BIN depends on HAVE_IFD_BIN help The embedded controller needs a firmware file. -- To view, visit https://review.coreboot.org/c/coreboot/+/30697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7 Gerrit-Change-Number: 30697 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Tatje Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/variants: Disable xHCI compliance mode for Fleex
by Amanda Hwang (Code Review) 20 Jan '19

20 Jan '19

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30984 Change subject: mb/google/octopus/variants: Disable xHCI compliance mode for Fleex ...................................................................... mb/google/octopus/variants: Disable xHCI compliance mode for Fleex Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:120009029 TEST=Verified usb operation successfully. Change-Id: Ic7fa08c894397598dee3c4ff9a764e43383a0627 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30984/1 diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index a6df66b..19246e0 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -140,4 +140,7 @@ end end # - I2C 7 end + + # Disable compliance mode + register "DisableComplianceMode" = "1" end -- To view, visit https://review.coreboot.org/c/coreboot/+/30984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7fa08c894397598dee3c4ff9a764e43383a0627 Gerrit-Change-Number: 30984 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/variants/meep: Disable xHCI compliance mode
by Chen Wisley (Code Review) 20 Jan '19

20 Jan '19

Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30948 to review the following change. Change subject: mb/google/octopus/variants/meep: Disable xHCI compliance mode ...................................................................... mb/google/octopus/variants/meep: Disable xHCI compliance mode Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BUG=b:122671995 TEST=check "Disable Link Compliance Mode" bit of "SuperSpeed Port Link control" register and usb operation successfully. Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/octopus/variants/meep/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30948/1 diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index f531d13..f7aeac1 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -112,4 +112,7 @@ end end # - I2C 7 end + + # Disable compliance mode + register "DisableComplianceMode" = "1" end -- To view, visit https://review.coreboot.org/c/coreboot/+/30948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec Gerrit-Change-Number: 30948 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell: Use DEVICE_NOOP
by Patrick Georgi (Code Review) 20 Jan '19

20 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29857 ) Change subject: src/soc/intel/braswell: Use DEVICE_NOOP ...................................................................... src/soc/intel/braswell: Use DEVICE_NOOP Use already defined DEVICE_NOOP instead. Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/29857 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/braswell/chip.c 1 file changed, 3 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 7a63b5b..b7f6d4d 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -37,12 +37,10 @@ .scan_bus = pci_domain_scan_bus, }; -static void cpu_bus_noop(struct device *dev) { } - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, .init = soc_init_cpus }; -- To view, visit https://review.coreboot.org/c/coreboot/+/29857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Gerrit-Change-Number: 29857 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: inteltool: add support for 8 Series/C220 Series Chipset
by Iru Cai (vimacs) (Code Review) 19 Jan '19

19 Jan '19

Iru Cai (vimacs) has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/21213 ) Change subject: inteltool: add support for 8 Series/C220 Series Chipset ...................................................................... Abandoned LynxPoint is in inteltool now -- To view, visit https://review.coreboot.org/c/coreboot/+/21213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ec155f67c7b6eda47557d00a3d0bcfe4ef98d08 Gerrit-Change-Number: 21213 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sdm845: Add QUPv3 FW load & config
by Julius Werner (Code Review) 18 Jan '19

18 Jan '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25372 ) Change subject: sdm845: Add QUPv3 FW load & config ...................................................................... Patch Set 63: (3 comments) https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… File src/mainboard/google/cheza/qupv3_config.c: https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… PS6, Line 18: struct se_cfg se_mappings[QUPV3_SE_MAX] = > Is the loading of FW from respective protocol init function is needed for OTA upgrade OR something else in terms design ? Not sure if I understand what you're asking... we definitely want to preserve the ability to update QUP firmware with an RW update where possible. That's why I was asking if it was possible to load the firmware again after it has already been loaded (without rebooting the whole SoC)... because we have to load some QUPs (like EC and TPM SPI) in RO firmware, but then we might want to reload a newer version after we have jumped to RW firmware. This would be a bit easier if each QUP was loaded individually from the respective driver function. However, we can also do the single table approach now and then write a new function to overwrite a single QUP if the need for such an RW update ever actually comes up after shipping. https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/include/soc… File src/soc/qualcomm/sdm845/include/soc/qupv3_fw_config.h: https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/include/soc… PS6, Line 65: bool dfs_mode; > But modes aren't directly depends on the protocol, for example, SPI can be operated in FIFO as well as DMA mode so, I am keeping that in latest patch. It looks like we just always want MIXED in practice (except for UART), though? Does MIXED just mean you can do either FIFO or DMA? And since this needs to work for the kernel and we don't know what kind of access the kernel would want to do we'll always end up wanting MIXED? In that case, we can hardcode it. https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… File src/soc/qualcomm/sdm845/qupv3_fw_config.c: https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… PS6, Line 227: /* HPG section 3.1.7.1 */ > We cannot directly release it to you, our tech release team will take care of that. […] Yes, please initiate a request with your tech team. -- To view, visit https://review.coreboot.org/c/coreboot/+/25372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e87f868ecbe2a8e51d94c045ad76b99bb1b345d Gerrit-Change-Number: 25372 Gerrit-PatchSet: 63 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Jan 2019 23:49:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Add UART for sdm845
by Julius Werner (Code Review) 18 Jan '19

18 Jan '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25817 ) Change subject: libpayload: Add UART for sdm845 ...................................................................... Patch Set 53: (1 comment) https://review.coreboot.org/#/c/25817/53/payloads/libpayload/drivers/serial… File payloads/libpayload/drivers/serial/sdm845.c: https://review.coreboot.org/#/c/25817/53/payloads/libpayload/drivers/serial… PS53, Line 267: { BTW, I think you asked a while ago why you still see depthcharge UART output even when building a production image, T.mike. The reason is that this should have a check for (lib_sysinfo.serial == NULL) and not register the console driver in that case, like all the other serial drivers here. (I'm not gonna review this driver further until there is some movement on CB:25373, since there is a lot of overlap.) -- To view, visit https://review.coreboot.org/c/coreboot/+/25817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb982bccd489048833a78b6f8c5a903e5d3cdf94 Gerrit-Change-Number: 25817 Gerrit-PatchSet: 53 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Jan 2019 22:45:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019