coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

1 participants
1296 discussions

Change in ...coreboot[master]: nb/intel/x4x: Use parallel MP init
by Angel Pons (Code Review) 21 Jan '19

21 Jan '19

Angel Pons has uploaded a new patch set (#40) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/25601 ) Change subject: nb/intel/x4x: Use parallel MP init ...................................................................... nb/intel/x4x: Use parallel MP init Use parallel MP init code to initialize all AP's. Also remove guards around CPU code where all platforms now use parallel MP init. Tested on Intel DG41WV, shaves off about 90ms on a quad core. Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/model_f4x/model_f4x_init.c M src/mainboard/asrock/g41c-gs/cmos.layout M src/mainboard/foxconn/g41s-k/cmos.layout M src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/i82801jx/lpc.c 9 files changed, 2 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/25601/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/25601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921 Gerrit-Change-Number: 25601 Gerrit-PatchSet: 40 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios"
by Raul Rangel (Code Review) 21 Jan '19

21 Jan '19

Hello Daniel Kurtz, build bot (Jenkins), Daniel Kurtz, Martin Roth, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30981 to review the following change. Change subject: Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios" ...................................................................... Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios" This reverts commit b82afce18aff24b6e5e3b73a67a6533cc4865a26. Reason for revert: This causes depthcharge to not boot due to TPM timeout errors. Because there is no wait after setting the debounce register, we lose data because the read-modify-write loses the interrupt status bit. e.g., GPIO 5 sets debounce, without a wait. Then GPIO 9 has it's debounce set. Because the interrupt controller is masking the interrupt enable status bit, the read-modify-write for GPIO9 loses the interrupt enable status bit and it never gets set again. This causes the interrupt to never latch. We should possibly make depthcharge set the interrupt enable status bit for latched GPIOs. Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8 --- M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 1 insertion(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/30981/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index bca8f5d..955cc6a 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -219,41 +219,12 @@ return gpio; } -/* - * Returns the debounce type corresponding to a given interrupt type. - * - * This matches what the linux kernel will set during gpio configuration: - * - * Interrupt Debounce - * Edge Remove Glitch - * Level High Preserve Low Glitch - * Level Low Preserve High Glitch - */ -static uint32_t gpio_irq_debounce(uint32_t flag) -{ - uint32_t trigger; - - trigger = flag & FLAGS_TRIGGER_MASK; - switch (trigger) { - case GPIO_TRIGGER_LEVEL_LOW: - return GPIO_IN_PRESERVE_HIGH_GLITCH; - case GPIO_TRIGGER_LEVEL_HIGH: - return GPIO_IN_PRESERVE_LOW_GLITCH; - case GPIO_TRIGGER_EDGE_LOW: - return GPIO_IN_REMOVE_GLITCH; - case GPIO_TRIGGER_EDGE_HIGH: - return GPIO_IN_REMOVE_GLITCH; - default: - return GPIO_IN_NO_DEBOUNCE; - } -} - void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { uint8_t *mux_ptr; uint32_t *gpio_ptr; uint32_t control, control_flags, edge_level, direction; - uint32_t mask, bit_edge, bit_level, debounce; + uint32_t mask, bit_edge, bit_level; uint8_t mux, index, gpio; int gevent_num; @@ -302,10 +273,6 @@ case GPIO_SCI_FLAG: mem_read_write32(gpio_ptr, control, INT_SCI_SMI_MASK); - /* Always set debounce type for SCI gpio */ - debounce = gpio_irq_debounce(control_flags); - mem_read_write32(gpio_ptr, debounce, - GPIO_DEBOUNCE_MASK); get_sci_config_bits(control_flags, &bit_edge, &bit_level); edge_level |= bit_edge << gevent_num; diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 422ee57..04eda49 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -450,11 +450,9 @@ #define INT_SCI_SMI_MASK 0x00f40000 #define IN_GLITCH_SHIFT 5 -#define DEBOUNCE_NONE 0 #define GLITCH_LOW 1 #define GLITCH_HIGH 2 #define GLITCH_NONE 3 -#define GPIO_IN_NO_DEBOUNCE (DEBOUNCE_NONE << IN_GLITCH_SHIFT) #define GPIO_IN_PRESERVE_LOW_GLITCH (GLITCH_LOW << IN_GLITCH_SHIFT) #define GPIO_IN_PRESERVE_HIGH_GLITCH (GLITCH_HIGH << IN_GLITCH_SHIFT) #define GPIO_IN_REMOVE_GLITCH (GLITCH_NONE << IN_GLITCH_SHIFT) -- To view, visit https://review.coreboot.org/c/coreboot/+/30981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8 Gerrit-Change-Number: 30981 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: util/inteltool: Add support for Denverton
by Felix Singer (Code Review) 21 Jan '19

21 Jan '19

Hello Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30887 to review the following change. Change subject: util/inteltool: Add support for Denverton ...................................................................... util/inteltool: Add support for Denverton Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/Makefile A util/inteltool/dnv_gpio.c A util/inteltool/dnv_gpio.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 212 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30887/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d88063b..6d0beb8 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -28,7 +28,7 @@ CPPFLAGS += -I$(top)/src/commonlib/include OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o dnv_gpio.o\ OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/dnv_gpio.c b/util/inteltool/dnv_gpio.c new file mode 100644 index 0000000..4249f4c --- /dev/null +++ b/util/inteltool/dnv_gpio.c @@ -0,0 +1,189 @@ +#include "dnv_gpio.h" +#include "pcr.h" +#include <stdio.h> +#include <stdint.h> + +char *names_c2[] = { + "NORTH_ALL_GBE0_SDP0", + "NORTH_ALL_GBE1_SDP0", + "NORTH_ALL_GBE0_SDP1", + "NORTH_ALL_GBE1_SDP1", + "NORTH_ALL_GBE0_SDP2", + "NORTH_ALL_GBE1_SDP2", + "NORTH_ALL_GBE0_SDP3", + "NORTH_ALL_GBE1_SDP3", + "NORTH_ALL_GBE2_LED0", + "NORTH_ALL_GBE2_LED1", + "NORTH_ALL_GBE0_I2C_CLK", + "NORTH_ALL_GBE0_I2C_DATA", + "NORTH_ALL_GBE1_I2C_CLK", + "NORTH_ALL_GBE1_I2C_DATA", + "NORTH_ALL_NCSI_RXD0", + "NORTH_ALL_NCSI_CLK_IN", + "NORTH_ALL_NCSI_RXD1", + "NORTH_ALL_NCSI_CRS_DV", + "NORTH_ALL_NCSI_ARB_IN", + "NORTH_ALL_NCSI_TX_EN", + "NORTH_ALL_NCSI_TXD0", + "NORTH_ALL_NCSI_TXD1", + "NORTH_ALL_NCSI_ARB_OUT", + "NORTH_ALL_GBE0_LED0", + "NORTH_ALL_GBE0_LED1", + "NORTH_ALL_GBE1_LED0", + "NORTH_ALL_GBE1_LED1", + "NORTH_ALL_GPIO_0", + "NORTH_ALL_PCIE_CLKREQ0_N", + "NORTH_ALL_PCIE_CLKREQ1_N", + "NORTH_ALL_PCIE_CLKREQ2_N", + "NORTH_ALL_PCIE_CLKREQ3_N", + "NORTH_ALL_PCIE_CLKREQ4_N", + "NORTH_ALL_GPIO_1", + "NORTH_ALL_GPIO_2", + "NORTH_ALL_SVID_ALERT_N", + "NORTH_ALL_SVID_DATA", + "NORTH_ALL_SVID_CLK", + "NORTH_ALL_THERMTRIP_N", + "NORTH_ALL_PROCHOT_N", + "NORTH_ALL_MEMHOT_N", +}; + +char *names_c5[] = { + "SOUTH_DFX_DFX_PORT_CLK0", + "SOUTH_DFX_DFX_PORT_CLK1", + "SOUTH_DFX_DFX_PORT0", + "SOUTH_DFX_DFX_PORT1", + "SOUTH_DFX_DFX_PORT2", + "SOUTH_DFX_DFX_PORT3", + "SOUTH_DFX_DFX_PORT4", + "SOUTH_DFX_DFX_PORT5", + "SOUTH_DFX_DFX_PORT6", + "SOUTH_DFX_DFX_PORT7", + "SOUTH_DFX_DFX_PORT8", + "SOUTH_DFX_DFX_PORT9", + "SOUTH_DFX_DFX_PORT10", + "SOUTH_DFX_DFX_PORT11", + "SOUTH_DFX_DFX_PORT12", + "SOUTH_DFX_DFX_PORT13", + "SOUTH_DFX_DFX_PORT14", + "SOUTH_DFX_DFX_PORT15", + "SOUTH_GROUP0_GPIO_12", + "SOUTH_GROUP0_SMB5_GBE_ALRT_N", + "SOUTH_GROUP0_PCIE_CLKREQ5_N", + "SOUTH_GROUP0_PCIE_CLKREQ6_N", + "SOUTH_GROUP0_PCIE_CLKREQ7_N", + "SOUTH_GROUP0_UART0_RXD", + "SOUTH_GROUP0_UART0_TXD", + "SOUTH_GROUP0_SMB5_GBE_CLK", + "SOUTH_GROUP0_SMB5_GBE_DATA", + "SOUTH_GROUP0_ERROR2_N", + "SOUTH_GROUP0_ERROR1_N", + "SOUTH_GROUP0_ERROR0_N", + "SOUTH_GROUP0_IERR_N", + "SOUTH_GROUP0_MCERR_N", + "SOUTH_GROUP0_SMB0_LEG_CLK", + "SOUTH_GROUP0_SMB0_LEG_DATA", + "SOUTH_GROUP0_SMB0_LEG_ALRT_N", + "SOUTH_GROUP0_SMB1_HOST_DATA", + "SOUTH_GROUP0_SMB1_HOST_CLK", + "SOUTH_GROUP0_SMB2_PECI_DATA", + "SOUTH_GROUP0_SMB2_PECI_CLK", + "SOUTH_GROUP0_SMB4_CSME0_DATA", + "SOUTH_GROUP0_SMB4_CSME0_CLK", + "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", + "SOUTH_GROUP0_USB_OC0_N", + "SOUTH_GROUP0_FLEX_CLK_SE0", + "SOUTH_GROUP0_FLEX_CLK_SE1", + "SOUTH_GROUP0_GPIO_4", + "SOUTH_GROUP0_GPIO_5", + "SOUTH_GROUP0_GPIO_6", + "SOUTH_GROUP0_GPIO_7", + "SOUTH_GROUP0_SATA0_LED_N", + "SOUTH_GROUP0_SATA1_LED_N", + "SOUTH_GROUP0_SATA_PDETECT0", + "SOUTH_GROUP0_SATA_PDETECT1", + "SOUTH_GROUP0_SATA0_SDOUT", + "SOUTH_GROUP0_SATA1_SDOUT", + "SOUTH_GROUP0_UART1_RXD", + "SOUTH_GROUP0_UART1_TXD", + "SOUTH_GROUP0_GPIO_8", + "SOUTH_GROUP0_GPIO_9", + "SOUTH_GROUP0_TCK", + "SOUTH_GROUP0_TRST_N", + "SOUTH_GROUP0_TMS", + "SOUTH_GROUP0_TDI", + "SOUTH_GROUP0_TDO", + "SOUTH_GROUP0_CX_PRDY_N", + "SOUTH_GROUP0_CX_PREQ_N", + "SOUTH_GROUP0_CTBTRIGINOUT", + "SOUTH_GROUP0_CTBTRIGOUT", + "SOUTH_GROUP0_DFX_SPARE2", + "SOUTH_GROUP0_DFX_SPARE3", + "SOUTH_GROUP0_DFX_SPARE4", + "SOUTH_GROUP1_SUSPWRDNACK", + "SOUTH_GROUP1_PMU_SUSCLK", + "SOUTH_GROUP1_ADR_TRIGGER", + "SOUTH_GROUP1_PMU_SLP_S45_N", + "SOUTH_GROUP1_PMU_SLP_S3_N", + "SOUTH_GROUP1_PMU_WAKE_N", + "SOUTH_GROUP1_PMU_PWRBTN_N", + "SOUTH_GROUP1_PMU_RESETBUTTON_N", + "SOUTH_GROUP1_PMU_PLTRST_N", + "SOUTH_GROUP1_SUS_STAT_N", + "SOUTH_GROUP1_SLP_S0IX_N", + "SOUTH_GROUP1_SPI_CS0_N", + "SOUTH_GROUP1_SPI_CS1_N", + "SOUTH_GROUP1_SPI_MOSI_IO0", + "SOUTH_GROUP1_SPI_MISO_IO1", + "SOUTH_GROUP1_SPI_IO2", + "SOUTH_GROUP1_SPI_IO3", + "SOUTH_GROUP1_SPI_CLK", + "SOUTH_GROUP1_SPI_CLK_LOOPBK", + "SOUTH_GROUP1_ESPI_IO0", + "SOUTH_GROUP1_ESPI_IO1", + "SOUTH_GROUP1_ESPI_IO2", + "SOUTH_GROUP1_ESPI_IO3", + "SOUTH_GROUP1_ESPI_CS0_N", + "SOUTH_GROUP1_ESPI_CLK", + "SOUTH_GROUP1_ESPI_RST_N", + "SOUTH_GROUP1_ESPI_ALRT0_N", + "SOUTH_GROUP1_GPIO_10", + "SOUTH_GROUP1_GPIO_11", + "SOUTH_GROUP1_ESPI_CLK_LOOPBK", + "SOUTH_GROUP1_EMMC_CMD", + "SOUTH_GROUP1_EMMC_STROBE", + "SOUTH_GROUP1_EMMC_CLK", + "SOUTH_GROUP1_EMMC_D0", + "SOUTH_GROUP1_EMMC_D1", + "SOUTH_GROUP1_EMMC_D2", + "SOUTH_GROUP1_EMMC_D3", + "SOUTH_GROUP1_EMMC_D4", + "SOUTH_GROUP1_EMMC_D5", + "SOUTH_GROUP1_EMMC_D6", + "SOUTH_GROUP1_EMMC_D7", + "SOUTH_GROUP1_GPIO_3", +}; + + +void print_dnv_gpio(struct pci_dev *sb) +{ + pcr_init(sb); + + uint16_t offset = 0; + uint32_t dw0 = 0, dw1 = 0; + + for (uint16_t i = 0; i < (uint16_t)ARRAY_SIZE(names_c2); i++) { + offset = 0x400 + i * 8; + dw0 = read_pcr32(0xc2, offset); + dw1 = read_pcr32(0xc2, offset + 4); + + printf("%s\t0x%08x 0x%08x\n", names_c2[i], dw0, dw1); + } + + printf("\n"); + for (size_t i = 0; i < ARRAY_SIZE(names_c5); i++) { + printf("0x%lx %s\n", (0x400 + i * 8), names_c5[i]); + } + + + pcr_cleanup(); +} diff --git a/util/inteltool/dnv_gpio.h b/util/inteltool/dnv_gpio.h new file mode 100644 index 0000000..43b7b57 --- /dev/null +++ b/util/inteltool/dnv_gpio.h @@ -0,0 +1,8 @@ +#ifndef INTELTOOL_DNV_GPIO_H +#define INTELTOOL_DNV_GPIO_H + +#include "inteltool.h" + +void print_dnv_gpio(struct pci_dev *sb); + +#endif diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 9a58ed8..3b62b7a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -27,6 +27,7 @@ #include <errno.h> #include "inteltool.h" #include "pcr.h" +#include "dnv_gpio.h" #ifdef __NetBSD__ #include <machine/sysarch.h> @@ -36,6 +37,7 @@ enum long_only_opts { LONG_OPT_PCR = 0x100, + LONG_OPT_DNV = 0x200, }; /* @@ -266,6 +268,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, "Intel(R) G35 Express Chipset Family" }, @@ -412,6 +415,7 @@ " -a | --all: dump all known (safe) registers\n" " --pcr=PORT_ID: dump all registers of a PCR port\n" " (may be specified max %d times)\n" + " --dnv_gpio: dump Denverton GPIO config\n" "\n", MAX_PCR_PORTS); exit(1); } @@ -430,7 +434,7 @@ int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0; - int show_gpio_diffs = 0; + int show_gpio_diffs = 0, dump_dnv_gpio = 0; size_t pcr_count = 0; uint8_t dump_pcr[MAX_PCR_PORTS]; @@ -454,6 +458,7 @@ {"ahci", 0, 0, 'R'}, {"sgx", 0, 0, 'x'}, {"pcr", required_argument, 0, LONG_OPT_PCR}, + {"dnv_gpio", 0, 0, LONG_OPT_DNV}, {0, 0, 0, 0} }; @@ -540,6 +545,9 @@ exit(1); } break; + case LONG_OPT_DNV: + dump_dnv_gpio = 1; + break; case 'h': case '?': default: @@ -749,6 +757,9 @@ if (pcr_count) print_pcr_ports(sb, dump_pcr, pcr_count); + if (dump_dnv_gpio) + print_dnv_gpio(sb); + /* Clean up */ pcr_cleanup(); if (ahci) diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index d86ba35..fb64811 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -235,6 +235,7 @@ #define CPUID_BAYTRAIL 0x30670 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 +#define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 5d519af..5c97a6c 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -97,6 +97,7 @@ case PCI_DEVICE_ID_INTEL_HM175: case PCI_DEVICE_ID_INTEL_QM175: case PCI_DEVICE_ID_INTEL_CM238: + case PCI_DEVICE_ID_INTEL_DNV_LPC: p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; case PCI_DEVICE_ID_INTEL_APL_LPC: -- To view, visit https://review.coreboot.org/c/coreboot/+/30887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae Gerrit-Change-Number: 30887 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

6 9

Change in ...coreboot[master]: lib/boot_device: Add API for write protect a region
by Patrick Georgi (Code Review) 21 Jan '19

21 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28724 ) Change subject: lib/boot_device: Add API for write protect a region ...................................................................... lib/boot_device: Add API for write protect a region Add API that should be implemented by the boot media drivers for write-protecting a subregion. Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-on: https://review.coreboot.org/c/28724 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/spi/boot_device_rw_nommap.c M src/include/boot_device.h M src/lib/boot_device.c 3 files changed, 74 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index 64d81c5..d01d778 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -108,3 +108,46 @@ return car_get_var_ptr(&sfg); } + +int boot_device_wp_region(struct region_device *rd, + const enum bootdev_prot_type type) +{ + uint32_t ctrlr_pr; + + /* Ensure boot device has been initialized at least once. */ + boot_device_init(); + + const struct spi_flash *boot_dev = boot_device_spi_flash(); + + if (boot_dev == NULL) + return -1; + + if (type == MEDIA_WP) { + if (spi_flash_is_write_protected(boot_dev, + region_device_region(rd)) != 1) { + return spi_flash_set_write_protected(boot_dev, + region_device_region(rd), true, + SPI_WRITE_PROTECTION_REBOOT); + } + + /* Already write protected */ + return 0; + } + + switch (type) { + case CTRLR_WP: + ctrlr_pr = WRITE_PROTECT; + break; + case CTRLR_RP: + ctrlr_pr = READ_PROTECT; + break; + case CTRLR_RWP: + ctrlr_pr = READ_WRITE_PROTECT; + break; + default: + return -1; + } + + return spi_flash_ctrlr_protect_region(boot_dev, + region_device_region(rd), ctrlr_pr); +} diff --git a/src/include/boot_device.h b/src/include/boot_device.h index cc70442..c882968 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -19,6 +19,22 @@ #include <commonlib/region.h> /* + * Boot device region can be protected by 2 sources, media and controller. + * The following modes are identified. It depends on the flash chip and the + * controller if mode is actually supported. + * + * MEDIA_WP : Flash/Boot device enforces write protect + * CTRLR_WP : Controller device enforces write protect + * CTRLR_RP : Controller device enforces read protect + * CTRLR_RWP : Controller device enforces read-write protect + */ +enum bootdev_prot_type { + CTRLR_WP = 1, + CTRLR_RP = 2, + CTRLR_RWP = 3, + MEDIA_WP = 4, +}; +/* * Please note that the read-only boot device may not be coherent with * the read-write boot device. Thus, mixing mmap() and writeat() is * most likely not to work so don't rely on such semantics. @@ -45,6 +61,14 @@ struct region_device *subrd); /* + * Write protect a sub-region of the boot device represented + * by the region device. + * Returns 0 on success, < 0 on error. + */ +int boot_device_wp_region(struct region_device *rd, + const enum bootdev_prot_type type); + +/* * Initialize the boot device. This may be called multiple times within * a stage so boot device implementations should account for this behavior. **/ diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c index efbbedb..429a6d8 100644 --- a/src/lib/boot_device.c +++ b/src/lib/boot_device.c @@ -20,6 +20,13 @@ /* Provide weak do-nothing init. */ } +int __weak boot_device_wp_region(struct region_device *rd, + const enum bootdev_prot_type type) +{ + /* return a failure, make aware WP is not implemented */ + return -1; +} + static int boot_device_subregion(const struct region *sub, struct region_device *subrd, const struct region_device *parent) -- To view, visit https://review.coreboot.org/c/coreboot/+/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 19 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: drivers/spi: Add controller protection type
by Rizwan Qureshi (Code Review) 21 Jan '19

21 Jan '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30559 Change subject: drivers/spi: Add controller protection type ...................................................................... drivers/spi: Add controller protection type Some SPI controllers support both READ and WRITE protection add a variable to teh protect API for the callers to specify the kind of protection that is requested. Also, update the callers and actual protect API implementation. BUG=None BRANCH=None TEST=test that the mrc cache is protected as expected on soraka. Also tried if the read protection is applied correctly. Change-Id: I093884c4768b08a378f21242ac82e430ac013d15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/drivers/mrc_cache/mrc_cache.c M src/drivers/spi/spi_flash.c M src/include/spi-generic.h M src/include/spi_flash.h M src/soc/intel/broadwell/include/soc/spi.h M src/soc/intel/broadwell/spi.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c 7 files changed, 37 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/30559/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 4dd0dbc..20026b7 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -462,7 +462,8 @@ if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) return 0; - return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r); + return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r, + WRITE_PROTECT); } /* Protect mrc region with a Protected Range Register */ diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 57bdaf4..7874d25 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -573,7 +573,8 @@ int spi_flash_ctrlr_protect_region(const struct spi_flash *flash, - const struct region *region) + const struct region *region, + enum ctrlr_prot_type type) { const struct spi_ctrlr *ctrlr; struct region flash_region = { 0 }; @@ -592,7 +593,7 @@ return -1; if (ctrlr->flash_protect) - return ctrlr->flash_protect(flash, region); + return ctrlr->flash_protect(flash, region, type); return -1; } diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index e3e7f82..f071ef0 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -97,6 +97,11 @@ struct spi_flash; +enum ctrlr_prot_type{ + READ_PROTECT = 1, + WRITE_PROTECT = 2, +}; + enum { /* Deduct the command length from the spi_crop_chunk() calculation for sizing a transaction. */ @@ -144,7 +149,8 @@ int (*flash_probe)(const struct spi_slave *slave, struct spi_flash *flash); int (*flash_protect)(const struct spi_flash *flash, - const struct region *region); + const struct region *region, + enum ctrlr_prot_type type); }; /*----------------------------------------------------------------------- diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 09908eb..1498909 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -207,7 +207,8 @@ /* Protect a region of spi flash using its controller, if available. Returns * < 0 on error, else 0 on success. */ int spi_flash_ctrlr_protect_region(const struct spi_flash *flash, - const struct region *region); + const struct region *region, + enum ctrlr_prot_type type); /* * This function is provided to support spi flash command-response transactions. diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h index 588af17..5ad62fd 100644 --- a/src/soc/intel/broadwell/include/soc/spi.h +++ b/src/soc/intel/broadwell/include/soc/spi.h @@ -38,6 +38,7 @@ #define SPI_PRR_BASE_SHIFT 0 #define SPI_PRR_LIMIT_SHIFT 16 #define SPI_PRR_WPE (1 << 31) +#define SPI_PRR_RPE (1 << 15) #define SPIBAR_PREOP 0x94 #define SPIBAR_OPTYPE 0x96 diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 2317c9a..a027446 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -615,11 +615,13 @@ /* Use first empty Protected Range Register to cover region of flash */ static int spi_flash_protect(const struct spi_flash *flash, - const struct region *region) + const struct region *region, + enum ctrlr_prot_type type) { u32 start = region_offset(region); u32 end = start + region_sz(region) - 1; u32 reg; + u32 protect_mask; int prr; /* Find first empty PRR */ @@ -637,12 +639,18 @@ reg = ((end >> SPI_PRR_SHIFT) & SPI_PRR_MASK); reg <<= SPI_PRR_LIMIT_SHIFT; reg |= ((start >> SPI_PRR_SHIFT) & SPI_PRR_MASK); - reg |= SPI_PRR_WPE; + + if (type & WRITE_PROTECT) + protect_mask |= SPI_PRR_WPE; + if (type & READ_PROTECT) + protect_mask |= SPI_PRR_RPE; + + reg |= protect_mask; /* Set the PRR register and verify it is protected */ SPIBAR32(SPI_PRR(prr)) = reg; reg = SPIBAR32(SPI_PRR(prr)); - if (!(reg & SPI_PRR_WPE)) { + if (!(reg & protect_mask)) { printk(BIOS_ERR, "ERROR: Unable to set SPI PRR %d\n", prr); return -1; } diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 4579b19..a56fe8b 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -367,11 +367,13 @@ * Protected Range (FPR) register if available. */ static int fast_spi_flash_protect(const struct spi_flash *flash, - const struct region *region) + const struct region *region, + enum ctrlr_prot_type type) { u32 start = region_offset(region); u32 end = start + region_sz(region) - 1; u32 reg; + u32 protect_mask = 0; int fpr; uintptr_t fpr_base; BOILERPLATE_CREATE_CTX(ctx); @@ -392,12 +394,18 @@ } /* Set protected range base and limit */ - reg = SPI_FPR(start, end) | SPI_FPR_WPE; + + if (type & WRITE_PROTECT) + protect_mask |= SPI_FPR_WPE; + if (type & READ_PROTECT) + protect_mask |= SPI_FPR_RPE; + + reg = SPI_FPR(start, end) | protect_mask; /* Set the FPR register and verify it is protected */ write32((void *)fpr_base, reg); reg = read32((void *)fpr_base); - if (!(reg & SPI_FPR_WPE)) { + if (!(reg & protect_mask)) { printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I093884c4768b08a378f21242ac82e430ac013d15 Gerrit-Change-Number: 30559 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

4 13

Change in ...coreboot[master]: sdm845: Add QUPv3 FW load & config
by Akash Asthana (Code Review) 21 Jan '19

21 Jan '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25372 ) Change subject: sdm845: Add QUPv3 FW load & config ...................................................................... Patch Set 63: (1 comment) https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… File src/mainboard/google/cheza/qupv3_config.c: https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… PS6, Line 18: struct se_cfg se_mappings[QUPV3_SE_MAX] = > > Is the loading of FW from respective protocol init function is needed for OTA upgrade OR something […] Okay, We are planning to load QUPV3 firmware from respective driver init function. Can you please share some reference driver for the same if any exists ? And if we load FW from respective driver init function then how should we handle the use cases that are only present in HLOS, like fingerprint SPI etc. Should we call respective instance driver init function from ramstage? So that will load FW and configure the required QUP. -- To view, visit https://review.coreboot.org/c/coreboot/+/25372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e87f868ecbe2a8e51d94c045ad76b99bb1b345d Gerrit-Change-Number: 25372 Gerrit-PatchSet: 63 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Jan 2019 13:14:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON
by Kyösti Mälkki (Code Review) 21 Jan '19

21 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30899 Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ...................................................................... AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON I refused bolton under agesa/ once it turned out to be blobbed. We have AMD_PI_BOLTON. Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/amd/agesa/state_machine.h M src/southbridge/amd/agesa/Makefile.inc M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h M src/southbridge/amd/agesa/hudson/pci_devs.h M src/southbridge/amd/common/Makefile.inc 7 files changed, 9 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30899/1 diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 81de242..43b205a 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -98,7 +98,6 @@ #define HAS_AGESA_FCH_OEM_CALLOUT \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index fd13bcf..cf4d790 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -13,6 +13,5 @@ # GNU General Public License for more details. # -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index b80f734..3806ae7 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -13,16 +13,13 @@ ## GNU General Public License for more details. ## -config SOUTHBRIDGE_AMD_AGESA_BOLTON - bool - config SOUTHBRIDGE_AMD_AGESA_HUDSON bool config SOUTHBRIDGE_AMD_AGESA_YANGTZE bool -if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y @@ -71,21 +68,18 @@ config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM config HUDSON_GEC_FWM_FILE string "GEC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/gec.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM @@ -180,7 +174,7 @@ bool default y -endif # SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE if SOUTHBRIDGE_AMD_AGESA_YANGTZE config AZ_PIN diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 77d660c..148bccc 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -21,7 +21,7 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define FCH_INT_TABLE_SIZE 0x54 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 @@ -51,8 +51,8 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) -#define PIRQ_SD 0x17 /* SD */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#define PIRQ_SD 0x17 /* SD */ #endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ @@ -70,9 +70,7 @@ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define PIRQ_SD 0x42 /* SD 14h.7 */ -#endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 328818c..7d3ad07 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index 4706403..c6528ae 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -26,13 +26,6 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) -#define XHCI2_DEV 0x10 -#define XHCI2_FUNC 1 -#define XHCI2_DEVID 0x7814 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) -#endif - /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -75,7 +68,7 @@ #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) /* IDE */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define IDE_DEV 0x14 #define IDE_FUNC 1 # define IDE_DEVID 0x780C @@ -108,7 +101,7 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) /* PCIe Ports */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define SB_PCIE_DEV 0x15 #define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT2_FUNC 1 diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index 92bb149..dcebdb5 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -1,6 +1,5 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70 Gerrit-Change-Number: 30899 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

6 13

Change in ...coreboot[master]: bachmann/mc2: Add new mainboard
by Christian Gmeiner (Code Review) 21 Jan '19

21 Jan '19

Christian Gmeiner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31025 ) Change subject: bachmann/mc2: Add new mainboard ...................................................................... Patch Set 1: > Patch Set 1: > > Do you configure the GPIO pads anywhere? Not yet as I *think* that I am not able to execute bootstage due to the boot guard. -- To view, visit https://review.coreboot.org/c/coreboot/+/31025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a86a8496e099dadd4d9f9d5df1b54cff4ce12e Gerrit-Change-Number: 31025 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-Reviewer: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 21 Jan 2019 11:58:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by Hung-Te Lin (Code Review) 21 Jan '19

21 Jan '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30331 ) Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 8 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 21 Jan 2019 09:57:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by You-Cheng Syu (Code Review) 21 Jan '19

21 Jan '19

Hello Julius Werner, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Chun-ta Lin, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30331 to look at the new patch set (#8). Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... google/kukui: Move some initialization from bootblock to verstage MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/verstage.c 4 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30331/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 8 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2019