coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: [test only, do not merge] add some printks in src/device
by Iru Cai (vimacs) (Code Review) 18 Jan '19

18 Jan '19

Iru Cai (vimacs) has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/20226 ) Change subject: [test only, do not merge] add some printks in src/device ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/20226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bfc49cc3205a2d3ed3141120fc30a28f85dcc29 Gerrit-Change-Number: 20226 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sdm845: Add QUPv3 FW load & config
by Akash Asthana (Code Review) 18 Jan '19

18 Jan '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25372 ) Change subject: sdm845: Add QUPv3 FW load & config ...................................................................... Patch Set 63: (8 comments) https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… File src/mainboard/google/cheza/qupv3_config.c: https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… PS6, Line 18: struct se_cfg se_mappings[QUPV3_SE_MAX] = > On other boards we usually have mainboard code call a function to initialize a controller at the fir […] So the expectation here is that i2c_init/spi_init.. function will load appropriate firmware to respective QUP. ======================================================= Further, you added comment in PS#25: Actually, thinking about this some more I'm not sure if we really need to do that on-demand approach I described earlier. Answering my own question from patch set 6, we have now determined empirically that it seems to be possible to update QUP firmware again after it had already been loaded (except for UARTs, but I assume that's just an issue with the code that could be fixed?), so there's not such big reason to delay the other QUPs until RW firmware anymore. However, even if we keep this approach there need to be some changes: the QSPI needs to be initialized in mainboard code (because the bus frequency is mainboard-dependent), so the QUP initialization needs to be called from there as well so it can run after QSPI (and thus access CBFS). If we have that we can get rid of this roundabout callback scheme and just pass the QUP mapping directly into the function. I think the structure can be simpler too, since QUPs are numbered 0 through 15 and there only needs to be one value if the other two are dependent on that... so I'd just make it a 16-element array of protocols (with 'none' as another valid protocol choice). See also the other comments from patch set 6 =========================================================== Few queries to get clear understanding, though we haven't thought of this wrt time/scoping. Is the loading of FW from respective protocol init function is needed for OTA upgrade OR something else in terms design ? Could you please provide some refrence drivers which are doing the same. If not then i shall make remaining changes you suggested for : Moving QSPI and QUP init to the mainboard and passing a 16-element array to qupv3 init function with none as an extra protocol. https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/include/soc… File src/soc/qualcomm/sdm845/include/soc/qupv3_fw_config.h: https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/include/soc… PS6, Line 65: bool dfs_mode; > Aren't mode and dfs_mode directly dependent on protocol (i.e. […] dfs_mode is directly dependent on protocol(true for all except UART) so, I have removed it from se_cfg structure. But modes aren't directly depends on the protocol, for example, SPI can be operated in FIFO as well as DMA mode so, I am keeping that in latest patch. https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… File src/soc/qualcomm/sdm845/qupv3_fw_config.c: https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… PS6, Line 142: #define SE_IRQ_EN_RMSK 0x0000000f > See general comments about how to do register accesses in other CLs (use struct overlays and the def […] We are using struct overlay for register access. https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… PS6, Line 145: __attribute__((packed)) > Avoid __attribute__((packed)) unless any elements are really misaligned. […] Agree, removed __attribute__((packed)) from latest patchset. https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… PS6, Line 190: static void fw_init_qup_common(void); > You generally shouldn't need to forward declare functions unless they recursively call into each oth […] Done https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… PS6, Line 227: /* HPG section 3.1.7.1 */ > "HPG" sounds like some sort of programming guide. […] We cannot directly release it to you, our tech release team will take care of that. If you still need it, I can initiate a request for that. https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… PS6, Line 353: fw_size_in_items > nit: could use an assert() to make sure it doesn't overrun the available register space (same goes f […] Done https://review.coreboot.org/#/c/25372/6/src/soc/qualcomm/sdm845/qupv3_fw_co… PS6, Line 422: REG_OUT(0x0015200C, 0, 0x3FFFFFC0); > Should probably be a separate function in clock.c. […] We are using clock_enable_qup API to turn on all the clocks. -- To view, visit https://review.coreboot.org/c/coreboot/+/25372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e87f868ecbe2a8e51d94c045ad76b99bb1b345d Gerrit-Change-Number: 25372 Gerrit-PatchSet: 63 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Jan 2019 09:39:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell: Use DEVICE_NOOP
by Patrick Rudolph (Code Review) 18 Jan '19

18 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29857 ) Change subject: src/soc/intel/braswell: Use DEVICE_NOOP ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Gerrit-Change-Number: 29857 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Jan 2019 09:23:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
by Patrick Georgi (Code Review) 18 Jan '19

18 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/26928 ) Change subject: soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE ...................................................................... soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE * Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Reviewed-on: https://review.coreboot.org/c/26928 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/denverton_ns/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..e34e4d1 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -56,6 +56,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE config FSP_T_ADDR hex "Intel FSP-T (temp ram init) binary location" -- To view, visit https://review.coreboot.org/c/coreboot/+/26928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Gerrit-Change-Number: 26928 Gerrit-PatchSet: 11 Gerrit-Owner: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien/variants: Add Thermal Sensors information
by Sumeet R Pawnikar (Code Review) 18 Jan '19

18 Jan '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30919 Change subject: mb/google/sarien/variants: Add Thermal Sensors information ...................................................................... mb/google/sarien/variants: Add Thermal Sensors information Add available thermal sensors information for CPU throttling action. BRANCH=None BUG=b:120058043 TEST=Built and tested on Arcada system Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 2 files changed, 36 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30919/1 diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 2d35878..bcf6364 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -16,16 +16,24 @@ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100 +/* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_SENSOR_NAME "Skin" #define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 80 +#define DPTF_TSR0_CRITICAL 70 +/* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_SENSOR_NAME "DDR" #define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 80 +/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER @@ -33,8 +41,14 @@ /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, - /* CPU Effect on Board */ + /* CPU Throttle Effect on Skin (TSR0) */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package () diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 2d35878..d63bdce 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -16,16 +16,24 @@ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100 +/* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_SENSOR_NAME "Skin" #define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 80 +#define DPTF_TSR0_CRITICAL 70 +/* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_SENSOR_NAME "DDR" #define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 80 +/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER @@ -33,8 +41,14 @@ /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, - /* CPU Effect on Board */ + /* CPU Throttle Effect on Skin (TSR0) */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package () -- To view, visit https://review.coreboot.org/c/coreboot/+/30919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Gerrit-Change-Number: 30919 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/spi/winbond.c: Add the rest of >=1MB Winbond W25 chips
by mikeb mikeb (Code Review) 18 Jan '19

18 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30746 to review the following change. Change subject: drivers/spi/winbond.c: Add the rest of >=1MB Winbond W25 chips ...................................................................... drivers/spi/winbond.c: Add the rest of >=1MB Winbond W25 chips Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I4d15d5acf0e2044e5128ce809c282fbcb35f24f0 --- M src/drivers/spi/winbond.c 1 file changed, 58 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30746/1 diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index f8ea247..8bf8fcd 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -104,6 +104,38 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { { + .id = 0x2014, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 4, + .name = "W25P80", + }, + { + .id = 0x2015, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 5, + .name = "W25P16", + }, + { + .id = 0x2016, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 6, + .name = "W25P32", + }, + { + .id = 0x3014, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 4, + .name = "W25X80", + }, + { .id = 0x3015, .l2_page_size_shift = 8, .pages_per_sector_shift = 4, @@ -133,7 +165,7 @@ .pages_per_sector_shift = 4, .sectors_per_block_shift = 4, .nr_blocks_shift = 4, - .name = "W25Q80", + .name = "W25Q80_V", }, { .id = 0x4015, @@ -141,7 +173,17 @@ .pages_per_sector_shift = 4, .sectors_per_block_shift = 4, .nr_blocks_shift = 5, - .name = "W25Q16", + .name = "W25Q16_V", + .protection_granularity_shift = 16, + .bp_bits = 3, + }, + { + .id = 0x6015, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 5, + .name = "W25Q16DW", .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -151,7 +193,7 @@ .pages_per_sector_shift = 4, .sectors_per_block_shift = 4, .nr_blocks_shift = 6, - .name = "W25Q32", + .name = "W25Q32_V", .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -171,7 +213,7 @@ .pages_per_sector_shift = 4, .sectors_per_block_shift = 4, .nr_blocks_shift = 7, - .name = "W25Q64", + .name = "W25Q64_V", .protection_granularity_shift = 17, .bp_bits = 3, }, @@ -191,7 +233,7 @@ .pages_per_sector_shift = 4, .sectors_per_block_shift = 4, .nr_blocks_shift = 8, - .name = "W25Q128", + .name = "W25Q128_V", .protection_granularity_shift = 18, .bp_bits = 3, }, @@ -221,7 +263,17 @@ .pages_per_sector_shift = 4, .sectors_per_block_shift = 4, .nr_blocks_shift = 9, - .name = "W25Q256", + .name = "W25Q256_V", + .protection_granularity_shift = 16, + .bp_bits = 4, + }, + { + .id = 0x7019, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 9, + .name = "W25Q256J", .protection_granularity_shift = 16, .bp_bits = 4, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/30746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d15d5acf0e2044e5128ce809c282fbcb35f24f0 Gerrit-Change-Number: 30746 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lib/boot_device: Add API for write protect a region
by Patrick Rudolph (Code Review) 18 Jan '19

18 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28724 ) Change subject: lib/boot_device: Add API for write protect a region ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 18 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 18 Jan 2019 07:49:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/wilco: Turn on wake up from lid
by Lijian Zhao (Code Review) 18 Jan '19

18 Jan '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30824 ) Change subject: ec/google/wilco: Turn on wake up from lid ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/30824/6/src/ec/google/wilco/commands.h File src/ec/google/wilco/commands.h: https://review.coreboot.org/#/c/30824/6/src/ec/google/wilco/commands.h@278 PS6, Line 278: EC_ACPI_WAKE_PWRB > I don't think this and LID are actually implemented (or can be disabled) and they are force/default […] Spec said power button had been force enabled, but lid switch not enabled by default, we checked during power on time. -- To view, visit https://review.coreboot.org/c/coreboot/+/30824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Gerrit-Change-Number: 30824 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Jan 2019 07:24:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pnp: simplify pnp_get_ioresource
by Samuel Holland (Code Review) 18 Jan '19

18 Jan '19

Samuel Holland has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/20095 ) Change subject: device/pnp: simplify pnp_get_ioresource ...................................................................... Abandoned Superseded by I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 -- To view, visit https://review.coreboot.org/c/coreboot/+/20095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia99b785dcd9cf56fb236ad7ade54656851f88a5e Gerrit-Change-Number: 20095 Gerrit-PatchSet: 2 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: ec/google/wilco: Turn on wake up from lid
by Duncan Laurie (Code Review) 18 Jan '19

18 Jan '19

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30824 ) Change subject: ec/google/wilco: Turn on wake up from lid ...................................................................... Patch Set 6: (2 comments) I will need to retest this, I had an open bug that it didn't work when set in coreboot... https://review.coreboot.org/#/c/30824/6//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30824/6//COMMIT_MSG@17 PS6, Line 17: Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> duplicate https://review.coreboot.org/#/c/30824/6/src/ec/google/wilco/commands.h File src/ec/google/wilco/commands.h: https://review.coreboot.org/#/c/30824/6/src/ec/google/wilco/commands.h@278 PS6, Line 278: EC_ACPI_WAKE_PWRB I don't think this and LID are actually implemented (or can be disabled) and they are force/default on. -- To view, visit https://review.coreboot.org/c/coreboot/+/30824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Gerrit-Change-Number: 30824 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Jan 2019 04:12:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019