coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: cpu/intel/model_206ax: Use parallel MP init
by Arthur Heymans (Code Review) 12 Jan '19

12 Jan '19

Hello Patrick Rudolph, Angel Pons, Tristan Corrick, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25618 to look at the new patch set (#34). Change subject: cpu/intel/model_206ax: Use parallel MP init ...................................................................... cpu/intel/model_206ax: Use parallel MP init This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves of ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/gen1/smi.h M src/cpu/intel/smm/gen1/smmrelocate.c M src/northbridge/intel/sandybridge/northbridge.c M src/southbridge/intel/common/smi.c 8 files changed, 193 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/25618/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/25618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Gerrit-Change-Number: 25618 Gerrit-PatchSet: 34 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/common: Add SSID header
by Angel Pons (Code Review) 12 Jan '19

12 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29490 ) Change subject: soc/intel/common: Add SSID header ...................................................................... Patch Set 13: Code-Review-1 AFAIK programming subsystem IDs can be done with plain C code. I do not think FSP should have to do it. -- To view, visit https://review.coreboot.org/c/coreboot/+/29490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bdabdd927fa477821f400e49c5787f405d0a9ea Gerrit-Change-Number: 29490 Gerrit-PatchSet: 13 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Jan 2019 23:14:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: clock: Adding the clock support for qcs405
by Julius Werner (Code Review) 12 Jan '19

12 Jan '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29962 ) Change subject: qcs405: clock: Adding the clock support for qcs405 ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/29962/3/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29962/3/src/soc/qualcomm/qcs405/clock.c@65 PS3, Line 65: spi_cfg > which SPI buses are initialized here? We'll need SPI bus 4 rather early, so it should be covered her […] This is the parent clock for the QSPI controller that is connected to SPI flash (the more recent SDM845 version names this qspi_core_cfg which is a little clearer). The other ("QUP") SPI busses use a different parent clock (this is qup_cfg in the SDM845 version of this file, where we merged what's called i2c_cfg and uart_cfg here into one table because it's really the same peripheral that can be programmed to do different things). https://review.coreboot.org/#/c/29962/3/src/soc/qualcomm/qcs405/clock.c@75 PS3, Line 75: SRC_XO_19_2MHZ I don't understand how this can work. What you're doing here is essentially saying that you can provide a 30MHz source clock by using the 19.2MHz oscillator with no divisor. That doesn't make sense, that would give you 19.2MHz, not 30. The point of this table is to define operating points of a frequency you can provide (.hz) and the settings that need to be programmed into the GCC registers to provide it (.hw_ctl, .src and .div). Note how, like everything else, this file needs to be deduplicated with SDM845 code (which has also changed quite a bit since you copied this... the clock code has now landed there, so you can start writing a patch to move it into a common directory now). I expect almost all the code will be shared, and maybe this table will need to be separately implemented by each SoC. -- To view, visit https://review.coreboot.org/c/coreboot/+/29962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Gerrit-Change-Number: 29962 Gerrit-PatchSet: 3 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Jan 2019 23:04:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/gen1/smmrelocate: Blacklist false SMRR advertisement
by Arthur Heymans (Code Review) 11 Jan '19

11 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30710 Change subject: cpu/intel/gen1/smmrelocate: Blacklist false SMRR advertisement ...................................................................... cpu/intel/gen1/smmrelocate: Blacklist false SMRR advertisement My pineview atom D400 on my Foxconn D41S advertisted SMRR support on MTRR_CAP_MSR but hangs on writing SMRR. The Intel® 64 and IA-32 Architectures Software Developer’s Manual makes no references to SMRR in the section "MSRS IN THE 45 NM AND 32 NM INTEL ® ATOM TM PROCESSOR FAMILY" so it is safe to assume it really isn't supported. Change-Id: Iee3cdfc21a7ab74b1f83680f43ceb7d6a6089fa3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c 1 file changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30710/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 46f6f93..8bcad54 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -87,6 +87,23 @@ } } +/* Some CPU's seem to falsely advertise SMRR support in MTRR_CAP_MSR */ +static bool cpu_smrr_blacklisted(void) +{ + struct cpuinfo_x86 c; + get_fms(&c, cpuid_eax(1)); + /* + * The Intel® 64 and IA-32 Architectures Software Developer’s Manual + * makes no references to SMRR in the section "MSRS IN THE 45 NM AND + * 32 NM INTEL ® ATOM TM PROCESSOR FAMILY" so it is safe to assume it + * really isn't supported. + */ + if (c.x86 == 6 && c.x86_model == 0x1c) + return true; + + return false; +} + /* The relocation work is actually performed in SMM context, but the code * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ @@ -135,7 +152,7 @@ /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) + if (mtrr_cap.lo & SMRR_SUPPORTED && !cpu_smrr_blacklisted()) write_smrr(relo_params); southbridge_clear_smi_status(); @@ -152,6 +169,9 @@ configuration value instead. */ const u32 tseg_size = northbridge_get_tseg_size(); + printk(BIOS_DEBUG, "SMM Relocate: TSEG_BASE: 0x%08x, TSEG_SIZE: 0x%08x\n", + tsegmb, tseg_size); + params->smram_base = tsegmb; params->smram_size = tseg_size; if (CONFIG_IED_REGION_SIZE != 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee3cdfc21a7ab74b1f83680f43ceb7d6a6089fa3 Gerrit-Change-Number: 30710 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/cpu/intel: Add model_f6x
by Angel Pons (Code Review) 11 Jan '19

11 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25565 ) Change subject: src/cpu/intel: Add model_f6x ...................................................................... Patch Set 26: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/25565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6003ec0f4d4245ce5fc9c1f38e555bfcfa1c22b5 Gerrit-Change-Number: 25565 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 11 Jan 2019 22:40:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/model_f6x: Add model F6x for i945 parallel MP init
by Angel Pons (Code Review) 11 Jan '19

11 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27558 ) Change subject: cpu/intel/model_f6x: Add model F6x for i945 parallel MP init ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/27558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62eedf2e6f1fd79fa3bf4e173e5317a7c775cdef Gerrit-Change-Number: 27558 Gerrit-PatchSet: 10 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Jan 2019 22:40:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/*/*: Use libgfxinit on sandy and ivy bridge boards
by Angel Pons (Code Review) 11 Jan '19

11 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27531 ) Change subject: mb/*/*: Use libgfxinit on sandy and ivy bridge boards ...................................................................... Patch Set 10: Code-Review+2 Looks good enough -- To view, visit https://review.coreboot.org/c/coreboot/+/27531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41ad1ce06d9afcc99941affa232fa76ffa6631fb Gerrit-Change-Number: 27531 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Comment-Date: Fri, 11 Jan 2019 22:36:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/kukui: add flapjack on top of kukui
by YH Lin (Code Review) 11 Jan '19

11 Jan '19

YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30859 ) Change subject: mb/google/kukui: add flapjack on top of kukui ...................................................................... Patch Set 1: Thanks!! -- To view, visit https://review.coreboot.org/c/coreboot/+/30859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9cd39e284f19b9179da73ed9f2b13d97442960e Gerrit-Change-Number: 30859 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Sanders <nsanders(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Comment-Date: Fri, 11 Jan 2019 21:32:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/kukui: add flapjack on top of kukui
by Julius Werner (Code Review) 11 Jan '19

11 Jan '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30859 ) Change subject: mb/google/kukui: add flapjack on top of kukui ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9cd39e284f19b9179da73ed9f2b13d97442960e Gerrit-Change-Number: 30859 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Sanders <nsanders(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Comment-Date: Fri, 11 Jan 2019 21:21:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/speedstep: Add Netburst
by Arthur Heymans (Code Review) 11 Jan '19

11 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22604 ) Change subject: cpu/intel/speedstep: Add Netburst ...................................................................... Patch Set 61: (2 comments) https://review.coreboot.org/#/c/22604/61/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/61/src/cpu/intel/speedstep/speedstep.… PS61, Line 84: !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { you don't want this on the same indentation level as the code. https://review.coreboot.org/#/c/22604/61/src/cpu/intel/speedstep/speedstep.… PS61, Line 95: switch (c.x86) { : case 0x6: : switch (c.x86_model) { : case 0xe: : /* Yonah */ : params->min.power = SPEEDSTEP_MIN_POWER_YONAH; : params->max.power = SPEEDSTEP_MAX_POWER_YONAH; : break; : case 0x17: : /* Penryn */ : params->slfm.power = SPEEDSTEP_SLFM_POWER_PENRYN; : params->min.power = SPEEDSTEP_MIN_POWER_PENRYN; : params->max.power = SPEEDSTEP_MAX_POWER_PENRYN; : params->turbo.power = SPEEDSTEP_MAX_POWER_PENRYN; : break; : } /* Merom fallthrough */ : default: : /* Use Merom values by default (as before). */ : params->slfm.power = SPEEDSTEP_SLFM_POWER_MEROM; : params->min.power = SPEEDSTEP_MIN_POWER_MEROM; : params->max.power = SPEEDSTEP_MAX_POWER_MEROM; : params->turbo.power = SPEEDSTEP_MAX_POWER_MEROM; : break; : } it is likely more readable if you set the default and then override it for select CPU's -- To view, visit https://review.coreboot.org/c/coreboot/+/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 61 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Jan 2019 20:32:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019