HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25601 )
Change subject: nb/intel/x4x: Use parallel MP init
......................................................................
Patch Set 36:
(2 comments)
https://review.coreboot.org/#/c/25601/36/src/cpu/intel/model_f4x/model_f4x_…
File src/cpu/intel/model_f4x/model_f4x_init.c:
https://review.coreboot.org/#/c/25601/36/src/cpu/intel/model_f4x/model_f4x_…
PS36, Line 16: #include <cpu/x86/mtrr.h>
Maybe you can remove this if it is not used
https://review.coreboot.org/#/c/25601/36/src/cpu/intel/model_f4x/model_f4x_…
PS36, Line 18: #include <cpu/intel/microcode.h>
: #include <cpu/intel/hyperthreading.h>
remove ?
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Kyösti Mälkki has uploaded a new patch set (#3) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/30777 )
Change subject: cpu/intel/car/p4: Update microcode in CAR setup
......................................................................
cpu/intel/car/p4: Update microcode in CAR setup
This updates the BSP microcode during CAR setup.
Change-Id: I87d34cf38dbd700ecb04d87c5b4767910e4a922c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30682
---
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
1 file changed, 37 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30777/3
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Kyösti Mälkki has uploaded a new patch set (#3) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/30776 )
Change subject: cpu/intel/car/p3: Update microcode in CAR setup
......................................................................
cpu/intel/car/p3: Update microcode in CAR setup
This updates the BSP microcode during CAR setup.
Change-Id: I5f31f7f30d6ce970d3616c12dbb264b2cf070ed9
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30682
---
M src/cpu/intel/car/p3/cache_as_ram.S
1 file changed, 33 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30776/3
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Name of user not set #1002090 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29676 )
Change subject: drivers/nvidia: Add PCI mapped option rom driver
......................................................................
Patch Set 2:
> Patch Set 2: -Code-Review
>
> I suspect that it will work if I'll use the vbios dumped from running OS under lenovo bios rather than the vbios extracted from bios dump. Because as I found out earlier (and mentioned on irc) lenovo bios patches vbios at runtime and changes PCI device id from 0ffb to 0ffc.
>
> I'm don't mind using vbios dumped from running OS, but if that's the case than we must explicitly mention it in the docs.
K2000M should be ffb and k1000M should be ffc. I have a dump from a running system for k2000m which has ffb. Are you sure it's changing at runtime ? You can get the rom from nouveau's debugfs and use https://github.com/awilliam/rom-parser to confirm.
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28640 )
Change subject: mb/clevo/n130wu: Add mainboard
......................................................................
Patch Set 64:
(4 comments)
https://review.coreboot.org/#/c/28640/64/src/mainboard/clevo/n130wu/gpio.h
File src/mainboard/clevo/n130wu/gpio.h:
https://review.coreboot.org/#/c/28640/64/src/mainboard/clevo/n130wu/gpio.h@…
PS64, Line 168: /* I2C5_SDA/ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000),
line over 80 characters
https://review.coreboot.org/#/c/28640/64/src/mainboard/clevo/n130wu/gpio.h@…
PS64, Line 169: /* I2C5_SCL/ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000),
line over 80 characters
https://review.coreboot.org/#/c/28640/64/src/mainboard/clevo/n130wu/pei_dat…
File src/mainboard/clevo/n130wu/pei_data.c:
https://review.coreboot.org/#/c/28640/64/src/mainboard/clevo/n130wu/pei_dat…
PS64, Line 31: 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}};
space required after that close brace '}'
https://review.coreboot.org/#/c/28640/64/src/mainboard/clevo/n130wu/pei_dat…
PS64, Line 40: {1, 0, 4, 5, 2, 3, 6, 7}};
space required after that close brace '}'
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Hello Paul Menzel, Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#64).
Change subject: mb/clevo/n130wu: Add mainboard
......................................................................
mb/clevo/n130wu: Add mainboard
Devices:
- N130WU / N131WU
Working:
- Compiling
- Seabios, iPXE
- NVMe, SATA3, booting from SSD into Arch Linux
- USB2, USB3
- Graphics, mDP, HDMI
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
WIP:
- Documentation
Not working:
- EC ACPI
- Thunderbolt
Untested:
- Virtualization
Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
A Documentation/mainboard/clevo/index.md
A Documentation/mainboard/clevo/n130wu/index.md
A Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg
M Documentation/mainboard/index.md
A src/mainboard/clevo/Kconfig
A src/mainboard/clevo/Kconfig.name
A src/mainboard/clevo/n130wu/Kconfig
A src/mainboard/clevo/n130wu/Kconfig.name
A src/mainboard/clevo/n130wu/Makefile.inc
A src/mainboard/clevo/n130wu/acpi/ec.asl
A src/mainboard/clevo/n130wu/acpi/superio.asl
A src/mainboard/clevo/n130wu/acpi_tables.c
A src/mainboard/clevo/n130wu/board_info.txt
A src/mainboard/clevo/n130wu/dsdt.asl
A src/mainboard/clevo/n130wu/gpio.h
A src/mainboard/clevo/n130wu/hda_verb.c
A src/mainboard/clevo/n130wu/pei_data.c
A src/mainboard/clevo/n130wu/pei_data.h
A src/mainboard/clevo/n130wu/ramstage.c
A src/mainboard/clevo/n130wu/romstage.c
A src/mainboard/clevo/n130wu/variants/n13xwu/data.vbt
A src/mainboard/clevo/n130wu/variants/n13xwu/devicetree.cb
22 files changed, 925 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28640/64
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Hello Alexander Couzens, Patrick Rudolph, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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Change subject: sb/intel/ibexpeak: Use common Intel SMM code
......................................................................
sb/intel/ibexpeak: Use common Intel SMM code
TODO in followup patch: Some not mainboard specific things should be
moved out of mainboard_smi_apmc.
Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/lenovo/x201/smihandler.c
M src/mainboard/packardbell/ms2290/smihandler.c
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/Makefile.inc
M src/southbridge/intel/ibexpeak/pch.h
D src/southbridge/intel/ibexpeak/smi.c
M src/southbridge/intel/ibexpeak/smihandler.c
7 files changed, 18 insertions(+), 1,033 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/26296/33
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Hello Patrick Rudolph, Angel Pons, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#36).
Change subject: nb/intel/x4x: Use parallel MP init
......................................................................
nb/intel/x4x: Use parallel MP init
Use parallel MP init code to initialize all AP's.
Also remove guards around CPU code where all platforms now use
parallel MP init.
Tested on Intel DG41WV, shaves off about 90ms on a quad core.
Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/model_6fx/model_6fx_init.c
M src/cpu/intel/model_f4x/model_f4x_init.c
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/northbridge.c
5 files changed, 2 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/25601/36
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Hello Patrick Rudolph, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#46).
Change subject: nb/intel/gm45: Use parallel MP init
......................................................................
nb/intel/gm45: Use parallel MP init
This places the parallel mp ops up in the model_1067x dir and is
included from other Intel core2 CPU dirs that can use the same code.
Tested on Thinkpad X200 on which boot time is reduced by ~35ms.
Change-Id: Iac416f671407246ee223075eee1aff511e612889
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/model_1067x/Makefile.inc
M src/cpu/intel/model_1067x/model_1067x_init.c
A src/cpu/intel/model_1067x/mp_init.c
M src/cpu/intel/model_6fx/Makefile.inc
M src/cpu/intel/model_6fx/model_6fx_init.c
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/northbridge.c
7 files changed, 107 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/23434/46
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