coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Arthur Heymans (Code Review) 13 Jan '19

13 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... Patch Set 9: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/27089/9//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27089/9//COMMIT_MSG@13 PS9, Line 13: What is tested and works: is S3 resume working? it is always nice to mention that since if it doesn't work in the future devs can know if it's a regression or not. -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Jan 2019 08:52:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30688 Change subject: [WIP] aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK ...................................................................... [WIP] aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK Need to figure out better solution for AP_SIPI_VECTOR. Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_mPGA604/Makefile.inc A src/mainboard/aopen/dxplplusu/Makefile.inc A src/mainboard/aopen/dxplplusu/bootblock.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c M src/superio/smsc/lpc47m10x/Makefile.inc 9 files changed, 54 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30688/1 diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index a7cb99e..8d2bbcb 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -44,6 +44,7 @@ config AP_SIPI_VECTOR hex + default 0xffff0000 if C_ENVIRONMENT_BOOTBLOCK default 0xfffff000 help This must equal address of ap_sipi_vector from bootblock build. diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ab0cf8a..ca2f7b3 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -10,6 +10,7 @@ select SSE select UDELAY_TSC select SIPI_VECTOR_IN_ROM + select C_ENVIRONMENT_BOOTBLOCK # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -26,4 +27,8 @@ hex default 0x4000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + endif # CPU_INTEL_SOCKET_MPGA604 diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 371f7a6..9e3b8d7 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -7,6 +7,8 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading -cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c + postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc new file mode 100644 index 0000000..0fedf5c --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Makefile.inc @@ -0,0 +1,14 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c new file mode 100644 index 0000000..7c1d11d --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_def.h> +#include <superio/smsc/lpc47m10x/lpc47m10x.h> + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Get the serial port running and print a welcome banner */ + lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 827f6bb..cae178a 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -29,8 +29,4 @@ hex default 0xfef00000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801dx/bootblock.c" - endif diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 7d87995..5ba2130 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -30,4 +30,6 @@ romstage-y += early_smbus.c +bootblock-y += bootblock.c + endif diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index 8ae419d..a5e48e5 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -11,9 +11,10 @@ * GNU General Public License for more details. */ +#include <cpu/intel/car/bootblock.h> #include <arch/io.h> -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { /* Set FWH IDs for 2 MB flash part. */ if (CONFIG_ROM_SIZE == 0x200000) diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc index 0dd272c..278aa1e 100644 --- a/src/superio/smsc/lpc47m10x/Makefile.inc +++ b/src/superio/smsc/lpc47m10x/Makefile.inc @@ -18,5 +18,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Gerrit-Change-Number: 30688 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86: Drop Kconfig AP_SIPI_VECTOR
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30854 Change subject: arch/x86: Drop Kconfig AP_SIPI_VECTOR ...................................................................... arch/x86: Drop Kconfig AP_SIPI_VECTOR This was used to check romcc-built bootblock and romstage agree about the location of 16-bit entrypoint. There was no need to customize it as bootblock size requirement did not grow. Just check for a fixed location at 4 GiB - 4 KiB. With C_ENVIRONMENT_BOOTBLOCK we can have a proper symbol for the purpose, since it appears in the same compilation unit. It will adjust if C_ENV_BOOTBLOCK_SIZE changes. Change-Id: I93f3c37e78ba587455c804de8c57e7e06832a81f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/failover.ld M src/cpu/Kconfig M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/16bit/entry16.ld 5 files changed, 15 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30854/1 diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index e9613d9..b32aa29 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -35,7 +35,6 @@ /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; - ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -54,9 +53,7 @@ (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); /* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0), - "Bad SIPI vector alignment"); - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), + _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index f98ce6d..6078022 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -42,12 +42,6 @@ This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. -config AP_SIPI_VECTOR - hex - default 0xfffff000 - help - This must equal address of ap_sipi_vector from bootblock build. - config MMX bool help diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index bdce514..fda572d 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,7 +23,10 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) +#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +/* Fixed location, ASSERTED in failover.ld if it changes. */ +.set ap_sipi_vector_in_rom, 0xff +#endif #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -180,7 +183,8 @@ /* Send Start IPI to all excluding ourself. */ movl LAPIC(ICR), %edi - movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP), %eax + orl $ap_sipi_vector_in_rom, %eax 1: movl %eax, (%edi) movl $0x30, %ecx 2: pause diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 5a9739c..55d9bd9 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -28,6 +28,13 @@ */ #include <arch/rom_segs.h> + +#if IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM) +/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with + * Startup IPI message without RAM. + */ +.align 4096 +#endif .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld index 112d429..66bfbd5 100644 --- a/src/cpu/x86/16bit/entry16.ld +++ b/src/cpu/x86/16bit/entry16.ld @@ -1,2 +1,3 @@ gdtptr16_offset = gdtptr16 & 0xffff; nullidt_offset = nullidt & 0xffff; + ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; -- To view, visit https://review.coreboot.org/c/coreboot/+/30854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93f3c37e78ba587455c804de8c57e7e06832a81f Gerrit-Change-Number: 30854 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/car/p4: Update microcode in CAR setup
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30777 ) Change subject: cpu/intel/car/p4: Update microcode in CAR setup ...................................................................... cpu/intel/car/p4: Update microcode in CAR setup This updates the BSP microcode during CAR setup. Change-Id: I87d34cf38dbd700ecb04d87c5b4767910e4a922c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30682 Reviewed-on: https://review.coreboot.org/c/30777 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S 1 file changed, 37 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 8587ea5..bdce514 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -297,21 +297,32 @@ post_code(0x2c) + /* Cache the whole rom to fetch microcode updates */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 - /* Clear the cache memory region. This will also fill up the cache. */ - cld - xorl %eax, %eax - movl $CACHE_AS_RAM_BASE, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - rep stosl - +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) + update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode + end_microcode_update: +#endif post_code(0x2d) - /* Enable Cache-as-RAM mode by disabling cache. */ + /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 @@ -326,8 +337,16 @@ movl $1, %eax cpuid cmp $0xf, %ah - je skip_cache_rom + jne cache_rom +disable_cache_rom: + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + andl $(~MTRR_PHYS_MASK_VALID), %eax + wrmsr + jmp fill_cache + +cache_rom: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx @@ -345,14 +364,21 @@ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr -skip_cache_rom: - +fill_cache: post_code(0x2e) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd movl %eax, %cr0 + /* Clear the cache memory region. This will also fill up the cache. */ + cld + xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + rep stosl + /* Setup the stack. */ mov $_car_stack_end, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/30777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87d34cf38dbd700ecb04d87c5b4767910e4a922c Gerrit-Change-Number: 30777 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/cpu/intel: Set get_ia32_fsb function common
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30103 ) Change subject: src/cpu/intel: Set get_ia32_fsb function common ...................................................................... Patch Set 24: (1 comment) https://review.coreboot.org/#/c/30103/24/src/cpu/intel/common/Makefile.inc File src/cpu/intel/common/Makefile.inc: https://review.coreboot.org/#/c/30103/24/src/cpu/intel/common/Makefile.inc@2 PS24, Line 2: romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c Not sure about the guard and leaving out bootblock and verstage. We might want to add tsc_freq_mhz() in this file. But that can be all followup. -- To view, visit https://review.coreboot.org/c/coreboot/+/30103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 Gerrit-Change-Number: 30103 Gerrit-PatchSet: 24 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 13 Jan 2019 02:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: console: Add Kconfig debug option DEBUG_CONSOLE_INIT
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30558 to look at the new patch set (#5). Change subject: console: Add Kconfig debug option DEBUG_CONSOLE_INIT ...................................................................... console: Add Kconfig debug option DEBUG_CONSOLE_INIT Under normal circumstances no printk() goes through until console_hw_init() has completed. This is wanted behaviour, except when you need to debug the setup of one of consoles. Change-Id: Ifc2bb22bf930009ee229d4461f512ada3018307b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/console/init.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30558/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/30558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc2bb22bf930009ee229d4461f512ada3018307b Gerrit-Change-Number: 30558 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Angel Pons (Code Review) 13 Jan '19

13 Jan '19

Hello Arthur Heymans, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27089 to look at the new patch set (#9). Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant This board has more or less the same as the p5qpl-am except for DDR3 memory and different colors on the ports. Tested with Arch Linux with kernel 4.20.0-arch1-1-ARCH. What is tested and works: - 800/1066/1333 MHz CPUs and DDR3 sticks at 800/1066 MHz Some bugs are still present in the DDR3 raminit code though. - Ethernet - Internal programmer with both coreboot and stock firmware. - PCI and PCIe x1 slots - All USB ports - S3 resume - SATA ports - PEG - Rear audio output Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p5qpl-am/Kconfig M src/mainboard/asus/p5qpl-am/Kconfig.name M src/mainboard/asus/p5qpl-am/Makefile.inc M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/asus/p5qpl-am/romstage.c A src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c A src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb R src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c A src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb 9 files changed, 387 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27089/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Angel Pons (Code Review) 13 Jan '19

13 Jan '19

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Angel Pons (Code Review) 13 Jan '19

13 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/27089/6/src/mainboard/asus/p5qpl-am/acpi/ic… File src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl: https://review.coreboot.org/#/c/27089/6/src/mainboard/asus/p5qpl-am/acpi/ic… PS6, Line 58: /* PCI1 SLOT 2 */ > Not sure, I can give you my DSDT if you want. Fixed thanks to Arthur's explanations. https://review.coreboot.org/#/c/27089/6/src/mainboard/asus/p5qpl-am/variant… File src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb: https://review.coreboot.org/#/c/27089/6/src/mainboard/asus/p5qpl-am/variant… PS6, Line 22: device pnp 2e.1 on # Parallel port > Then what does CB:30242 do? (it's what I based this overridetree out of) Moved the whole superio chip definition to overridetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Jan 2019 01:47:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/eltan: Add vendor code for measured and verified boot.
by Angel Pons (Code Review) 13 Jan '19

13 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30218 ) Change subject: vendorcode/eltan: Add vendor code for measured and verified boot. ...................................................................... Patch Set 7: BTW, you can add all the related patches to the same gerrit topic so that it is easier to keep track of them. There is also the option of using patch trains, so that you build on previous, not yet merged patches. It is good for reviewing as well, since one can follow the order in which the code was added. -- To view, visit https://review.coreboot.org/c/coreboot/+/30218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80 Gerrit-Change-Number: 30218 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 13 Jan 2019 01:38:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019