coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Angel Pons (Code Review) 13 Jan '19

13 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/27089/9/src/mainboard/asus/p5qpl-am/romstag… File src/mainboard/asus/p5qpl-am/romstage.c: https://review.coreboot.org/#/c/27089/9/src/mainboard/asus/p5qpl-am/romstag… PS9, Line 70: static int setup_sio_gpio(void) > If you feel lazy, this is from before variants/ existed: […] After trying to use a proper variant romstage.c and failing to get it to work, I will use one IS_ENABLED instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Jan 2019 17:01:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/27089/9/src/mainboard/asus/p5qpl-am/romstag… File src/mainboard/asus/p5qpl-am/romstage.c: https://review.coreboot.org/#/c/27089/9/src/mainboard/asus/p5qpl-am/romstag… PS9, Line 70: static int setup_sio_gpio(void) > Um, yes, the current function is ugly at best. So this would be a romstage. […] If you feel lazy, this is from before variants/ existed: src/mainboard/asus/f2a85-m/romstage.c So just doing IS_ENABLED() once is major improvment here. -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Jan 2019 16:47:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Angel Pons (Code Review) 13 Jan '19

13 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... Patch Set 9: Code-Review-1 (1 comment) https://review.coreboot.org/#/c/27089/9/src/mainboard/asus/p5qpl-am/romstag… File src/mainboard/asus/p5qpl-am/romstage.c: https://review.coreboot.org/#/c/27089/9/src/mainboard/asus/p5qpl-am/romstag… PS9, Line 70: static int setup_sio_gpio(void) > My opinion is this would have been worth two separate functions, one for each variant. […] Um, yes, the current function is ugly at best. So this would be a romstage.c in each variant dir and a makefile.inc entry to gain readability. Sounds wise. -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Jan 2019 16:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/27089/9/src/mainboard/asus/p5qpl-am/romstag… File src/mainboard/asus/p5qpl-am/romstage.c: https://review.coreboot.org/#/c/27089/9/src/mainboard/asus/p5qpl-am/romstag… PS9, Line 70: static int setup_sio_gpio(void) My opinion is this would have been worth two separate functions, one for each variant. Maybe even thrown over under variant/x/ directory. -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Jan 2019 16:39:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Angel Pons (Code Review) 13 Jan '19

13 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/27089/9//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27089/9//COMMIT_MSG@13 PS9, Line 13: What is tested and works: > is S3 resume working? it is always nice to mention that since if it doesn't work in the future devs […] See line 20 ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Jan 2019 16:28:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in ...coreboot[master]: Drop unused dump_mem()
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30894 Change subject: Drop unused dump_mem() ...................................................................... Drop unused dump_mem() If needed, there are hexdump variants in lib/hexdump.c. Change-Id: I2467d03f269007fea1bf830b213d4f11d2b552bf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/northbridge/amd/amdfam10/debug.c M src/northbridge/amd/amdfam10/debug.h M src/northbridge/intel/e7505/debug.c M src/northbridge/intel/e7505/debug.h M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/i945.h 15 files changed, 0 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/30894/1 diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index c9fc9ec..056f840 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -100,8 +100,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 788907a..e93f2dd 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -100,8 +100,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 5cc9707..1bf4e78 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -101,8 +101,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 6b03ffd..5c36727 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -104,8 +104,6 @@ console_init(); printk(BIOS_DEBUG, "\n"); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 1bb3c64..9f77635 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -96,8 +96,6 @@ it8718f_disable_reboot(GPIO_DEV); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 11dd190..f608845 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -96,8 +96,6 @@ it8718f_disable_reboot(GPIO_DEV); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index d42e90b..3167bf3 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -98,8 +98,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 9c4183e..7737625 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -103,8 +103,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 8508189..db5147f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -110,8 +110,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 067c299..55a00e1 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -299,19 +299,6 @@ } } -void dump_mem(u32 start, u32 end) -{ - u32 i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - printk(BIOS_DEBUG, "\n"); -} - #if IS_ENABLED(CONFIG_DIMM_DDR2) void print_tx(const char *strval, u32 val) { diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h index a4ecfe9..a23303e 100644 --- a/src/northbridge/amd/amdfam10/debug.h +++ b/src/northbridge/amd/amdfam10/debug.h @@ -38,7 +38,6 @@ #endif void dump_io_resources(u32 port); -void dump_mem(u32 start, u32 end); void print_tx(const char *strval, u32 val); void print_t(const char *strval); diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index f3a27e2..c21e321 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -183,15 +183,3 @@ port++; } } - -void dump_mem(unsigned start, unsigned end) -{ - unsigned i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf)==0) - printk(BIOS_DEBUG, "\n%08x:", i); - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); -} diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h index 238c500..98ca848 100644 --- a/src/northbridge/intel/e7505/debug.h +++ b/src/northbridge/intel/e7505/debug.h @@ -22,6 +22,5 @@ void dump_spd_registers(const struct mem_controller *ctrl); void dump_smbus_registers(void); void dump_io_resources(unsigned port); -void dump_mem(unsigned start, unsigned end); #endif diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index ef4f17b..c52f2a6 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -96,15 +96,3 @@ printk(BIOS_DEBUG, "\n"); } } - -void dump_mem(unsigned int start, unsigned int end) -{ - unsigned int i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) - printk(BIOS_DEBUG, "\n%08x:", i); - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); -} diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 65a40e7..757eb52 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -379,7 +379,6 @@ void dump_pci_device(unsigned int dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned int start, unsigned int end); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); -- To view, visit https://review.coreboot.org/c/coreboot/+/30894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2467d03f269007fea1bf830b213d4f11d2b552bf Gerrit-Change-Number: 30894 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29853 ) Change subject: {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem() ...................................................................... {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem() Use hexdump() instead of dump_mem(). Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/29853 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Guckian Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/northbridge/amd/amdfam10/debug.c M src/northbridge/amd/amdfam10/debug.h M src/northbridge/intel/e7505/debug.c M src/northbridge/intel/e7505/debug.h M src/northbridge/intel/fsp_rangeley/northbridge.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/sandybridge.h M src/soc/intel/fsp_baytrail/include/soc/baytrail.h 20 files changed, 0 insertions(+), 63 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index c9fc9ec..056f840 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -100,8 +100,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 788907a..e93f2dd 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -100,8 +100,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 5cc9707..1bf4e78 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -101,8 +101,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 6b03ffd..5c36727 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -104,8 +104,6 @@ console_init(); printk(BIOS_DEBUG, "\n"); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 1bb3c64..9f77635 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -96,8 +96,6 @@ it8718f_disable_reboot(GPIO_DEV); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 11dd190..f608845 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -96,8 +96,6 @@ it8718f_disable_reboot(GPIO_DEV); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index d42e90b..3167bf3 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -98,8 +98,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 9c4183e..7737625 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -103,8 +103,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 8508189..db5147f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -110,8 +110,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 067c299..55a00e1 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -299,19 +299,6 @@ } } -void dump_mem(u32 start, u32 end) -{ - u32 i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - printk(BIOS_DEBUG, "\n"); -} - #if IS_ENABLED(CONFIG_DIMM_DDR2) void print_tx(const char *strval, u32 val) { diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h index a4ecfe9..a23303e 100644 --- a/src/northbridge/amd/amdfam10/debug.h +++ b/src/northbridge/amd/amdfam10/debug.h @@ -38,7 +38,6 @@ #endif void dump_io_resources(u32 port); -void dump_mem(u32 start, u32 end); void print_tx(const char *strval, u32 val); void print_t(const char *strval); diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index f3a27e2..c21e321 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -183,15 +183,3 @@ port++; } } - -void dump_mem(unsigned start, unsigned end) -{ - unsigned i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf)==0) - printk(BIOS_DEBUG, "\n%08x:", i); - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); -} diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h index 238c500..98ca848 100644 --- a/src/northbridge/intel/e7505/debug.h +++ b/src/northbridge/intel/e7505/debug.h @@ -22,6 +22,5 @@ void dump_spd_registers(const struct mem_controller *ctrl); void dump_smbus_registers(void); void dump_io_resources(unsigned port); -void dump_mem(unsigned start, unsigned end); #endif diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index f68d175..11089a5 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -69,7 +69,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #ifndef __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index f67995d..9125764 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -228,7 +228,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index ef4f17b..c52f2a6 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -96,15 +96,3 @@ printk(BIOS_DEBUG, "\n"); } } - -void dump_mem(unsigned int start, unsigned int end) -{ - unsigned int i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) - printk(BIOS_DEBUG, "\n%08x:", i); - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); -} diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 65a40e7..757eb52 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -379,7 +379,6 @@ void dump_pci_device(unsigned int dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned int start, unsigned int end); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 5756c90..b0e8490 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -277,7 +277,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index faa9cd90..9e3da4b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -219,7 +219,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); #endif /* !__SMM__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 82fd0a1..68bdd12 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -63,7 +63,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* __PRE_RAM__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Gerrit-Change-Number: 29853 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29853 ) Change subject: {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Gerrit-Change-Number: 29853 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 13 Jan 2019 16:24:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Add symbols for CAR MTRRs in linker script
by build bot (Jenkins) (Code Review) 13 Jan '19

13 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30872 ) Change subject: arch/x86: Add symbols for CAR MTRRs in linker script ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/30872/2/src/arch/x86/car.ld File src/arch/x86/car.ld: https://review.coreboot.org/#/c/30872/2/src/arch/x86/car.ld@129 PS2, Line 129: _bogus1 = ASSERT(((_car_mtrr_start & (_car_mtrr_size - 1)) == 0), "Cache as RAM area has invalid aligment for MTRRs"); 'aligment' may be misspelled - perhaps 'alignment'? -- To view, visit https://review.coreboot.org/c/coreboot/+/30872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Gerrit-Change-Number: 30872 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 13 Jan 2019 14:21:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Add symbols for CAR MTRRs in linker script
by Kyösti Mälkki (Code Review) 13 Jan '19

13 Jan '19

Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30872 to look at the new patch set (#2). Change subject: arch/x86: Add symbols for CAR MTRRs in linker script ...................................................................... arch/x86: Add symbols for CAR MTRRs in linker script This allows to remove references to CONFIG_DCACHE_RAM entries in most cache_as_ram.S files. While Kconfig variable names appear for every stage, linker symbol names will only appear in stages they are valid in. Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30872/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Gerrit-Change-Number: 30872 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2019