coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: drivers/spi/amic.c: Add the rest of >=1MB AMIC A25 chips
by mikeb mikeb (Code Review) 14 Jan '19

14 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30884 to review the following change. Change subject: drivers/spi/amic.c: Add the rest of >=1MB AMIC A25 chips ...................................................................... drivers/spi/amic.c: Add the rest of >=1MB AMIC A25 chips Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ic5bd3e43e0d3fd5f454fae71b307c0682f203d5c --- M src/drivers/spi/amic.c 1 file changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30884/1 diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 64bdab3..b0e926e 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -42,6 +42,38 @@ static const struct amic_spi_flash_params amic_spi_flash_table[] = { { + .id = 0x2015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "A25L16PU", + }, + { + .id = 0x2025, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "A25L16PT", + }, + { + .id = 0x3014, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "A25L080", + }, + { + .id = 0x3015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "A25L016", + }, + { .id = 0x3016, .l2_page_size = 8, .pages_per_sector = 16, @@ -49,6 +81,38 @@ .nr_blocks = 64, .name = "A25L032", }, + { + .id = 0x4014, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "A25LQ080", + }, + { + .id = 0x4015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "A25LQ16", + }, + { + .id = 0x4016, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "A25LQ032", + }, + { + .id = 0x4017, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "A25LQ64", + }, }; static int amic_write(const struct spi_flash *flash, u32 offset, size_t len, -- To view, visit https://review.coreboot.org/c/coreboot/+/30884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5bd3e43e0d3fd5f454fae71b307c0682f203d5c Gerrit-Change-Number: 30884 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: drivers/spi/adesto.c: Add the rest of >=1MB Adesto (Atmel) chips
by mikeb mikeb (Code Review) 14 Jan '19

14 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30883 to review the following change. Change subject: drivers/spi/adesto.c: Add the rest of >=1MB Adesto (Atmel) chips ...................................................................... drivers/spi/adesto.c: Add the rest of >=1MB Adesto (Atmel) chips Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I8c0e6d8f1487ca90f88d4a56af3fb0e21458ef1e --- M src/drivers/spi/adesto.c 1 file changed, 73 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30883/1 diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 3e3e7d4..5195bec 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -44,15 +44,47 @@ static const struct adesto_spi_flash_params adesto_spi_flash_table[] = { { + .id = 0x4218, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "AT25SL128A", + }, + { .id = 0x4501, .l2_page_size = 8, .pages_per_sector = 16, .sectors_per_block = 16, .nr_blocks = 16, + .name = "AT25DF081A", /* Yes, 81A id < 81 */ + }, + { + .id = 0x4502, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, .name = "AT25DF081", }, { - .id = 0x4701, + .id = 0x4602, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "AT25DF161", + }, + { + .id = 0x4603, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "AT25DL161", + }, + { + .id = 0x4700, .l2_page_size = 8, .pages_per_sector = 16, .sectors_per_block = 16, @@ -60,6 +92,14 @@ .name = "AT25DF321", }, { + .id = 0x4701, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "AT25DF321A", + }, + { .id = 0x4800, .l2_page_size = 8, .pages_per_sector = 16, @@ -67,6 +107,38 @@ .nr_blocks = 128, .name = "AT25DF641", }, + { + .id = 0x8501, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "AT25SF081", + }, + { + .id = 0x8600, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "AT25DQ161", + }, + { + .id = 0x8601, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "AT25SF161", + }, + { + .id = 0x8700, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "AT25DQ321", + }, }; static int adesto_write(const struct spi_flash *flash, u32 offset, size_t len, -- To view, visit https://review.coreboot.org/c/coreboot/+/30883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c0e6d8f1487ca90f88d4a56af3fb0e21458ef1e Gerrit-Change-Number: 30883 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: drivers/spi/gigadevice.c: Add the rest of >=1MB Gigadevice GD25 chips
by mikeb mikeb (Code Review) 14 Jan '19

14 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30882 to review the following change. Change subject: drivers/spi/gigadevice.c: Add the rest of >=1MB Gigadevice GD25 chips ...................................................................... drivers/spi/gigadevice.c: Add the rest of >=1MB Gigadevice GD25 chips Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I333c8589ddc2bece488608ff66015ca8307eae0f --- M src/drivers/spi/gigadevice.c 1 file changed, 59 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/30882/1 diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 2d7544c..ff1ce2f 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -51,12 +51,20 @@ static const struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] = { { + .id = 0x3114, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "GD25T80", + }, + { .id = 0x4014, .l2_page_size = 8, .pages_per_sector = 16, .sectors_per_block = 16, .nr_blocks = 16, - .name = "GD25Q80", + .name = "GD25Q80(B)", }, { .id = 0x4015, @@ -75,6 +83,54 @@ .name = "GD25Q32(B)", }, { + .id = 0x4017, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "GD25Q64(B)/GD25B64C", + }, + { + .id = 0x4018, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "GD25Q128(B)", + }, + { + .id = 0x4214, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "GD25VQ80C", + }, + { + .id = 0x4215, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "GD25VQ16C", + }, + { + .id = 0x6014, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "GD25LQ80", + }, + { + .id = 0x6015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "GD25LQ16", + }, + { .id = 0x6016, .l2_page_size = 8, .pages_per_sector = 16, @@ -83,14 +139,6 @@ .name = "GD25LQ32", }, { - .id = 0x4017, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 128, - .name = "GD25Q64B/GD25B64C", - }, - { .id = 0x6017, .l2_page_size = 8, .pages_per_sector = 16, @@ -99,12 +147,12 @@ .name = "GD25LQ64C/GD25LB64C", }, { - .id = 0x4018, + .id = 0x6018, .l2_page_size = 8, .pages_per_sector = 16, .sectors_per_block = 16, .nr_blocks = 256, - .name = "GD25Q128(B)", + .name = "GD25LQ128", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I333c8589ddc2bece488608ff66015ca8307eae0f Gerrit-Change-Number: 30882 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: drivers/spi/macronix.c: Add the rest of >=1MB Macronix MX25 chips
by mikeb mikeb (Code Review) 14 Jan '19

14 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30877 to review the following change. Change subject: drivers/spi/macronix.c: Add the rest of >=1MB Macronix MX25 chips ...................................................................... drivers/spi/macronix.c: Add the rest of >=1MB Macronix MX25 chips Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I4508a65a5bdcbf58aadf452de5e896fc3c5b1bc3 --- M src/drivers/spi/macronix.c 1 file changed, 83 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30877/1 diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 7ed70c0..1fac076 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -80,22 +80,6 @@ .name = "MX25L3205D", }, { - .idcode = 0x5e16, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 64, - .name = "MX25L3235D", /* MX25L3225D/MX25L3235D/MX25L3236D/MX25L3237D */ - }, - { - .idcode = 0x2536, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 64, - .name = "MX25L3239E", - }, - { .idcode = 0x2017, .page_size = 256, .pages_per_sector = 16, @@ -112,12 +96,60 @@ .name = "MX25L12805D", }, { - .idcode = 0x2618, + .idcode = 0x2019, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, - .nr_blocks = 256, - .name = "MX25L12855E", + .nr_blocks = 512, + .name = "MX25L25635F", + }, + { + .idcode = 0x201a, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 1024, + .name = "MX66L51235F", + }, + { + .idcode = 0x2415, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "MX25L1635D", + }, + { + .idcode = 0x2515, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "MX25L1635E", + }, + { + .idcode = 0x2534, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "MX25U8032E", + }, + { + .idcode = 0x2535, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "MX25U1635E", + }, + { + .idcode = 0x2536, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "MX25U3235E", }, { .idcode = 0x2537, @@ -136,6 +168,38 @@ .name = "MX25U12835F", }, { + .idcode = 0x2539, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 512, + .name = "MX25U25635F", + }, + { + .idcode = 0x253a, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 1024, + .name = "MX25U51245G", + }, + { + .idcode = 0x2618, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "MX25L12855E", + }, + { + .idcode = 0x5e16, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "MX25L3235D", /* MX25L3225D/MX25L3235D/MX25L3236D/MX25L3237D */ + }, + { .idcode = 0x9517, .page_size = 256, .pages_per_sector = 16, -- To view, visit https://review.coreboot.org/c/coreboot/+/30877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4508a65a5bdcbf58aadf452de5e896fc3c5b1bc3 Gerrit-Change-Number: 30877 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: drivers/spi/spansion.c: Add more S25FL_K chips
by mikeb mikeb (Code Review) 14 Jan '19

14 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30874 to review the following change. Change subject: drivers/spi/spansion.c: Add more S25FL_K chips ...................................................................... drivers/spi/spansion.c: Add more S25FL_K chips Add S25FL208K (ID 0x4014), S25FL132K (ID 0x4016) and S25FL164K (ID 0x4017) chips in a way similar to S25FL116K (ID 0x4015) chip from the same family. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I9bf7197bbc0d12797c8ed100c673628de9c140f7 --- M src/drivers/spi/spansion.c 1 file changed, 36 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30874/1 diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 16c5180..2e92434 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -39,14 +39,17 @@ #define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */ #define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */ -#define SPSN_MANUFACTURER_ID_S25FL116K 0x01 +#define SPSN_MANUFACTURER_ID_S25FL_K 0x01 #define SPSN_ID_S25FL008A 0x0213 #define SPSN_ID_S25FL016A 0x0214 #define SPSN_ID_S25FL032A 0x0215 #define SPSN_ID_S25FL064A 0x0216 #define SPSN_ID_S25FL128S 0x0219 #define SPSN_ID_S25FL128P 0x2018 +#define SPSN_ID_S25FL208K 0x4014 #define SPSN_ID_S25FL116K 0x4015 +#define SPSN_ID_S25FL132K 0x4016 +#define SPSN_ID_S25FL164K 0x4017 #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 #define SPSN_EXT_ID_S25FL032P 0x4d00 @@ -176,10 +179,20 @@ .page_size = 256, .pages_per_sector = 256, .nr_sectors = 256, - .name = "25FS128S", + .name = "S25FS128S", }, { - .idcode0 = SPSN_MANUFACTURER_ID_S25FL116K, + .idcode0 = SPSN_MANUFACTURER_ID_S25FL_K, + .idcode1 = SPSN_ID_S25FL208K, + .idcode2 = 0, + .identify = identify_123, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "S25FL208K", + }, + { + .idcode0 = SPSN_MANUFACTURER_ID_S25FL_K, .idcode1 = SPSN_ID_S25FL116K, .idcode2 = 0, .identify = identify_123, @@ -188,6 +201,26 @@ .nr_sectors = 32, .name = "S25FL116K_16M", }, + { + .idcode0 = SPSN_MANUFACTURER_ID_S25FL_K, + .idcode1 = SPSN_ID_S25FL132K, + .idcode2 = 0, + .identify = identify_123, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "S25FL132K", + }, + { + .idcode0 = SPSN_MANUFACTURER_ID_S25FL_K, + .idcode1 = SPSN_ID_S25FL164K, + .idcode2 = 0, + .identify = identify_123, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 128, + .name = "S25FL164K", + }, }; static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, -- To view, visit https://review.coreboot.org/c/coreboot/+/30874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bf7197bbc0d12797c8ed100c673628de9c140f7 Gerrit-Change-Number: 30874 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: buildsystem: Promote rules.h to default include
by Kyösti Mälkki (Code Review) 14 Jan '19

14 Jan '19

Hello Patrick Rudolph, Aaron Durbin, Julius Werner, Paul Menzel, build bot (Jenkins), Philipp Hug, Patrick Georgi, Furquan Shaikh, ron minnich, David Guckian, Vanny E, Huang Jin, York Yang, Lee Leahy, Jonathan Neuschäfer, Nico Huber, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/17656 to look at the new patch set (#9). Change subject: buildsystem: Promote rules.h to default include ...................................................................... buildsystem: Promote rules.h to default include Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Makefile.inc M src/arch/arm64/boot.c M src/arch/riscv/boot.c M src/arch/riscv/stages.c M src/arch/x86/acpi_s3.c M src/arch/x86/exception.c M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/early_variables.h M src/arch/x86/include/arch/exception.h M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/memlayout.h M src/arch/x86/rdrand.c M src/commonlib/storage/pci_sdhci.c M src/console/console.c M src/console/init.c M src/console/post.c M src/cpu/intel/microcode/microcode.c M src/cpu/x86/32bit/entry32.inc M src/cpu/x86/pae/pgtbl.c M src/drivers/intel/fsp1_1/cache_as_ram.inc M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/net/ne2k.c M src/drivers/spi/spi_flash.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/bootstate.h M src/include/cbmem.h M src/include/console/cbmem_console.h M src/include/console/console.h M src/include/console/flash.h M src/include/console/ne2k.h M src/include/console/qemu_debugcon.h M src/include/console/spi.h M src/include/console/spkmodem.h M src/include/console/uart.h M src/include/console/usb.h M src/include/device/device.h M src/include/device/pci.h M src/include/device/pnp.h M src/include/memlayout.h M src/include/stddef.h M src/lib/bootmode.c M src/lib/cbmem_common.c M src/lib/ext_stage_cache.c M src/lib/imd_cbmem.c M src/lib/prog_loaders.c M src/lib/romstage_handoff.c M src/lib/timestamp.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/kahlee/ec.c M src/mainboard/google/octopus/ec.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/reef/ec.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/storm/mmu.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/glkrvp/ec.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/northbridge/intel/fsp_rangeley/northbridge.h M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/sandybridge/sandybridge.h M src/security/vboot/bootmode.c M src/security/vboot/vboot_common.c M src/security/vboot/vboot_loader.c M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/include/soc/iosf.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/braswell/include/soc/smm.h M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/spi.c M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/pmutil.c M src/southbridge/amd/rs780/rs780.h M src/southbridge/intel/bd82x6x/early_pch_common.c 98 files changed, 1 insertion(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/17656/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/17656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Gerrit-Change-Number: 17656 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> 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Change in ...coreboot[master]: mb/supermicro/a2sdi-4c-hln4f: Add mainboard
by Felix Singer (Code Review) 14 Jan '19

14 Jan '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30898 Change subject: mb/supermicro/a2sdi-4c-hln4f: Add mainboard ...................................................................... mb/supermicro/a2sdi-4c-hln4f: Add mainboard WIP Change-Id: Ibdd8a831db095efdcfcc458f6373c78a8c23ac9e Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A src/mainboard/supermicro/a2sdi-4c-hln4f/Kconfig A src/mainboard/supermicro/a2sdi-4c-hln4f/Kconfig.name A src/mainboard/supermicro/a2sdi-4c-hln4f/Makefile.inc A src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/mainboard.asl A src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/mainboard_pci_irqs.asl A src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/platform.asl A src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/thermal.asl A src/mainboard/supermicro/a2sdi-4c-hln4f/acpi_tables.c A src/mainboard/supermicro/a2sdi-4c-hln4f/board_info.txt A src/mainboard/supermicro/a2sdi-4c-hln4f/devicetree.cb A src/mainboard/supermicro/a2sdi-4c-hln4f/dsdt.asl A src/mainboard/supermicro/a2sdi-4c-hln4f/fadt.c A src/mainboard/supermicro/a2sdi-4c-hln4f/ramstage.c 13 files changed, 197 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30898/1 diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/Kconfig b/src/mainboard/supermicro/a2sdi-4c-hln4f/Kconfig new file mode 100644 index 0000000..3dccb78 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/Kconfig @@ -0,0 +1,41 @@ +if BOARD_SUPERMICRO_A2SDI_4C_HLN4F + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_DENVERTON_NS + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default supermicro/a2sdi-4c-hln4f + +config MAINBOARD_PART_NUMBER + string + default "A2SDI-4C-HLN4F" + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x0969 + +config CBFS_SIZE + hex + default 0x800000 + +config DIMM_MAX + int + default 4 + +config DIMM_SPD_SIZE + int + default 512 + +config PXE_ROM_ID + string + default "8086,15e4" + +endif diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/Kconfig.name b/src/mainboard/supermicro/a2sdi-4c-hln4f/Kconfig.name new file mode 100644 index 0000000..ee8992a --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_A2SDI_4C_HLN4F + bool "A2SDI-4C-HLN4F" diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/Makefile.inc b/src/mainboard/supermicro/a2sdi-4c-hln4f/Makefile.inc new file mode 100644 index 0000000..0d1aea5 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += ramstage.c diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/mainboard.asl b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/mainboard.asl diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/mainboard_pci_irqs.asl b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/mainboard_pci_irqs.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/mainboard_pci_irqs.asl diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/platform.asl b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/platform.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/platform.asl diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/thermal.asl b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/thermal.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi/thermal.asl diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi_tables.c b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi_tables.c new file mode 100644 index 0000000..48deb5f --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/acpi_tables.c @@ -0,0 +1,24 @@ +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/board_info.txt b/src/mainboard/supermicro/a2sdi-4c-hln4f/board_info.txt new file mode 100644 index 0000000..1d9347f --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Supermicro +Board name: N130WU +Category: Server +Release year: 2018 +ROM package: SOIC-16 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/devicetree.cb b/src/mainboard/supermicro/a2sdi-4c-hln4f/devicetree.cb new file mode 100644 index 0000000..419d651 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/devicetree.cb @@ -0,0 +1,74 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 - 2017 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +chip soc/intel/denverton_ns + + # configure pirq routing + register "pirqa_routing" = "11" + register "pirqb_routing" = "10" + register "pirqc_routing" = "06" + register "pirqd_routing" = "07" + register "pirqe_routing" = "12" + register "pirqf_routing" = "14" + register "pirqg_routing" = "15" + register "pirqh_routing" = "15" + + # configure device interrupt routing + register "ir00_routing" = "0x3217" # IR00, Dev31 + register "ir01_routing" = "0x3210" # IR01, Dev22 + register "ir02_routing" = "0x3211" # IR02, Dev23 + register "ir03_routing" = "0x3217" # IR03, Dev5 + register "ir04_routing" = "0x3212" # IR04, Dev6 + register "ir05_routing" = "0x3210" # IR05, Dev24 + register "ir06_routing" = "0x3214" # IR06, Dev19 + register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12 + register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17 + register "ir09_routing" = "0x3213" # IR09, Dev21 + register "ir10_routing" = "0x3210" # IR10, Dev26/18 + register "ir11_routing" = "0x3215" # IR11, Dev20 + register "ir12_routing" = "0x3210" # IR12, Dev27 + + # configure interrupt polarity control + register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow + register "ipc1" = "0x00000000" # IPC1 + register "ipc2" = "0x00000000" # IPC2 + register "ipc3" = "0x00000000" # IPC3 + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 04.0 on end # RAS + device pci 05.0 on end # RCEC(Root Complex Event Collector) + device pci 06.0 on end # Virtual root port 2 (QAT) + device pci 09.0 on end # PCI Express Port 0, cluster #0, x8 + device pci 0e.0 on end # PCI Express Port 4, cluster #1, x4 + device pci 10.0 on end # PCI Express Port 6, cluster #1, x4 + device pci 12.0 on end # SMBus Controller 1 + device pci 14.0 on end # SATA Controller 1 + device pci 15.0 on end # XHCI USB Controller + device pci 16.0 on end # Virtual root port 0 (10GBE0) + device pci 17.0 on end # Virtual root port 1 (10GBE1) + device pci 18.0 on end # CSME HECI 1 + device pci 1a.0 on end # UART 0 + device pci 1a.1 on end # UART 1 + device pci 1a.2 on end # UART 2 + device pci 1c.0 on end # eMMC + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # PMC/ACPI + device pci 1f.4 on end # SMBus Controller 0 + device pci 1f.5 on end # SPI Controller + end +end diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/dsdt.asl b/src/mainboard/supermicro/a2sdi-4c-hln4f/dsdt.asl new file mode 100644 index 0000000..91ade69 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/dsdt.asl @@ -0,0 +1,34 @@ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // General Purpose Events + //#include "acpi/gpe.asl" + + // Thermal Handler + #include "acpi/thermal.asl" + + // global NVS and variables + #include <soc/intel/denverton_ns/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/denverton_ns/acpi/northcluster.asl> + #include <soc/intel/denverton_ns/acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/denverton_ns/acpi/sleepstates.asl> +} diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/fadt.c b/src/mainboard/supermicro/a2sdi-4c-hln4f/fadt.c new file mode 100644 index 0000000..8041641 --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/fadt.c @@ -0,0 +1,8 @@ +#include <string.h> +#include <arch/acpi.h> +#include <soc/acpi.h> +#include <soc/soc_util.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} diff --git a/src/mainboard/supermicro/a2sdi-4c-hln4f/ramstage.c b/src/mainboard/supermicro/a2sdi-4c-hln4f/ramstage.c new file mode 100644 index 0000000..134dfd5f --- /dev/null +++ b/src/mainboard/supermicro/a2sdi-4c-hln4f/ramstage.c @@ -0,0 +1,5 @@ +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdd8a831db095efdcfcc458f6373c78a8c23ac9e Gerrit-Change-Number: 30898 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: sb/intel/i82801gx: Implement PCIe coalescing
by Nico Huber (Code Review) 13 Jan '19

13 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30320 ) Change subject: sb/intel/i82801gx: Implement PCIe coalescing ...................................................................... Patch Set 12: Code-Review+2 (2 comments) https://review.coreboot.org/#/c/30320/12/src/southbridge/intel/i82801gx/pci… File src/southbridge/intel/i82801gx/pcie.c: https://review.coreboot.org/#/c/30320/12/src/southbridge/intel/i82801gx/pci… PS12, Line 30: int coalesce; Caching `coalesce` doesn't seem necessary as you can also read it from `config` when checking `rpc.ports[0].enable`. https://review.coreboot.org/#/c/30320/12/src/southbridge/intel/i82801gx/pci… PS12, Line 125: struct device *dev = pcidev_path_on_root(PCI_DEVFN(31, 0)); same as `pcidev_on_root(31, 0)` -- To view, visit https://review.coreboot.org/c/coreboot/+/30320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273 Gerrit-Change-Number: 30320 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Sun, 13 Jan 2019 22:41:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/clevo/n130wu: Add mainboard
by Felix Singer (Code Review) 13 Jan '19

13 Jan '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28640 ) Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... Patch Set 65: > Patch Set 63: > > Please add the variant in a separate commit on top. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 65 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-Comment-Date: Sun, 13 Jan 2019 20:57:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/clevo/n130wu: Add mainboard
by build bot (Jenkins) (Code Review) 13 Jan '19

13 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28640 ) Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... Patch Set 65: (4 comments) https://review.coreboot.org/#/c/28640/65/src/mainboard/clevo/n130wu/gpio.h File src/mainboard/clevo/n130wu/gpio.h: https://review.coreboot.org/#/c/28640/65/src/mainboard/clevo/n130wu/gpio.h@… PS65, Line 168: /* I2C5_SDA/ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), line over 80 characters https://review.coreboot.org/#/c/28640/65/src/mainboard/clevo/n130wu/gpio.h@… PS65, Line 169: /* I2C5_SCL/ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), line over 80 characters https://review.coreboot.org/#/c/28640/65/src/mainboard/clevo/n130wu/pei_dat… File src/mainboard/clevo/n130wu/pei_data.c: https://review.coreboot.org/#/c/28640/65/src/mainboard/clevo/n130wu/pei_dat… PS65, Line 31: 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; space required after that close brace '}' https://review.coreboot.org/#/c/28640/65/src/mainboard/clevo/n130wu/pei_dat… PS65, Line 40: {1, 0, 4, 5, 2, 3, 6, 7}}; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 65 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-Comment-Date: Sun, 13 Jan 2019 20:35:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019