coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: Revert "mb/google/kalista: Disable EC-EFS"
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Hello Aaron Durbin, Zhuohao Lee, Daisuke Nojiri, build bot (Jenkins), I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30857 to review the following change. Change subject: Revert "mb/google/kalista: Disable EC-EFS" ...................................................................... Revert "mb/google/kalista: Disable EC-EFS" This reverts commit 4e3cd744492c7a3d80bca55a35276efeada731e5. Reason for revert: Daisuke says "We'll keep EFS on … [View More]

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 14 Jan '19

14 Jan '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 33: (2 comments) > Patch Set 33: > > >> The more I'm thinking about this the more I realize that I don't > >> understand the purpose of this update mechanism. > >> > >> For being able to … [View More]perform the update, you already need a RO MCU that > >> works good enough to get you to ramstage. At this point, you can > >> already apply additional MCUs from any RW partition. So what kind of > >> issue would have to be fixed by an update that makes use of this > >> mechanism? > >> > >> In other words, what problem can this new update mechanism fix, that > >> current mechanisms can't? And is it worth the added complexity and > >> accompanying security degradation (more code is always more error- > >> prone)? > > > > Microcode patch contains patch for Punit as well, and that has to > > be applied prior to reset. > > Ah, understood. Thanks for the clarification. > > Ofc, it's too late for current products. But is there any change > planned for the FIT update mechanism. e.g. a rule that multiple > updates for one processor signature are allowed and the newest would > be applied. That would make this much easier, would allow a single > RO FIT with some entries pointing to RO and some to the MCU RW and > we wouldn't need the top-swap feature any more. > If you haven't tried, add multiple microcode patches in FIT for the same processor signature, you will find that FIT will pick the latest revision and load. However there is no fallback if there is a failure. 2 FITs, 1 for normal boot, another for recovery boot. Even if the CPU manages to load the latest revision (from the normal boot FIT) and that results in a hang/reboot loop. We need a tried and tested patch to recover from the hang/reboot for which the top-swap FIT will be used. > > Hence the effort to load the updated microcode via FIT. > > This is probably the most urgent thing to mention in the commit > message. Without this reasoning, it looks like you are just playing > around and Intel adds complexity just because they can. Ok. will update the commit message. https://review.coreboot.org/#/c/27369/30/src/soc/intel/common/basecode/fw_u… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/#/c/27369/30/src/soc/intel/common/basecode/fw_u… PS30, Line 103: static int protect_staging(void) > should be called in BS_POST_DEVICE Claim an FPR and set the range as soon as you get an opportunity. Do you see a problem? https://review.coreboot.org/#/c/27369/30/src/soc/intel/common/basecode/fw_u… PS30, Line 118: check_and_update_ucode > I think it would be good to check the FIT table itself too? Because the FIT table will be in RO. I don't think we need to check that. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 33 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 14 Jan 2019 14:25:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment [View Less]

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Change in ...coreboot[master]: nb/intel/i945: Use parallel MP init
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Hello Patrick Rudolph, HAOUAS Elyes, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25600 to look at the new patch set (#38). Change subject: nb/intel/i945: Use parallel MP init ...................................................................... nb/intel/i945: Use parallel MP init Use the parallel mp init path to initialize AP's. This should result in a … [View More]

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Change in ...coreboot[master]: nb/intel/gm45: Use parallel MP init
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Hello Patrick Rudolph, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/23434 to look at the new patch set (#47). Change subject: nb/intel/gm45: Use parallel MP init ...................................................................... nb/intel/gm45: Use parallel MP init This places the parallel mp ops up in the model_1067x dir and is included from other Intel … [View More]

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Change in ...coreboot[master]: cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30868 to look at the new patch set (#2). Change subject: cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's ...................................................................... cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's Intel pineview has the same alternative SMRR MSR and IA32_FEATURE_CONTROL enable … [View More]

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Change in ...coreboot[master]: binaryPI: Fix missing AMD_PI_BOLTON blobs
by Kyösti Mälkki (Code Review) 14 Jan '19

14 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30911 Change subject: binaryPI: Fix missing AMD_PI_BOLTON blobs ...................................................................... binaryPI: Fix missing AMD_PI_BOLTON blobs These were left out by mistake while rebasing, when AGESA/binaryPI directory split happened. Change-Id: Id0cb07e9ad7edede60cd9daa9a4772dc9b893c16 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/… [View More]

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Change in ...coreboot[master]: vendorcode/eltan: Add vendor code for measured and verified boot
by Frans Hendriks (Code Review) 14 Jan '19

14 Jan '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30218 ) Change subject: vendorcode/eltan: Add vendor code for measured and verified boot ...................................................................... Patch Set 8: > Patch Set 7: > > BTW, you can add all the related patches to the same gerrit topic so that it is easier to keep track of them. There is also the option of using patch trains, so that you build on previous, not yet … [View More]

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Change in ...coreboot[master]: src/superio/smsc/smscsuperio/superio.c: Add SCH5504
by Felix Held (Code Review) 14 Jan '19

14 Jan '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28971 ) Change subject: src/superio/smsc/smscsuperio/superio.c: Add SCH5504 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/28971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: … [View More]

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Change in ...coreboot[master]: mainboard/ocp/wedge100s: Fix uart
by Felix Held (Code Review) 14 Jan '19

14 Jan '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30827 ) Change subject: mainboard/ocp/wedge100s: Fix uart ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/30827/1/src/mainboard/ocp/wedge100s/romstag… File src/mainboard/ocp/wedge100s/romstage.c: https://review.coreboot.org/#/c/30827/1/src/mainboard/ocp/wedge100s/romstag… PS1, Line 96: } > That should … [View More]

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Change in ...coreboot[master]: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27586 ) Change subject: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/#/c/27586/26//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27586/26//COMMIT_MSG@14 PS26, Line 14: the possibility to not lock VMX > CONFIG_ENABLE_VMX is separate from … [View More]

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coreboot-gerrit January 2019