coreboot-gerrit January 2019

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Change in ...coreboot[master]: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27586 ) Change subject: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/#/c/27586/26//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27586/26//COMMIT_MSG@14 PS26, Line 14: the possibility to not lock VMX > set_vmx_and_lock() is still called, just from somewhere else. […] CONFIG_ENABLE_VMX is separate from CONFIG_SET_IA32_FC_LOCK_BIT. The option to (not) lock VMX with CONFIG_SET_IA32_FC_LOCK_BIT is still there for CPU's not supporting SMRR or don't need the SMRR_ENABLE bit in IA32_FEATURE_CONTROL. It might be confusing however... Should I select CONFIG_SET_IA32_FC_LOCK_BIT in the CPU Kconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/27586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Gerrit-Change-Number: 27586 Gerrit-PatchSet: 26 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Jan 2019 12:05:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: /src/mb/google/poppy/variants/atlas: Revise SPK reset
by Gaggery Tsai (Code Review) 14 Jan '19

14 Jan '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30866 Change subject: /src/mb/google/poppy/variants/atlas: Revise SPK reset ...................................................................... /src/mb/google/poppy/variants/atlas: Revise SPK reset This patch revises the pad reset config of speaker reset GPIO pin from RSMRST to PLTRST. Audio engineer suggested to reset the amps with warm reset. BUG=b:122441567 BRANCH=None TEST=warm & cold reset & suspend_stress_test -c 10 and ensure the speakers are working well. Change-Id: I87c554b186b068da93e1662a97afaf01dddae0ef Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30866/1 diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 02c145c..c8203df 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -275,7 +275,7 @@ /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */ PAD_CFG_GPI_APIC(GPP_F10, 20K_PU, PLTRST), /* F11 : I2C5_SCL ==> SPKR_RST_L */ - PAD_CFG_GPO(GPP_F11, 1, RSMRST), + PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* F12 : EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* F13 : EMMC_DATA0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c554b186b068da93e1662a97afaf01dddae0ef Gerrit-Change-Number: 30866 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: Update mainboard UART Kconfig for whlrvp
by Wonkyu Kim (Code Review) 14 Jan '19

14 Jan '19

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30861 Change subject: Update mainboard UART Kconfig for whlrvp ...................................................................... Update mainboard UART Kconfig for whlrvp Change-Id: Ic56c019a12b467e5bede5648098d3fb82b56ba7e Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30861/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 9474c51..1634e71 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -7,6 +7,7 @@ select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE if BOARD_INTEL_WHISKEYLAKE_RVP select MAINBOARD_HAS_CHROMEOS select GENERIC_SPD_BIN select DRIVERS_I2C_HID @@ -48,6 +49,10 @@ default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 default 8 +config UART_FOR_CONSOLE + int + default 2 + config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -- To view, visit https://review.coreboot.org/c/coreboot/+/30861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56c019a12b467e5bede5648098d3fb82b56ba7e Gerrit-Change-Number: 30861 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/pineview: Move the boilerplate mainboard_romstage_entry
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30851 Change subject: nb/intel/pineview: Move the boilerplate mainboard_romstage_entry ...................................................................... nb/intel/pineview: Move the boilerplate mainboard_romstage_entry The mainboard_romstage_entry function is mostly boilerplate, so move it to a common location and provide mainboard specific callbacks. Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/intel/d510mo/romstage.c M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/pineview.h A src/northbridge/intel/pineview/romstage.c 5 files changed, 140 insertions(+), 192 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/30851/1 diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index cde813c..ade85e6 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -15,44 +15,16 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> -#include <northbridge/intel/pineview/raminit.h> #include <northbridge/intel/pineview/pineview.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <cpu/x86/lapic.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> -#include <lib.h> -#include <cbmem.h> -#include <romstage_handoff.h> -#include <timestamp.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) -/* Early mainboard specific GPIO setup */ -static void mb_gpio_init(void) -{ - pci_devfn_t dev; - - /* Southbridge GPIOs. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); -} - -static void nm10_enable_lpc(void) +void mb_enable_lpc(void) { /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); @@ -65,75 +37,12 @@ /* Environment Controller */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); -} -static void rcba_config(void) -{ - /* Set up virtual channel 0 */ - RCBA32(0x0014) = 0x80000001; - RCBA32(0x001c) = 0x03128010; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; -} - -void mainboard_romstage_entry(unsigned long bist) -{ - const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; - int cbmem_was_initted; - int s3resume = 0; - int boot_path; - - if (bist == 0) - enable_lapic(); - - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - - /* Set southbridge and Super I/O GPIOs. */ - mb_gpio_init(); - - nm10_enable_lpc(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); +} - report_bist_failure(bist); - enable_smbus(); - - pineview_early_initialization(); - - post_code(0x30); - - s3resume = southbridge_detect_s3_resume(); - - if (s3resume) { - boot_path = BOOT_PATH_RESUME; - } else { - if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */ - boot_path = BOOT_PATH_RESET; - else - boot_path = BOOT_PATH_NORMAL; - } - - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - printk(BIOS_DEBUG, "Memory initialized\n"); - - post_code(0x31); - - quick_ram_check(); - - rcba_config(); - - cbmem_was_initted = !cbmem_recovery(s3resume); - - if (!cbmem_was_initted && s3resume) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - - romstage_handoff_init(s3resume); +void get_mb_spd_addrmap(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[1] = 0x51; } diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 8648e20..f0544be 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -14,45 +14,17 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> -#include <northbridge/intel/pineview/raminit.h> #include <northbridge/intel/pineview/pineview.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <cpu/x86/lapic.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <superio/winbond/common/winbond.h> -#include <lib.h> -#include <cbmem.h> -#include <romstage_handoff.h> -#include <timestamp.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) -/* Early mainboard specific GPIO setup */ -static void mb_gpio_init(void) -{ - pci_devfn_t dev; - - /* Southbridge GPIOs. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); -} - -static void nm10_enable_lpc(void) +static void mb_enable_lpc(void) { /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); @@ -64,14 +36,12 @@ | COMB_LPC_EN); pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -static void rcba_config(void) +void mb_pirq_setup(void) { - /* Set up virtual channel 0 */ - RCBA32(0x0014) = 0x80000001; - RCBA32(0x001c) = 0x03128010; - /* dev irq route register */ RCBA16(D31IR) = 0x0132; RCBA16(D30IR) = 0x0146; @@ -79,69 +49,12 @@ RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x0146; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - + /* Does not belong here, but is it needed? */ RCBA32(FD) |= FD_INTLAN; } -void mainboard_romstage_entry(unsigned long bist) +void get_mb_spd_addrmap(u8 *spd_addrmap) { - const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; - int cbmem_was_initted; - int s3resume = 0; - int boot_path; - - if (bist == 0) - enable_lapic(); - - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - - /* Set southbridge and Super I/O GPIOs. */ - mb_gpio_init(); - - nm10_enable_lpc(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - report_bist_failure(bist); - enable_smbus(); - - pineview_early_initialization(); - - post_code(0x30); - - s3resume = southbridge_detect_s3_resume(); - - if (s3resume) { - boot_path = BOOT_PATH_RESUME; - } else { - if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */ - boot_path = BOOT_PATH_RESET; - else - boot_path = BOOT_PATH_NORMAL; - } - - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - printk(BIOS_DEBUG, "Memory initialized\n"); - - post_code(0x31); - - quick_ram_check(); - - rcba_config(); - - cbmem_was_initted = !cbmem_recovery(s3resume); - - if (!cbmem_was_initted && s3resume) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - - romstage_handoff_init(s3resume); + spd_addrmap[0] = 0x50; + spd_addrmap[1] = 0x51; } diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index d7936c1..524bcae 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -21,6 +21,7 @@ ramstage-y += gma.c ramstage-y += acpi.c +romstage-y += romstage.c romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 9873d4d..7378a78 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -235,6 +235,11 @@ u32 decode_igd_gtt_size(const u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); +/* Mainboard romstage callback */ +void mb_enable_lpc(void); +void get_mb_spd_addrmap(u8 *spd_addr_map); +void mb_pirq_setup(void); /* optional */ + /* provided by mainboard code */ void setup_ich7_gpios(void); diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c new file mode 100644 index 0000000..10ac0f5 --- /dev/null +++ b/src/northbridge/intel/pineview/romstage.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Platform has no romstage entry point under mainboard directory, + * so this one is named with prefix mainboard. + */ + +#include <lib.h> +#include <timestamp.h> +#include <console/console.h> +#include <cbmem.h> +#include <romstage_handoff.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/gpio.h> +#include <cpu/intel/romstage.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include "raminit.h" +#include "pineview.h" + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(0x0014) = 0x80000001; + RCBA32(0x001c) = 0x03128010; + + /* Enable IOAPIC */ + RCBA8(OIC) = 0x03; +} + +__weak void mb_pirq_setup(void) +{ +} + +#define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0) + +void mainboard_romstage_entry(unsigned long bist) +{ + u8 spd_addrmap[4] = {}; + int boot_path, cbmem_was_initted; + int s3resume = 0; + + if (bist == 0) + enable_lapic(); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; + + /* Enable GPIOs */ + pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + mb_enable_lpc(); // nm10_enable_lpc + + /* Initialize console device(s) */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + enable_smbus(); + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + pineview_early_initialization(); + + post_code(0x30); + + s3resume = southbridge_detect_s3_resume(); + + if (s3resume) { + boot_path = BOOT_PATH_RESUME; + } else { + if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */ + boot_path = BOOT_PATH_RESET; + else + boot_path = BOOT_PATH_NORMAL; + } + + get_mb_spd_addrmap(&spd_addrmap[0]); + + printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + printk(BIOS_DEBUG, "Memory initialized\n"); + + post_code(0x31); + + quick_ram_check(); + + mb_pirq_setup(); + + rcba_config(); + + cbmem_was_initted = !cbmem_recovery(s3resume); + + if (!cbmem_was_initted && s3resume) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } + + romstage_handoff_init(s3resume); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b Gerrit-Change-Number: 30851 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/{i945,pineview}: Remove unused function
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30852 Change subject: nb/intel/{i945,pineview}: Remove unused function ...................................................................... nb/intel/{i945,pineview}: Remove unused function Change-Id: I6ca83bde61f231b9f79c90af1d6c1cfa1a027768 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/i945.h M src/northbridge/intel/pineview/pineview.h 2 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/30852/1 diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 65a40e7..06414f5 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -371,9 +371,6 @@ void i945_early_initialization(void); void i945_late_initialization(int s3resume); -/* provided by mainboard code */ -void setup_ich7_gpios(void); - /* debugging functions */ void print_pci_devices(void); void dump_pci_device(unsigned int dev); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 7378a78..8172bcd 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -240,9 +240,6 @@ void get_mb_spd_addrmap(u8 *spd_addr_map); void mb_pirq_setup(void); /* optional */ -/* provided by mainboard code */ -void setup_ich7_gpios(void); - struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); -- To view, visit https://review.coreboot.org/c/coreboot/+/30852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca83bde61f231b9f79c90af1d6c1cfa1a027768 Gerrit-Change-Number: 30852 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/variants: Configure PLT_RST_L pad IOSSTATE masked
by John Zhao (Code Review) 14 Jan '19

14 Jan '19

Hello John Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30815 to review the following change. Change subject: mb/google/octopus/variants: Configure PLT_RST_L pad IOSSTATE masked ...................................................................... mb/google/octopus/variants: Configure PLT_RST_L pad IOSSTATE masked PLT_RST_L was asserted twice at boot-up and a glitch was observed when coming out of suspend mode. Configure PLT_RST_L pad IOSSTATE from HIZCRx1 to be masked. BUG=b:117302959 TEST=Verified no glitch on PLT_RST_L at S3 and PLT_RST_L stays high 3.3v during S0ix. Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/mainboard/google/octopus/variants/ampton/gpio.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bip/gpio.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30815/1 diff --git a/src/mainboard/google/octopus/variants/ampton/gpio.c b/src/mainboard/google/octopus/variants/ampton/gpio.c index f34645d..201db9e 100644 --- a/src/mainboard/google/octopus/variants/ampton/gpio.c +++ b/src/mainboard/google/octopus/variants/ampton/gpio.c @@ -137,7 +137,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ /* PMU Signals */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, MASK, DISPUPD),/* PMU_PLTRST_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 566422d..2ce44d7 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -138,7 +138,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ /* PMU Signals */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, MASK, DISPUPD),/* PMU_PLTRST_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index b319a0e..343c9aa 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -137,7 +137,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ /* PMU Signals */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, MASK, DISPUPD),/* PMU_PLTRST_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae Gerrit-Change-Number: 30815 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86: Enforce CPU stack alignment
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/26302 ) Change subject: arch/x86: Enforce CPU stack alignment ...................................................................... arch/x86: Enforce CPU stack alignment When rmodule is loaded CPU stack alignment is only guaranteed to 4kiB. Implementation of cpu_info() requires that each CPU sees its stack aligned to CONFIG_STACK_SIZE. Add one spare CPU for the stack reserve, such that alignment can be enforced runtime. Change-Id: Ie04956c64df0dc7bb156002d3d4f2629f92b340e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/26302 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/c_start.S M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c 3 files changed, 21 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Aaron Durbin: Looks good to me, approved diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 3fbdac1..86147ec 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -19,9 +19,11 @@ .global _stack .global _estack +/* Stack alignment is not enforced with rmodule loader, reserve one + * extra CPU such that alignment can be enforced on entry. */ .align CONFIG_STACK_SIZE _stack: -.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE +.space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE _estack: #if IS_ENABLED(CONFIG_COOP_MULTITASKING) .global thread_stacks @@ -70,8 +72,9 @@ rep stosl - /* set new stack */ + /* Set new stack with enforced alignment. */ movl $_estack, %esp + andl $(~(CONFIG_STACK_SIZE-1)), %esp #if IS_ENABLED(CONFIG_COOP_MULTITASKING) /* Push the thread pointer. */ diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 4498b97..7daca0a 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -263,8 +263,8 @@ int start_cpu(struct device *cpu) { struct cpu_info *info; - unsigned long stack_end; - unsigned long stack_base; + uintptr_t stack_top; + uintptr_t stack_base; unsigned long apicid; unsigned int index; unsigned long count; @@ -278,23 +278,23 @@ /* Get an index for the new processor */ index = ++last_cpu_index; - /* Find end of the new processor's stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - - sizeof(struct cpu_info); - - stack_base = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*(index+1)); - printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_end %p\n", index, - (void *)stack_base, (void *)stack_end); + /* Find boundaries of the new processor's stack */ + stack_top = ALIGN_DOWN((uintptr_t)_estack, CONFIG_STACK_SIZE); + stack_top -= (CONFIG_STACK_SIZE*index); + stack_base = stack_top - CONFIG_STACK_SIZE; + stack_top -= sizeof(struct cpu_info); + printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_top %p\n", index, + (void *)stack_base, (void *)stack_top); stacks[index] = (void *)stack_base; /* Record the index and which CPU structure we are using */ - info = (struct cpu_info *)stack_end; + info = (struct cpu_info *)stack_top; info->index = index; info->cpu = cpu; thread_init_cpu_info_non_bsp(info); /* Advertise the new stack and index to start_cpu */ - secondary_stack = stack_end; + secondary_stack = stack_top; secondary_cpu_index = index; /* Until the CPU starts up report the CPU is not enabled */ diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9526824..3889c7d 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <rmodule.h> #include <arch/cpu.h> +#include <commonlib/helpers.h> #include <cpu/cpu.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> @@ -229,11 +230,11 @@ static void setup_default_sipi_vector_params(struct sipi_params *sp) { - sp->gdt = (uint32_t)&gdt; - sp->gdtlimit = (uint32_t)&gdt_end - (u32)&gdt - 1; - sp->idt_ptr = (uint32_t)&idtarg; + sp->gdt = (uintptr_t)&gdt; + sp->gdtlimit = (uintptr_t)&gdt_end - (uintptr_t)&gdt - 1; + sp->idt_ptr = (uintptr_t)&idtarg; sp->stack_size = CONFIG_STACK_SIZE; - sp->stack_top = (uint32_t)&_estack; + sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE); /* Adjust the stack top to take into account cpu_info. */ sp->stack_top -= sizeof(struct cpu_info); } -- To view, visit https://review.coreboot.org/c/coreboot/+/26302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie04956c64df0dc7bb156002d3d4f2629f92b340e Gerrit-Change-Number: 26302 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/octopus/variants: Disable xHCI compliance mode
by John Zhao (Code Review) 14 Jan '19

14 Jan '19

Hello John Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30817 to review the following change. Change subject: mb/google/octopus/variants: Disable xHCI compliance mode ...................................................................... mb/google/octopus/variants: Disable xHCI compliance mode Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BUG=b:115699781 CQ-DEPEND=CL:*30816 TEST=Verified usb operation successfully. Change-Id: I41fecaa43f4b1588a0e4bbfc465d595feb54dd24 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/mainboard/google/octopus/variants/bobba/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/30817/1 diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 9706e69..04dc768 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -163,4 +163,7 @@ end end # - I2C 7 end + + # Disable compliance mode + register "DisableComplianceMode" = "1" end -- To view, visit https://review.coreboot.org/c/coreboot/+/30817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41fecaa43f4b1588a0e4bbfc465d595feb54dd24 Gerrit-Change-Number: 30817 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake: Add option to disable xHCI Link Compliance Mode
by John Zhao (Code Review) 14 Jan '19

14 Jan '19

Hello John Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30816 to review the following change. Change subject: soc/intel/apollolake: Add option to disable xHCI Link Compliance Mode ...................................................................... soc/intel/apollolake: Add option to disable xHCI Link Compliance Mode Provide options to disable xHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. BUG=b:115699781 TEST=Verified booting to kernel. Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30816/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1c8f321..b38265f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -571,8 +571,13 @@ * FSP provides UPD interface to execute IPC command. In order to * improve boot performance, configure PmicPmcIpcCtrl for PMC to program * PMIC PCH_PWROK delay. - */ + */ silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl; + + /* + * Options to disable XHCI Link Compliance Mode. + */ + silconfig->DisableComplianceMode = cfg->DisableComplianceMode; #endif } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 202f2ac..b9c9dc5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -162,6 +162,12 @@ * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) */ uint32_t PmicPmcIpcCtrl; + + /* Options to disable XHCI Link Compliance Mode. Default is FALSE to not + * disable Compliance Mode. Set TRUE to disable Compliance Mode. + * 0:FALSE(Default), 1:True. + */ + uint8_t DisableComplianceMode; }; typedef struct soc_intel_apollolake_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/30816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4 Gerrit-Change-Number: 30816 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/[xtz]60: Introduce and use RCBA64 macro
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30802 ) Change subject: mb/lenovo/[xtz]60: Introduce and use RCBA64 macro ...................................................................... mb/lenovo/[xtz]60: Introduce and use RCBA64 macro Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/30802 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/southbridge/intel/common/rcba.h 4 files changed, 7 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 72dd8b4..3017357 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -100,12 +100,10 @@ RCBA32(FD) |= FD_INTLAN; /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA32(IOTR0) = 0x0000fe01; - RCBA32(IOTR0+4) = 0x00020001; + RCBA64(IOTR0) = 0x000200010000fe01ULL; /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(IOTR3) = 0x000c0801; - RCBA32(IOTR3+4) = 0x000200f0; + RCBA64(IOTR3) = 0x000200f0000c0801ULL; } static void early_ich7_init(void) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 8943f97..6f66c88 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -99,12 +99,10 @@ RCBA32(FD) |= FD_INTLAN; /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA32(IOTR0) = 0x0000fe01; - RCBA32(IOTR0+4) = 0x00020001; + RCBA64(IOTR0) = 0x000200010000fe01ULL; /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(IOTR3) = 0x000c0801; - RCBA32(IOTR3+4) = 0x000200f0; + RCBA64(IOTR3) = 0x000200f0000c0801ULL; } static void early_ich7_init(void) diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 966d0e5..6eceaeb 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -100,12 +100,10 @@ RCBA32(FD) |= FD_INTLAN; /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA32(IOTR0) = 0x0000fe01; - RCBA32(IOTR0+4) = 0x00020001; + RCBA64(IOTR0) = 0x000200010000fe01ULL; /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(IOTR3) = 0x000c0801; - RCBA32(IOTR3+4) = 0x000200f0; + RCBA64(IOTR3) = 0x000200f0000c0801ULL; } static void early_ich7_init(void) diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index e7482f9..225cd26 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -28,6 +28,7 @@ #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) #define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x))) +#define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + x))) #define RCBA_AND_OR(bits, x, and, or) \ (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) -- To view, visit https://review.coreboot.org/c/coreboot/+/30802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c Gerrit-Change-Number: 30802 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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