coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/apollolake: Hook up microcode
by Nico Huber (Code Review) 14 Jan '19

14 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30885 ) Change subject: soc/intel/apollolake: Hook up microcode ...................................................................... Patch Set 1: Please review CB:29902 instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/30885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b42dc00d82c9d80d72a911762e79a4e48809281 Gerrit-Change-Number: 30885 Gerrit-PatchSet: 1 Gerrit-Owner: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Mon, 14 Jan 2019 12:56:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/apl: Hook microcode updates up
by Nico Huber (Code Review) 14 Jan '19

14 Jan '19

Hello Patrick Rudolph, Angel Pons, Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29902 to look at the new patch set (#4). Change subject: soc/intel/apl: Hook microcode updates up ...................................................................... soc/intel/apl: Hook microcode updates up Only tested on APL. Change-Id: I53f680fc4342a9bd1cd0ba9d72e025995e25f7f2 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29902/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f680fc4342a9bd1cd0ba9d72e025995e25f7f2 Gerrit-Change-Number: 29902 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Nico Huber (Code Review) 14 Jan '19

14 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 33: >> The more I'm thinking about this the more I realize that I don't >> understand the purpose of this update mechanism. >> >> For being able to perform the update, you already need a RO MCU that >> works good enough to get you to ramstage. At this point, you can >> already apply additional MCUs from any RW partition. So what kind of >> issue would have to be fixed by an update that makes use of this >> mechanism? >> >> In other words, what problem can this new update mechanism fix, that >> current mechanisms can't? And is it worth the added complexity and >> accompanying security degradation (more code is always more error- >> prone)? > > Microcode patch contains patch for Punit as well, and that has to > be applied prior to reset. Ah, understood. Thanks for the clarification. Ofc, it's too late for current products. But is there any change planned for the FIT update mechanism. e.g. a rule that multiple updates for one processor signature are allowed and the newest would be applied. That would make this much easier, would allow a single RO FIT with some entries pointing to RO and some to the MCU RW and we wouldn't need the top-swap feature any more. > Hence the effort to load the updated microcode via FIT. This is probably the most urgent thing to mention in the commit message. Without this reasoning, it looks like you are just playing around and Intel adds complexity just because they can. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 33 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 14 Jan 2019 12:31:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Provide interface to update TCC offset
by John Su (Code Review) 14 Jan '19

14 Jan '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30803 Change subject: soc/intel/cannonlake: Provide interface to update TCC offset ...................................................................... soc/intel/cannonlake: Provide interface to update TCC offset This change provides an interface for canonlake to set TCC. With this change, we can add code to update Tcc in devicetree. BUG=b:122636962 TEST=Match the result from TAT UI Change-Id: Ib54a118e4e409919e3e60112e4621a109404b16d Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30803/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 9601863..534f87f 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -167,6 +167,26 @@ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } +static void configure_thermal_target(void) +{ + struct device *dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + msr_t msr; + + /* Set TCC activation offset if supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~0x7f; /* Bits 6:0 */ + msr.lo |= 0xe6; /* setting 100ms thermal time window */ + wrmsr(MSR_TEMPERATURE_TARGET, msr); +} + /* * The emulated ACPI timer allows replacing of the ACPI timer * (PM1_TMR) to have no impart on the system. @@ -264,4 +284,7 @@ { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_thermal_target(); } diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index ea781bc..866d9c8 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -67,6 +67,7 @@ { int i; FSP_S_CONFIG *params = &supd->FspsConfig; + FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; @@ -239,6 +240,9 @@ params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; if (config->PchPmSlpAMinAssert) params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; + + /* Set TccActivationOffset */ + tconfig->TccActivationOffset = config->tcc_offset; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib54a118e4e409919e3e60112e4621a109404b16d Gerrit-Change-Number: 30803 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/27089 ) Change subject: mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant ...................................................................... mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant This board has more or less the same as the p5qpl-am except for DDR3 memory and different colors on the ports. Tested with Arch Linux with kernel 4.20.0-arch1-1-ARCH. What is tested and works: - 800/1066/1333 MHz CPUs and DDR3 sticks at 800/1066 MHz Some bugs are still present in the DDR3 raminit code though. - Ethernet - Internal programmer with both coreboot and stock firmware. - PCI and PCIe x1 slots - All USB ports - S3 resume - SATA ports - PEG - Rear audio output Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/27089 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asus/p5qpl-am/Kconfig M src/mainboard/asus/p5qpl-am/Kconfig.name M src/mainboard/asus/p5qpl-am/Makefile.inc M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/asus/p5qpl-am/romstage.c A src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c A src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb R src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c A src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb 9 files changed, 395 insertions(+), 91 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig index ccc9094..7eee9cd 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -14,7 +14,7 @@ # GNU General Public License for more details. # -if BOARD_ASUS_P5QPL_AM +if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX config BOARD_SPECIFIC_OPTIONS def_bool y @@ -33,18 +33,34 @@ select HAVE_ACPI_RESUME select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT - select ATHEROS_ATL1E_SETMAC + + # P5G41T-M LX has ATL1C which works fine + select ATHEROS_ATL1E_SETMAC if BOARD_ASUS_P5QPL_AM config MAINBOARD_DIR string default "asus/p5qpl-am" +config VARIANT_DIR + string + default "p5qpl-am" if BOARD_ASUS_P5QPL_AM + default "p5g41t-m_lx" if BOARD_ASUS_P5G41T_M_LX + config MAINBOARD_PART_NUMBER string - default "P5QPL-AM" + default "P5QPL-AM" if BOARD_ASUS_P5QPL_AM + default "P5G41T-M LX" if BOARD_ASUS_P5G41T_M_LX + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAX_CPUS int default 4 -endif # BOARD_ASUS_P5QPL_AM +# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + +endif # BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX diff --git a/src/mainboard/asus/p5qpl-am/Kconfig.name b/src/mainboard/asus/p5qpl-am/Kconfig.name index a65174d..48ca843 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig.name +++ b/src/mainboard/asus/p5qpl-am/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASUS_P5QPL_AM bool "P5QPL-AM" + +config BOARD_ASUS_P5G41T_M_LX + bool "P5G41T-M LX" diff --git a/src/mainboard/asus/p5qpl-am/Makefile.inc b/src/mainboard/asus/p5qpl-am/Makefile.inc index 0786d6f..82e72fb 100644 --- a/src/mainboard/asus/p5qpl-am/Makefile.inc +++ b/src/mainboard/asus/p5qpl-am/Makefile.inc @@ -1,4 +1,4 @@ ramstage-y += cstates.c -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index f721f08..63ae8ce 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -24,7 +25,6 @@ end end device domain 0 on # PCI domain - subsystemid 0x1043 0x836d inherit device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 on end # Integrated graphics controller @@ -46,76 +46,26 @@ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x04000440" - device pci 1b.0 on end # Audio - device pci 1c.0 on end # PCIe 1 + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1: PCIe x1 slot device pci 1c.1 on # PCIe 2: NIC device pci 00.0 on end end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 - device pci 1d.0 on end # USB - device pci 1d.1 on end # USB - device pci 1d.2 on end # USB - device pci 1d.3 on end # USB - device pci 1d.7 on end # USB - device pci 1e.0 on end # PCI bridge + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge device pci 1e.2 off end # AC'97 Audio Controller device pci 1e.3 off end # AC'97 Modem Controller - device pci 1f.0 on # ISA bridge - chip superio/winbond/w83627dhg - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel port - # global - irq 0x2c = 0x92 - # parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off end # COM2, IR - device pnp 2e.5 on # Keyboard, mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # SPI - device pnp 2e.7 on end # GPIO6 (all input) - device pnp 2e.8 off end # WDT0#, PLED - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xf0 = 0xf3 -# irq 0xf1 = 0x08 - end - device pnp 2e.209 on # GPIO4 - irq 0xf4 = 0x00 - end - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a on # ACPI - irq 0x70 = 0 - irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 - end - device pnp 2e.b on # HWM, front pannel LED - io 0x60 = 0x290 - irq 0x70 = 0 - end - device pnp 2e.c on # PECI, SST - irq 0xe0 = 0x10 - irq 0xe1 = 0x64 - irq 0xe8 = 0x01 - end - end - end - device pci 1f.1 on end # PATA/IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMbus + device pci 1f.0 on end # ISA bridge + device pci 1f.1 on end # PATA/IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus end end end diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 13e0364b..a541533 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -51,12 +51,7 @@ return fsbcfg; } -/* - * BSEL MCH straps are not hooked up to the CPU as usual but to the SIO - * BSEL0 -> not hooked up (such configs are not supported anyways) - * BSEL1 -> GPIO33 - * BSEL2 -> GPIO40 - */ +/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */ static int setup_sio_gpio(void) { @@ -79,27 +74,55 @@ pnp_enter_ext_func_mode(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); - reg = 0x92; - old_reg = pnp_read_config(GPIO_DEV, 0x2c); - pnp_write_config(GPIO_DEV, 0x2c, reg); - need_reset = (reg != old_reg); + if (IS_ENABLED(CONFIG_BOARD_ASUS_P5QPL_AM)) { + /* + * P5QPL-AM: + * BSEL0 -> not hooked up (not supported anyways) + * BSEL1 -> GPIO33 + * BSEL2 -> GPIO40 + */ + reg = 0x92; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); - pnp_write_config(GPIO_DEV, 0x30, 0x06); - pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3 direction */ - pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ + pnp_write_config(GPIO_DEV, 0x30, 0x06); + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3 direction */ + pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ - int gpio33 = (bsel & 2) >> 1; - int gpio40 = (bsel & 4) >> 2; - reg = (gpio33 << 3); - old_reg = pnp_read_config(GPIO_DEV, 0xf1); - pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg); - need_reset += ((reg & 0x8) != (old_reg & 0x8)); + const int gpio33 = (bsel & 2) >> 1; + const int gpio40 = (bsel & 4) >> 2; + reg = (gpio33 << 3); + old_reg = pnp_read_config(GPIO_DEV, 0xf1); + pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg); + need_reset += ((reg & 0x8) != (old_reg & 0x8)); - reg = gpio40; - old_reg = pnp_read_config(GPIO_DEV, 0xf5); - pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); - need_reset += ((reg & 0x1) != (old_reg & 0x1)); + reg = gpio40; + old_reg = pnp_read_config(GPIO_DEV, 0xf5); + pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); + need_reset += ((reg & 0x1) != (old_reg & 0x1)); + } else { + /* + * P5G41T-M LX: + * BSEL0 -> not hooked up + * BSEL1 -> GPIO43 (inverted) + * BSEL2 -> GPIO44 + */ + reg = 0xf2; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + pnp_write_config(GPIO_DEV, 0x30, 0x05); + pnp_write_config(GPIO_DEV, 0xf6, 0x08); /* invert GPIO43 */ + pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ + const int gpio43 = (bsel & 2) >> 1; + const int gpio44 = (bsel & 4) >> 2; + reg = (gpio43 << 3) | (gpio44 << 4); + old_reg = pnp_read_config(GPIO_DEV, 0xf5); + pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); + need_reset += ((reg & 0x18) != (old_reg & 0x18)); + } pnp_exit_ext_func_mode(GPIO_DEV); return need_reset; diff --git a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c new file mode 100644 index 0000000..0c19135 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_HIGH, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb new file mode 100644 index 0000000..919d409 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb @@ -0,0 +1,80 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device domain 0 on # PCI domain + subsystemid 0x1043 0x8179 inherit + chip southbridge/intel/i82801gx # Southbridge + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + irq 0x2c = 0xf2 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard, mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 on # GPIO2 + irq 0xe4 = 0x04 + end + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 on # GPIO4 + irq 0xe8 = 0x80 + irq 0xf4 = 0xa4 + irq 0xf5 = 0x46 + end + device pnp 2e.309 on # GPIO5 + irq 0xfa = 0xff + irq 0xf3 = 0x09 # RSVD SUSLED settings + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # Power dram during s3 + irq 0xe6 = 0x8c + irq 0xf2 = 0x7d + end + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0x290 + irq 0x70 = 0 + irq 0xf1 = 0xff + irq 0xf2 = 0x83 + end + device pnp 2e.c on # PECI, SST + irq 0xe0 = 0x10 + irq 0xe1 = 0x64 + irq 0xe8 = 0x01 + end + end + end + end + end +end diff --git a/src/mainboard/asus/p5qpl-am/gpio.c b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c similarity index 100% rename from src/mainboard/asus/p5qpl-am/gpio.c rename to src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb new file mode 100644 index 0000000..e84fd8a --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -0,0 +1,71 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device domain 0 on # PCI domain + subsystemid 0x1043 0x836d inherit + chip southbridge/intel/i82801gx # Southbridge + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + irq 0x2c = 0x92 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard, mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xf0 = 0xf3 + end + device pnp 2e.209 on # GPIO4 + irq 0xf4 = 0x00 + end + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0x70 = 0 + irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 + end + device pnp 2e.b on # HWM, front pannel LED + io 0x60 = 0x290 + irq 0x70 = 0 + end + device pnp 2e.c on # PECI, SST + irq 0xe0 = 0x10 + irq 0xe1 = 0x64 + irq 0xe8 = 0x01 + end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 12 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Print the MTRR's FSP-T set up
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30876 Change subject: drivers/intel/fsp1_1: Print the MTRR's FSP-T set up ...................................................................... drivers/intel/fsp1_1: Print the MTRR's FSP-T set up Change-Id: I19e9038eb52922fa0c248936438f27789d00ddb5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/car.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30876/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 79dd368..3a41e40 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -64,6 +64,8 @@ printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); + display_mtrrs(); + if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || car_params->bootloader_car_end != (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19e9038eb52922fa0c248936438f27789d00ddb5 Gerrit-Change-Number: 30876 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: drivers/intel/fsp1.1: Read stack guards later
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30875 Change subject: drivers/intel/fsp1.1: Read stack guards later ...................................................................... drivers/intel/fsp1.1: Read stack guards later Read back the stack guards after most of the romstage took place. Change-Id: Ia7dc26c7ed1750d4ebbe7514ed87da57f9e34a89 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/car.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30875/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 63c5042..79dd368 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -39,6 +39,7 @@ const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base; + void *ram_stack; u32 size; /* Size of unallocated CAR. */ @@ -78,6 +79,9 @@ set_fih_car(car_params->fih); + /* Return new stack value in RAM back to assembly stub. */ + ram_stack = cache_as_ram_stage_main(car_params->fih); + /* Check the stack. */ for (i = 0; i < num_guards; i++) { if (stack_base[i] == stack_guard) @@ -85,8 +89,7 @@ printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - /* Return new stack value in RAM back to assembly stub. */ - return cache_as_ram_stage_main(car_params->fih); + return ram_stack; } /* Entry point taken when romstage is called after a separate verstage. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7dc26c7ed1750d4ebbe7514ed87da57f9e34a89 Gerrit-Change-Number: 30875 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/pineview: Select 1M TSEG
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30869 ) Change subject: nb/intel/pineview: Select 1M TSEG ...................................................................... nb/intel/pineview: Select 1M TSEG With the only valid GTT setting being 1M, TSEG_BASE can only be aligned to TSEG_SIZE if it is also 1M. This alignment requirement comes from the desire to use SMRR to protect the SMM RAM. Tested on Foxconn D41S. Change-Id: Ibd879529923a1676f2e78500797a52d8a37b8eef Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30869 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 3413cc1..ee19b61 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -2032,9 +2032,9 @@ gttsize = ggc_to_gtt[(ggc & 0x300) >> 8]; tom = s->channel_capacity[0]; - /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, - which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - tsegsize = 0x2; + /* with GTT always being 1M, TSEG 1M is the only setting that can + be covered by SMRR which has alignment requirements. */ + tsegsize = 0x1; mmiosize = 0x400; // 1GB reclaim = false; @@ -2071,7 +2071,7 @@ u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); reg8 &= ~0x7; - reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ + reg8 |= (0 << 1) | (1 << 0); /* 1M and TSEG_Enable */ pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/30869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd879529923a1676f2e78500797a52d8a37b8eef Gerrit-Change-Number: 30869 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: cpu/intel/gen1/smmrelocate: Check for sanity on SMRR
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30709 Change subject: cpu/intel/gen1/smmrelocate: Check for sanity on SMRR ...................................................................... cpu/intel/gen1/smmrelocate: Check for sanity on SMRR This happens when TSEG is found to be unaligned. Change-Id: Id0c078a880dddb55857af2bca233cf4dee91250a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30709/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 426eae5..46f6f93 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -60,6 +60,9 @@ { struct cpuinfo_x86 c; + if (relo_params->smrr_base.lo == 0) + return; + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); /* Both model_6fx and model_1067x SMRR function slightly differently -- To view, visit https://review.coreboot.org/c/coreboot/+/30709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0c078a880dddb55857af2bca233cf4dee91250a Gerrit-Change-Number: 30709 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/car/non-evict: Update microcode in CAR setup
by Kyösti Mälkki (Code Review) 14 Jan '19

14 Jan '19

Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30813 to review the following change. Change subject: cpu/intel/car/non-evict: Update microcode in CAR setup ...................................................................... cpu/intel/car/non-evict: Update microcode in CAR setup On CPU's with a non eviction mode we cache the whole ROM to speed up finding the microcode updates, remove the caching to fill in the non eviction mode and then turn on caching the whole ROM again to speed executing XIP code in flash. Change-Id: Ib7f36678913e0ba8ef1305bca2c482f375b23eaf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 36 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30813/1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 4ac6d29..d2beaa7 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -114,6 +114,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25) /* Enable MTRR. */ @@ -128,6 +139,30 @@ invd movl %eax, %cr0 +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif + /* Disable caching to change MTRR's. */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + /* Clear the mask valid to disable the MTRR */ + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + andl $(~MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + /* enable the 'no eviction' mode */ movl $NoEvictMod_MSR, %ecx rdmsr @@ -154,15 +189,9 @@ orl $CR0_CacheDisable, %eax movl %eax, %cr0 - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + orl $MTRR_PHYS_MASK_VALID, %eax wrmsr post_code(0x28) -- To view, visit https://review.coreboot.org/c/coreboot/+/30813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f36678913e0ba8ef1305bca2c482f375b23eaf Gerrit-Change-Number: 30813 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019