coreboot-gerrit January 2019

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Nico Huber (Code Review) 14 Jan '19

14 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 35: >> Ofc, it's too late for current products. But is there any change >> planned for the FIT update mechanism. e.g. a rule that multiple >> updates for one processor signature are allowed and the newest would >> be applied. That would make this much easier, would allow a single >> RO FIT with some entries pointing to RO and some to the MCU RW and >> we wouldn't need the top-swap feature any more. >> > If you haven't tried, add multiple microcode patches in FIT for the same processor > signature, you will find that FIT will pick the latest revision and load. However > there is no fallback if there is a failure. > Hmm, that's not allowed by the Coffee Lake BWG. > 2 FITs, 1 for normal boot, another for recovery boot. > Even if the CPU manages to load the latest revision (from the > normal boot FIT) and that results in a hang/reboot loop. We need a > tried and tested patch to recover from the hang/reboot for which > the top-swap FIT will be used. That's just relaying the problem of dependable firmware from MCU to coreboot. If things are really that bad that you expect Intel to sign an MCU that results in a boot failure, you shift the problem to this update mechanism here. How can you be sure that no OEM will acciden- tally ship devices with a broken update mechanism in RO? If it's broken, you need a way to recover; a fallback fallback? I understand why you are doing this. I just don't see that it's a good solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 35 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 14 Jan 2019 15:52:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29973 ) Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 5: (39 comments) https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py File util/qualcomm/createxbl.py: https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@25 PS5, Line 25: # 09/04/15 et Added -x and -d to embed xbl_sec ELF trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@68 PS5, Line 68: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@84 PS5, Line 84: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@103 PS5, Line 103: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@113 PS5, Line 113: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@121 PS5, Line 121: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@144 PS5, Line 144: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@164 PS5, Line 164: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@172 PS5, Line 172: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@192 PS5, Line 192: header_format = 'reg' trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@223 PS5, Line 223: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@231 PS5, Line 231: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@232 PS5, Line 232: # Create hash table trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@235 PS5, Line 235: target_hash, trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@237 PS5, Line 237: secure_type = image_header_secflag) trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@245 PS5, Line 245: target_hash_hd, trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@254 PS5, Line 254: # Add the hash segment into the ELF trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@272 PS5, Line 272: def merge_elfs(env, trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@284 PS5, Line 284: mbn_tools.preprocess_elf_file(elf_in_file_name1) trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@289 PS5, Line 289: mbn_tools.preprocess_elf_file(elf_in_file_name2) trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@290 PS5, Line 290: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@294 PS5, Line 294: mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@325 PS5, Line 325: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@364 PS5, Line 364: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@400 PS5, Line 400: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@477 PS5, Line 477: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@512 PS5, Line 512: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@614 PS5, Line 614: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@618 PS5, Line 618: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@621 PS5, Line 621: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@640 PS5, Line 640: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@674 PS5, Line 674: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@675 PS5, Line 675: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@681 PS5, Line 681: inp_data_offset = 0 trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@682 PS5, Line 682: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@689 PS5, Line 689: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@706 PS5, Line 706: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/createxbl.py@708 PS5, Line 708: trailing whitespace https://review.coreboot.org/#/c/29973/5/util/qualcomm/mbn_tools.py File util/qualcomm/mbn_tools.py: https://review.coreboot.org/#/c/29973/5/util/qualcomm/mbn_tools.py@1167 PS5, Line 1167: # Check if a shifting is required to accomodate for the hash segment. 'accomodate' may be misspelled - perhaps 'accommodate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 5 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:50:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 5: (95 comments) https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/clock.c@206 PS5, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/clock.c@206 PS5, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/clock.c@207 PS5, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/clock.c@207 PS5, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/clock.c@208 PS5, Line 208: BLSP2_AHB_CLK_ENA); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/clock.c@208 PS5, Line 208: BLSP2_AHB_CLK_ENA); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/qup.h: https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 161: unsigned clk_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 162: unsigned src_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 164: unsigned initialized; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 173: unsigned data_len; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 178: unsigned size; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@63 PS5, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@63 PS5, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@63 PS5, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@64 PS5, Line 64: /* BLSP5 registers for SPI interface */ code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@65 PS5, Line 65: { code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@65 PS5, Line 65: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@66 PS5, Line 66: BLSP5_SPI_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@66 PS5, Line 66: BLSP5_SPI_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@67 PS5, Line 67: BLSP5_SPI_IO_CONTROL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@67 PS5, Line 67: BLSP5_SPI_IO_CONTROL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@68 PS5, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@68 PS5, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@69 PS5, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@69 PS5, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@70 PS5, Line 70: BLSP5_QUP_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@70 PS5, Line 70: BLSP5_QUP_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@71 PS5, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@71 PS5, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@72 PS5, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@72 PS5, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@73 PS5, Line 73: BLSP5_QUP_OPERATIONAL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@73 PS5, Line 73: BLSP5_QUP_OPERATIONAL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@74 PS5, Line 74: BLSP5_QUP_IO_MODES_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@74 PS5, Line 74: BLSP5_QUP_IO_MODES_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@75 PS5, Line 75: BLSP5_QUP_STATE_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@75 PS5, Line 75: BLSP5_QUP_STATE_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@76 PS5, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@76 PS5, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@77 PS5, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@77 PS5, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@78 PS5, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@78 PS5, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@79 PS5, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@79 PS5, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@80 PS5, Line 80: BLSP5_QUP_SW_RESET_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@80 PS5, Line 80: BLSP5_QUP_SW_RESET_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@81 PS5, Line 81: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@81 PS5, Line 81: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@82 PS5, Line 82: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@82 PS5, Line 82: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@83 PS5, Line 83: BLSP5_QUP_OPERATIONAL_MASK, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@83 PS5, Line 83: BLSP5_QUP_OPERATIONAL_MASK, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@84 PS5, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@84 PS5, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@85 PS5, Line 85: }, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@85 PS5, Line 85: }, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@273 PS5, Line 273: SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); line over 80 characters https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@310 PS5, Line 310: switch(slave->bus) { switch and case should be at the same indent https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@310 PS5, Line 310: switch(slave->bus) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@311 PS5, Line 311: case 5: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@311 PS5, Line 311: case 5: please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@313 PS5, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@313 PS5, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@313 PS5, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@314 PS5, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@314 PS5, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@314 PS5, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@315 PS5, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@315 PS5, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@315 PS5, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@316 PS5, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@316 PS5, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@316 PS5, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@318 PS5, Line 318: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@318 PS5, Line 318: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@319 PS5, Line 319: default: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@320 PS5, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); line over 80 characters https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@320 PS5, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@320 PS5, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@321 PS5, Line 321: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@321 PS5, Line 321: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@322 PS5, Line 322: } code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@322 PS5, Line 322: } please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@354 PS5, Line 354: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@428 PS5, Line 428: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@684 PS5, Line 684: "or chipselect\n", bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@684 PS5, Line 684: "or chipselect\n", bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@713 PS5, Line 713: static int xfer_vectors(const struct spi_slave *slave, open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@714 PS5, Line 714: struct spi_op vectors[], size_t count) code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@714 PS5, Line 714: struct spi_op vectors[], size_t count) please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@715 PS5, Line 715: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@716 PS5, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@716 PS5, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/5/src/soc/qualcomm/qcs405/spi.c@717 PS5, Line 717: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 5 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:50:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Patch Set 5: (4 comments) https://review.coreboot.org/#/c/29966/5/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/5/src/soc/qualcomm/qcs405/usb.c@137 PS5, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/5/src/soc/qualcomm/qcs405/usb.c@138 PS5, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/5/src/soc/qualcomm/qcs405/usb.c@139 PS5, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/5/src/soc/qualcomm/qcs405/usb.c@140 PS5, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 5 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:50:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: lib/boot_device: Add API for write protect a region
by Rizwan Qureshi (Code Review) 14 Jan '19

14 Jan '19

Hello Patrick Rudolph, Aaron Durbin, Subrata Banik, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28724 to look at the new patch set (#16). Change subject: lib/boot_device: Add API for write protect a region ...................................................................... lib/boot_device: Add API for write protect a region Add API that should be implemented by the boot media drivers for write-protecting a subregion. Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/drivers/spi/boot_device_rw_nommap.c M src/include/boot_device.h M src/lib/boot_device.c 3 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28724/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 16 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Add blsp uart driver
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add blsp uart driver ...................................................................... Patch Set 5: (25 comments) https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/cdp.h: https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 36: unsigned smem_get_board_machtype(void); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 89: SPI_CS_0 , space prohibited before that ',' (ctx:WxE) https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 119: unsigned count; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 124: unsigned base; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 126: unsigned is_macsec; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 127: unsigned mac_pwr0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 128: unsigned mac_pwr1; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 129: unsigned mac_conn_to_phy; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 172: unsigned int get_board_index(unsigned machid); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 173: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/iomap.h: https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/include/soc… PS5, Line 49: #define writel_i(v,a) write32((void *)a, v) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c File src/soc/qualcomm/qcs405/uart.c: https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@50 PS5, Line 50: unsigned blsp_uart; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@54 PS5, Line 54: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@56 PS5, Line 56: int i; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@56 PS5, Line 56: int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@58 PS5, Line 58: for (i = 0; i < count; i++) { code indent should use tabs where possible https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@58 PS5, Line 58: for (i = 0; i < count; i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@59 PS5, Line 59: gpio_configure(gpio->gpio, gpio->func, code indent should use tabs where possible https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@59 PS5, Line 59: gpio_configure(gpio->gpio, gpio->func, please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@60 PS5, Line 60: gpio->pull, gpio->drvstr, gpio->enable); code indent should use tabs where possible https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@60 PS5, Line 60: gpio->pull, gpio->drvstr, gpio->enable); please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@61 PS5, Line 61: gpio++; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@61 PS5, Line 61: gpio++; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@62 PS5, Line 62: } code indent should use tabs where possible https://review.coreboot.org/#/c/29964/5/src/soc/qualcomm/qcs405/uart.c@62 PS5, Line 62: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 5 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:49:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29959 ) Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... Patch Set 5: (6 comments) https://review.coreboot.org/#/c/29959/5/src/soc/qualcomm/qcs405/flash_contr… File src/soc/qualcomm/qcs405/flash_controller.c: https://review.coreboot.org/#/c/29959/5/src/soc/qualcomm/qcs405/flash_contr… PS5, Line 37: static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) line over 80 characters https://review.coreboot.org/#/c/29959/5/src/soc/qualcomm/qcs405/flash_contr… PS5, Line 68: { that open brace { should be on the previous line https://review.coreboot.org/#/c/29959/5/src/soc/qualcomm/qcs405/flash_contr… PS5, Line 78: static char name[] = "ram_flash"; static char array declaration should probably be static const char https://review.coreboot.org/#/c/29959/5/src/soc/qualcomm/qcs405/flash_contr… PS5, Line 80: printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/5/src/soc/qualcomm/qcs405/flash_contr… PS5, Line 82: printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/5/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29959/5/src/soc/qualcomm/qcs405/mmu.c@40 PS5, Line 40: mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 5 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:49:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/google/mistral: Add support for Mistral
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has uploaded a new patch set (#5) to the change originally created by nsekar(a)codeaurora.org. ( https://review.coreboot.org/c/coreboot/+/29949 ) Change subject: mainboard/google/mistral: Add support for Mistral ...................................................................... mainboard/google/mistral: Add support for Mistral Adding a new board variant 'Mistral' based on qcs405 soc. TEST=build Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A src/mainboard/google/mistral/Kconfig A src/mainboard/google/mistral/Kconfig.name A src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/board_info.txt A src/mainboard/google/mistral/bootblock.c A src/mainboard/google/mistral/chromeos.c A src/mainboard/google/mistral/chromeos.fmd A src/mainboard/google/mistral/devicetree.cb A src/mainboard/google/mistral/mainboard.c A src/mainboard/google/mistral/memlayout.ld A src/mainboard/google/mistral/romstage.c 11 files changed, 256 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29949/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Gerrit-Change-Number: 29949 Gerrit-PatchSet: 5 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has uploaded a new patch set (#5) to the change originally created by nsekar(a)codeaurora.org. ( https://review.coreboot.org/c/coreboot/+/29948 ) Change subject: soc/qualcomm/qcs405: Support for new SoC ...................................................................... soc/qualcomm/qcs405: Support for new SoC Adding the basic infrastruture soc support for qcs405 and a new build variant. TEST=build Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A src/soc/qualcomm/qcs405/Kconfig A src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/cbmem.c A src/soc/qualcomm/qcs405/include/soc/gpio.h A src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/soc.c A src/soc/qualcomm/qcs405/spi.c A src/soc/qualcomm/qcs405/timer.c 9 files changed, 288 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29948/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Gerrit-Change-Number: 29948 Gerrit-PatchSet: 5 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405 [temp]: HACK HACK for commit id for VBOOT project
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29974 ) Change subject: qcs405 [temp]: HACK HACK for commit id for VBOOT project ...................................................................... Patch Set 4: We can drop this commit once https://review.coreboot.org/c/coreboot/+/30914 landed. It updates vboot to something newer than this commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/29974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd040619eb996164e50705fcf16547571e99f99 Gerrit-Change-Number: 29974 Gerrit-PatchSet: 4 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Jan 2019 15:42:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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