coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: [RFC]util/checklist: Remove this functionality
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30691 Change subject: [RFC]util/checklist: Remove this functionality ...................................................................... [RFC]util/checklist: Remove this functionality It was only hooked up for galileo board when using the obsolete FSP1.1. I don't see how it can be useful... Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D Documentation/Intel/Board/Galileo_checklist.html M Documentation/Intel/Board/galileo.html M src/Kconfig M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp2_0/Kconfig M src/mainboard/intel/galileo/Kconfig D src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat D src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat D src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat D src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat D src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat D src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat D src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat D src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat D util/checklist/Makefile.inc D util/checklist/description.md 16 files changed, 0 insertions(+), 757 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/30691/1 diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html deleted file mode 100644 index 397f570..0000000 --- a/Documentation/Intel/Board/Galileo_checklist.html +++ /dev/null @@ -1,160 +0,0 @@ -<html> -<head> -<title>Galileo Implementation Status</title> -</title> -<body> -<h1>Galileo Implementation Status<br>2016/07/08 06:51:34 PDT</h1> -<table> - <tr><td colspan=2><b>Legend</b></td></tr> - <tr><td bgcolor="#ffc0c0">Red</td><td>Required - To-be-implemented</td></tr> - <tr><td bgcolor="#ffffc0">Yellow</td><td>Optional</td></tr> - <tr><td bgcolor="#c0ffc0">Green</td><td>Implemented</td></tr> -</table> -<table> - <tr valign="top"> - <td> -<table border=1> -<tr><th colspan=2>bootblock: 100% Done</th></tr> -<tr><th>Type</th><th>Routine</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_c_entry</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_main_with_timestamp</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_mainboard_early_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_mainboard_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_pre_c_entry</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_protected_mode_entry</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_soc_early_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_soc_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>uart_init</td></tr> -</table> - </td> - <td width=5> </td> - <td> -<table border=1> -<tr><th colspan=2>romstage: 67% Done</th></tr> -<tr><th>Type</th><th>Routine</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>car_mainboard_post_console_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>car_mainboard_pre_console_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_post_console_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_pre_console_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>car_stage_entry</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>fill_power_state</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_check_ec_image</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_fill_spd_data</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_memory_init_params</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>mainboard_romstage_entry</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_save_dimm_info</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>migrate_power_state</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_get_current_with_version</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_stash_data_with_version</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>print_fsp_info</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>raminit</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>ramstage_cache_invalid</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>report_memory_config</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>romstage_common</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>set_max_freq</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>setup_stack_and_mtrrs</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>timestamp_get</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vboot_platform_prepare_reboot</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>verstage_mainboard_init</td></tr> -</table> - </td> - <td width=5> </td> - <td> -<table border=1> -<tr><th colspan=2>ramstage: 60% Done</th></tr> -<tr><th>Type</th><th>Routine</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>acpi_create_serialio_ssdt</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>fw_cfg_acpi_tables</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>lb_board</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>lb_framebuffer</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_silicon_init_params</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_suspend_resume</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mirror_payload</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>northbridge_smi_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>nvm_mmio_to_flash_offset</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_bios_version</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_manufacturer</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_product_name</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_serial_number</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_set_uuid</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_silicon_init_params</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>soc_fill_acpi_wake</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_silicon_init_params</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_skip_ucode_update</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_get</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_tick_freq_mhz</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>wifi_regulatory_domain</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>write_smp_table</td></tr> -</table> - </td> - <td width=5> </td> - </tr> -</table> -</body> -</html> diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index cd0a28a..f7edf6e 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -17,7 +17,6 @@ <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> <li><a target="_blank" href="board.html">Board</a> support</li> - <li><a target="_blank" href="Galileo_checklist.html">Implementation Checklist</a></li> </ul> </td> </tr> diff --git a/src/Kconfig b/src/Kconfig index 87b088f..1c9b504 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1089,36 +1089,6 @@ with the normal image enabled before assuming the normal image is defective and switching to the fallback image. -config CREATE_BOARD_CHECKLIST - bool - default n - help - When selected, creates a webpage showing the implementation status for - the board. Routines highlighted in green are complete, yellow are - optional and red are required and must be implemented. A table is - produced for each stage of the boot process except the bootblock. The - red items may be used as an implementation checklist for the board. - -config MAKE_CHECKLIST_PUBLIC - bool - default n - help - When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html - is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board - directory. - -config CHECKLIST_DATA_FILE_LOCATION - string - help - Location of the <stage>_complete.dat and <stage>_optional.dat files - that are consumed during checklist processing. <stage>_complete.dat - contains the symbols that are expected to be in the resulting image. - <stage>_optional.dat is a subset of <stage>_complete.dat and contains - a list of weak symbols which the resulting image may consume. Other - symbols contained only in <stage>_complete.dat will be flagged as - required and not implemented if a weak implementation is found in the - resulting image. - config UNCOMPRESSED_RAMSTAGE bool diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index af6ed42..2575577 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -86,10 +86,6 @@ The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms. -config CHECKLIST_DATA_FILE_LOCATION - string - default "src/vendorcode/intel/fsp/fsp1_1/checklist" - config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 28e9e5d..8156d18 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -146,10 +146,6 @@ Verify that the HOBs required by coreboot are returned by FSP and that the resource HOBs are in the correct order and position. -config CHECKLIST_DATA_FILE_LOCATION - string - default "src/vendorcode/intel/fsp/fsp2_0/checklist" - config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 87f82bc..8af4989 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 -# select CREATE_BOARD_CHECKLIST select ENABLE_BUILTIN_HSUART1 select HAVE_ACPI_TABLES select SOC_INTEL_QUARK @@ -52,7 +51,6 @@ config FSP_VERSION_1_1 bool "FSP 1.1" - select CREATE_BOARD_CHECKLIST select PLATFORM_USES_FSP1_1 # select ADD_FSP_RAW_BIN help diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat deleted file mode 100644 index 4055a3c..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat +++ /dev/null @@ -1,10 +0,0 @@ -bootblock_c_entry -bootblock_mainboard_early_init -bootblock_mainboard_init -bootblock_main_with_timestamp -bootblock_pre_c_entry -bootblock_protected_mode_entry -bootblock_soc_early_init -bootblock_soc_init -tsc_freq_mhz -uart_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat deleted file mode 100644 index fc0e872..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat +++ /dev/null @@ -1,6 +0,0 @@ -bootblock_c_entry -bootblock_mainboard_early_init -bootblock_mainboard_init -bootblock_soc_early_init -bootblock_soc_init -uart_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat deleted file mode 100644 index 64f8584..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat +++ /dev/null @@ -1,53 +0,0 @@ -acpi_create_serialio_ssdt -arch_segment_loaded -backup_top_of_ram -boot_device_init -cbfs_master_header_locator -cbmem_fail_resume -clear_recovery_mode_switch -cpu_smi_handler -fw_cfg_acpi_tables -get_sw_write_protect_state -get_top_of_ram -gpio_acpi_path -init_timer -lb_board -lb_framebuffer -mainboard_add_dimm_info -mainboard_io_trap_handler -mainboard_post -mainboard_silicon_init_params -mainboard_smi_apmc -mainboard_smi_gpi -mainboard_smi_sleep -mainboard_suspend_resume -map_oprom_vendev -mirror_payload -northbridge_smi_handler -nvm_mmio_to_flash_offset -platform_prog_run -platform_segment_loaded -save_chromeos_gpios -smbios_mainboard_bios_version -smbios_mainboard_manufacturer -smbios_mainboard_product_name -smbios_mainboard_serial_number -smbios_mainboard_set_uuid -smbios_mainboard_version -smm_disable_busmaster -soc_after_silicon_init -soc_display_silicon_init_params -soc_fill_acpi_wake -soc_silicon_init_params -soc_skip_ucode_update -southbridge_smi_handler -stage_cache_add -stage_cache_load_stage -timestamp_get -timestamp_tick_freq_mhz -tsc_freq_mhz -vb2ex_hwcrypto_digest_extend -vb2ex_hwcrypto_digest_finalize -vb2ex_hwcrypto_digest_init -wifi_regulatory_domain -write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat deleted file mode 100644 index 6608583..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat +++ /dev/null @@ -1,46 +0,0 @@ -arch_segment_loaded -backup_top_of_ram -boot_device_init -cbmem_fail_resume -clear_recovery_mode_switch -cpu_smi_handler -fw_cfg_acpi_tables -get_sw_write_protect_state -get_top_of_ram -gpio_acpi_path -lb_board -lb_framebuffer -mainboard_add_dimm_info -mainboard_io_trap_handler -mainboard_post -mainboard_silicon_init_params -mainboard_smi_apmc -mainboard_smi_gpi -mainboard_smi_sleep -mainboard_suspend_resume -map_oprom_vendev -mirror_payload -northbridge_smi_handler -nvm_mmio_to_flash_offset -platform_prog_run -platform_segment_loaded -save_chromeos_gpios -smbios_mainboard_bios_version -smbios_mainboard_manufacturer -smbios_mainboard_product_name -smbios_mainboard_serial_number -smbios_mainboard_set_uuid -smbios_mainboard_version -smm_disable_busmaster -soc_after_silicon_init -soc_display_silicon_init_params -soc_silicon_init_params -soc_skip_ucode_update -southbridge_smi_handler -stage_cache_add -stage_cache_load_stage -vb2ex_hwcrypto_digest_extend -vb2ex_hwcrypto_digest_finalize -vb2ex_hwcrypto_digest_init -wifi_regulatory_domain -write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat deleted file mode 100644 index 3417212..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat +++ /dev/null @@ -1,53 +0,0 @@ -arch_segment_loaded -backup_top_of_ram -boot_device_init -car_stage_entry -cbfs_master_header_locator -cbmem_fail_resume -clear_recovery_mode_switch -cpu_smi_handler -fill_power_state -get_sw_write_protect_state -get_top_of_ram -gpio_acpi_path -init_timer -mainboard_add_dimm_info -mainboard_check_ec_image -mainboard_fill_spd_data -mainboard_io_trap_handler -mainboard_memory_init_params -mainboard_post -mainboard_romstage_entry -mainboard_save_dimm_info -mainboard_smi_apmc -mainboard_smi_gpi -mainboard_smi_sleep -map_oprom_vendev -migrate_power_state -mrc_cache_get_current_with_version -mrc_cache_stash_data_with_version -platform_prog_run -platform_segment_loaded -print_fsp_info -raminit -ramstage_cache_invalid -report_memory_config -romstage_common -save_chromeos_gpios -set_max_freq -setup_stack_and_mtrrs -smm_region -smm_region_size -soc_after_ram_init -soc_display_memory_init_params -soc_memory_init_params -soc_pre_ram_init -southbridge_smi_handler -stage_cache_add -stage_cache_load_stage -timestamp_get -tsc_freq_mhz -vb2ex_hwcrypto_digest_extend -vb2ex_hwcrypto_digest_finalize -vb2ex_hwcrypto_digest_init -vboot_platform_prepare_reboot diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat deleted file mode 100644 index 0835190..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat +++ /dev/null @@ -1,33 +0,0 @@ -arch_segment_loaded -backup_top_of_ram -boot_device_init -car_stage_entry -cbmem_fail_resume -clear_recovery_mode_switch -cpu_smi_handler -get_sw_write_protect_state -get_top_of_ram -gpio_acpi_path -mainboard_add_dimm_info -mainboard_check_ec_image -mainboard_io_trap_handler -mainboard_post -mainboard_romstage_entry -mainboard_save_dimm_info -mainboard_smi_apmc -mainboard_smi_gpi -mainboard_smi_sleep -map_oprom_vendev -platform_prog_run -platform_segment_loaded -save_chromeos_gpios -soc_after_ram_init -soc_display_memory_init_params -soc_memory_init_params -soc_pre_ram_init -southbridge_smi_handler -stage_cache_add -stage_cache_load_stage -vb2ex_hwcrypto_digest_extend -vb2ex_hwcrypto_digest_finalize -vb2ex_hwcrypto_digest_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat deleted file mode 100644 index 0910152..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat +++ /dev/null @@ -1,33 +0,0 @@ -arch_segment_loaded -backup_top_of_ram -boot_device_init -car_mainboard_post_console_init -car_mainboard_pre_console_init -car_soc_post_console_init -car_soc_pre_console_init -cbfs_master_header_locator -cbmem_fail_resume -clear_recovery_mode_switch -cpu_smi_handler -get_sw_write_protect_state -gpio_acpi_path -init_timer -mainboard_check_ec_image -mainboard_io_trap_handler -mainboard_post -mainboard_smi_apmc -mainboard_smi_gpi -mainboard_smi_sleep -map_oprom_vendev -platform_prog_run -platform_segment_loaded -save_chromeos_gpios -stage_cache_add -stage_cache_load_stage -timestamp_get -tsc_freq_mhz -vb2ex_hwcrypto_digest_extend -vb2ex_hwcrypto_digest_finalize -vb2ex_hwcrypto_digest_init -vboot_platform_prepare_reboot -verstage_mainboard_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat deleted file mode 100644 index fe1f0d9..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat +++ /dev/null @@ -1,20 +0,0 @@ -arch_segment_loaded -backup_top_of_ram -boot_device_init -car_mainboard_post_console_init -car_mainboard_pre_console_init -car_soc_post_console_init -car_soc_pre_console_init -mainboard_check_ec_image -mainboard_post -platform_prog_run -platform_segment_loaded -stage_cache_add -stage_cache_load_stage -timestamp_get -tsc_freq_mhz -vb2ex_hwcrypto_digest_extend -vb2ex_hwcrypto_digest_finalize -vb2ex_hwcrypto_digest_init -vboot_platform_prepare_reboot -verstage_mainboard_init diff --git a/util/checklist/Makefile.inc b/util/checklist/Makefile.inc deleted file mode 100644 index 362498e..0000000 --- a/util/checklist/Makefile.inc +++ /dev/null @@ -1,301 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2016 Intel Corporation. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -########################################################################### -# Instructions -########################################################################### -# -# Create new control files for checklist: -# -# 1. Remove any selection for CREATE_BOARD_CHECKLIST -# 2. Remove any selection for MAKE_CHECKLIST_PUBLIC -# 3. make -# 4. nm build/cbfs/fallback/<stage>.debug > <stage>_symbols.txt -# 6. sed 's/^...........//' <stage>_symbols.txt > <stage>_complete.dat -# 7. grep -F " W " <stage>_symbols.txt | sed 's/^...........//' \ -# > <stage>_optional.dat -# 8. Edit <stage>_complete.dat to remove any symbols that are not -# desired in the report -# 9. Edit <stage>_optional.dat to remove any symbols that are -# required to be implemented -# -# Create a board checklist: -# -# 1. select CREATE_BOARD_CHECKLIST -# 2. Optionally: select MAKE_CHECKLIST_PUBLIC -# 3. Specify CONFIG_CHECKLIST_DATA_FILE_LOCATION -# 4. make -# -# Build Errors: -# * No checklist built - verify CREATE_BOARD_CHECKLIST is selected in -# board Kconfig file. Do a make clean -# * <stage>_complete.dat not found - verify that -# CONFIG_CHECKLIST_DATA_FILE_LOCATION points to the directory -# containing the checklist data files. Build the checklist -# data files if necessary. -# * Segmentation fault - most likely caused by $(NM_$(class)) not being -# set. -# -########################################################################### -# Build the board implementation checklist -########################################################################### - -# Only build the checklist for boards under development -ifeq ($(CONFIG_CREATE_BOARD_CHECKLIST),y) - -# -# Extract the symbol table from the image -# -%.symbol_table: %.elf %.debug - $(NM_$(class)) $(*D)/$(*F).debug > $@ - $(NM_$(class)) $< >> $@ - -# -# All symbols in the image -# -# 1. Remove the address and symbol type -# 2. Sort the table into alphabetical order -# 3. Remove any duplicates -# -%.symbols: %.symbol_table - sed 's/^...........//' $< > $@.tmp - sort $@.tmp > $@.tmp2 - uniq $@.tmp2 > $@ - rm $@.tmp $@.tmp2 - -# -# Weak symbols in the image -# -# 1. Find the weak symbols -# 2. Remove the address and symbol type -# 3. Sort the table into alphabetical order -# 4. Remove any duplicates -# -%.weak: %.symbol_table - grep -F " W " $< | sed 's/^...........//' > $@.tmp - sort $@.tmp > $@.tmp2 - uniq $@.tmp2 > $@ - rm $@.tmp $@.tmp2 - -# -# Expected symbols in the image -# -# 1. Get the complete list of expected symbols in the image -# 2. Sort the table into alphabetical order -# 3. Remove any duplicates -# -%.expected: %.symbol_table - cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_complete.dat $@.tmp - cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat >> $@.tmp - # If no separate verstage, combine verstage and romstage routines into a single list - if [ "$(*F)" = "romstage" ]; then \ - if [ ! -e $(*D)/verstage.elf ]; then \ - if [ ! -e $(*D)/postcar.elf ]; then \ - cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_complete.dat >> $@.tmp; \ - cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_optional.dat >> $@.tmp; \ - fi; \ - fi; \ - fi - sort $@.tmp > $@.tmp2 - uniq $@.tmp2 > $@ - rm $@.tmp $@.tmp2 - -# -# Optional symbols in the image -# -# 1. Get the list of optional symbols in the image -# 2. Sort the table into alphabetical order -# 3. Remove any duplicates -# -%.optional: %.symbol_table - cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat $@.tmp - # If no separate verstage, combine verstage and romstage routines into a single list - if [ "$(*F)" = "romstage" ]; then \ - if [ ! -e $(*D)/verstage.elf ]; then \ - if [ ! -e $(*D)/postcar.elf ]; then \ - cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_optional.dat >> $@.tmp; \ - fi; \ - fi; \ - fi - sort $@.tmp > $@.tmp2 - uniq $@.tmp2 > $@ - rm $@.tmp $@.tmp2 - -# -# Expected Symbols Optional Weak Done Type -# no yes no d/c yes Don't display -# yes no no no no Required - not implemented -# yes no yes no no Optional - not implemented -# yes yes yes yes no Optional - not implemented -# yes yes no no yes Required - implemented -# yes yes yes no yes Required - implemented -# -# Implemented routines are in the symbol table and are not weak -# -# 1. Remove expected symbols which are not in the image (not implemented yet) -# 2. Remove weak symbols from the list (not implemented yet) -# -%.done: %.symbols %.expected %.weak %.optional - comm -12 $(*D)/$(*F).expected $(*D)/$(*F).symbols | sed "s/^[ \t]*//" > $@.tmp - comm -23 $@.tmp $(*D)/$(*F).weak | sed "s/^[ \t]*//" > $@ - rm $@.tmp - -# -# Remove any routines that are implemented -# -%.optional2: %.optional %.done - comm -23 $^ | sed "s/^[ \t]*//" > $@ - -# -# Remove any implemented or optional routines -# -%.tbd: %.expected %.done %.optional2 - comm -23 $(*D)/$(*F).expected $(*D)/$(*F).done | sed "s/^[ \t]*//" > $@.tmp - comm -23 $@.tmp $(*D)/$(*F).optional2 | sed "s/^[ \t]*//" > $@ - rm $@.tmp - -# -# Build the implementation table for each stage -# 1. Color code the rows -# * Done table rows are in green -# * Optional table rows are in yellow -# * TBD table rows are in red -# 2. Add the row termination -# 3. Sort the rows into alphabetical order -# -%.table_rows: %.optional2 %.done %.expected %.tbd - sed -e 's/^/<tr bgcolor=#c0ffc0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).done > $@.tmp - sed -e 's/^/<tr bgcolor=#ffffc0><td>Optional<\/td><td>/' $(*D)/$(basename $(*F)).optional2 >> $@.tmp - if [ -s $(*D)/$(basename $(*F)).tbd ]; then \ - sed -e 's/^/<tr bgcolor=#ffc0c0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).tbd >> $@.tmp; \ - fi - sed -e 's/$$/<\/td><\/tr>/' -i $@.tmp - sort -t ">" -k4 $@.tmp > $@ - rm $@.tmp - -# -# Count the lines in the done file -# -done_lines = $$(wc -l $(*D)/$(basename $(*F)).done | sed 's/ .*//') - -# -# Count the lines in the optional file -# -optional_lines = $$(wc -l $(*D)/$(basename $(*F)).optional2 | sed 's/ .*//') - -# -# Count the lines in the expected file -# -expected_lines = $$(wc -l $(*D)/$(basename $(*F)).expected | sed 's/ .*//') - -# Compute the percentage done by routine count -percent_complete = $$(($(done_lines) * 100 / ($(expected_lines) - $(optional_lines)))) - -# -# Build the table -# 1. Add the table header -# 2. Add the table rows -# 3. Add the table trailer -# -%.html: %.table_rows - echo "<table border=1>" > $@ - echo "<tr><th colspan=2>$(basename $(*F)): $(percent_complete)% Done</th></tr>" >> $@ - echo "<tr><th>Type</th><th>Routine</td></tr>" >> $@ - cat $< >> $@ - echo "</table>" >> $@ - -# -# Determine which HTML files to include into the webpage -# -ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) -html_table_files += $(objcbfs)/bootblock.html -endif -ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) -html_table_files += $(objcbfs)/verstage.html -endif -html_table_files += $(objcbfs)/romstage.html -ifeq ($(CONFIG_POSTCAR_STAGE),y) -html_table_files += $(objcbfs)/postcar.html -endif -html_table_files += $(objcbfs)/ramstage.html - -# -# Create a list with each file on a separate line -# -list_of_html_files = $(subst _NEWLINE_,${\n},${html_table_files}) - -# -# Get the date for the webpage -# -current_date_time = $$(date +"%Y/%m/%d %T %Z") - -# -# Build the webpage from the implementation tables -# 1. Add the header to the webpage -# 2. Add the legend to the webpage -# 3. Use a table to place stage tables side-by-side -# 4. Add the stage tables to the webpage -# 5. Separate the stage tables -# 6. Terminate the outer table -# 7. Add the trailer to the webpage -# -$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(html_table_files) - echo "<html>" > $@ - echo "<head>" >> $@ - echo "<title>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status</title>" >> $@ - echo "</title>" >> $@ - echo "<body>" >> $@ - echo "<h1>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status<br>$(current_date_time)</h1>" >> $@ - echo "<table>" >> $@ - echo " <tr><td colspan=2><b>Legend</b></td></tr>" >> $@ - echo " <tr><td bgcolor=\"#ffc0c0\">Red</td><td>Required - To-be-implemented</td></tr>" >> $@ - echo " <tr><td bgcolor=\"#ffffc0\">Yellow</td><td>Optional</td></tr>" >> $@ - echo " <tr><td bgcolor=\"#c0ffc0\">Green</td><td>Implemented</td></tr>" >> $@ - echo "</table>" >> $@ - echo "<table>" >> $@ - echo " <tr valign=\"top\">" >> $@ - for table in $(list_of_html_files); do \ - echo " <td>" >> $@; \ - cat $$table >> $@; \ - echo " </td>" >> $@; \ - echo " <td width=5> </td>" >> $@; \ - done - echo " </tr>" >> $@ - echo "</table>" >> $@ - echo "</body>" >> $@ - echo "</html>" >> $@ - -# -# Copy the output file into the Documentation directory -# -Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html - if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR) ]; then \ - mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR); \ - fi - if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board ]; then \ - mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board; \ - fi - cp $< $@ - -# -# Determine where to place the output file -# -ifeq ($(CONFIG_MAKE_CHECKLIST_PUBLIC),y) -INTERMEDIATE+=Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html -else -INTERMEDIATE+=$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html -endif - -endif diff --git a/util/checklist/description.md b/util/checklist/description.md deleted file mode 100644 index 3133ed2..0000000 --- a/util/checklist/description.md +++ /dev/null @@ -1 +0,0 @@ -Board implementation checklist generator `Make` -- To view, visit https://review.coreboot.org/c/coreboot/+/30691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c Gerrit-Change-Number: 30691 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by Martin Roth (Code Review) 14 Jan '19

14 Jan '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30348 ) Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/30348/2/3rdparty/blobs File 3rdparty/blobs: https://review.coreboot.org/#/c/30348/2/3rdparty/blobs@1 PS2, Line 1: Subproject commit dd00ad1260ef1dc0ba8c55c06ab10c7639dc3eb1 Accidental update? https://review.coreboot.org/#/c/30348/2/src/arch/riscv/Kconfig File src/arch/riscv/Kconfig: https://review.coreboot.org/#/c/30348/2/src/arch/riscv/Kconfig@14 PS2, Line 14: config ARCH_RISCV_M : # Whether a SOC implements M mode. : # M mode is the most privileged mode, it is : # the equivalent in some ways of x86 SMM mode : # save that in M mode it is impossible to turn : # on paging. : # While the spec requires it, there is at least : # one implementation that will not have it due : # to security concerns. : bool : default y Maybe add another config option to allow this to be disabled via a select: config ARCH_RISCV_M_DISABLED bool config ARCH_RISCV_M bool default n if ARCH_RISCV_M_DISABLED default y https://review.coreboot.org/#/c/30348/2/src/arch/riscv/Kconfig@40 PS2, Line 40: config ARCH_RISCV_RV32 : bool : default n maybe default this to y unless 64-bit is selected? -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Jan 2019 19:41:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30348 ) Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/30348/2/3rdparty/blobs File 3rdparty/blobs: PS2: I suppose this change doesn't belong in this commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Jan 2019 19:41:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/apollolake: Hook up microcode
by Lijian Zhao (Code Review) 14 Jan '19

14 Jan '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30885 ) Change subject: soc/intel/apollolake: Hook up microcode ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/30885/1/src/soc/intel/apollolake/Makefile.i… File src/soc/intel/apollolake/Makefile.inc: https://review.coreboot.org/#/c/30885/1/src/soc/intel/apollolake/Makefile.i… PS1, Line 141: Micorcode > Microcode Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b42dc00d82c9d80d72a911762e79a4e48809281 Gerrit-Change-Number: 30885 Gerrit-PatchSet: 2 Gerrit-Owner: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: John Zhao <john.zhao(a)intel.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Mon, 14 Jan 2019 19:27:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/apollolake: Hook up microcode
by Lijian Zhao (Code Review) 14 Jan '19

14 Jan '19

Lijian Zhao has uploaded a new patch set (#2) to the change originally created by Lance Zhao. ( https://review.coreboot.org/c/coreboot/+/30885 ) Change subject: soc/intel/apollolake: Hook up microcode ...................................................................... soc/intel/apollolake: Hook up microcode Hook up Apollolake, Broxton and Geminilake microcode to blobs. BUG=N/A TEST=Build and boot up on Yorp platform. Change-Id: I7b42dc00d82c9d80d72a911762e79a4e48809281 Signed-off-by: lance <lance.zhao(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30885/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b42dc00d82c9d80d72a911762e79a4e48809281 Gerrit-Change-Number: 30885 Gerrit-PatchSet: 2 Gerrit-Owner: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: John Zhao <john.zhao(a)intel.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: AGESA: Drop CONFIG_CBB and CONFIG_CDB
by Kyösti Mälkki (Code Review) 14 Jan '19

14 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30732 Change subject: AGESA: Drop CONFIG_CBB and CONFIG_CDB ...................................................................... AGESA: Drop CONFIG_CBB and CONFIG_CDB Static values, copy paste from multi-node fam15 code. Change-Id: I07bc046c74280f49e46793c119d36b87b8789949 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family12/Kconfig M src/cpu/amd/agesa/family14/Kconfig M src/cpu/amd/agesa/family15tn/Kconfig M src/cpu/amd/agesa/family16kb/Kconfig M src/northbridge/amd/agesa/family12/amdfam12_conf.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/amdfam14_conf.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/southbridge/amd/cimx/sb800/reset.c M src/southbridge/amd/cimx/sb900/reset.c 12 files changed, 20 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30732/1 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index fa9cd5f..921ec90 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -23,14 +23,6 @@ int default 48 -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index c539d27..0ee7eb0 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -23,14 +23,6 @@ int default 36 -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 1cc77b8..7514590 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -23,14 +23,6 @@ int default 48 -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 0cdf55a..5138745 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -23,14 +23,6 @@ int default 40 -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 0e5dc3c..b7f0741 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -27,7 +27,7 @@ struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); + dev = PCI_DEV(0x0, 0x18, 1); #else dev = __f1_dev[0]; #endif // defined(__PRE_RAM__) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index a290eff..f8da3af 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -46,7 +46,7 @@ static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); } static void get_fx_devs(void) @@ -89,7 +89,7 @@ static u32 amdfam12_nodeid(struct device *dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; } #include "amdfam12_conf.c" diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 0eabaa8..2bc8367 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -27,7 +27,7 @@ struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); + dev = PCI_DEV(0x0, 0x18, 1); #else dev = __f1_dev[0]; #endif // defined(__PRE_RAM__) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index adf7878..2fe9d4a 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -43,7 +43,7 @@ static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); } static void get_fx_devs(void) @@ -85,7 +85,7 @@ static u32 amdfam14_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; } #include "amdfam14_conf.c" diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index f1a2051..292c08c 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -99,7 +99,7 @@ static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); } static void get_fx_devs(void) @@ -142,7 +142,7 @@ static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -818,9 +818,9 @@ int siblings = 0; unsigned int family; - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(0x18, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0x0, 0x18); die(""); } sysconf_init(dev_mc); @@ -843,7 +843,7 @@ unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = 0x18 + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cf7e3f8..b4b1a46 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -98,7 +98,7 @@ static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); } static void get_fx_devs(void) @@ -141,7 +141,7 @@ static u32 amdfam16_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -843,9 +843,9 @@ int siblings = 0; unsigned int family; - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(0x18, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0x0, 0x18); die(""); } sysconf_init(dev_mc); @@ -868,7 +868,7 @@ unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = 0x18 + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index b7ee613..43a4859 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -23,7 +23,7 @@ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) -#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#define NODE_PCI(x, fn) (((0x18+x)<32)?(PCI_DEV(0x0,(0x18+x),fn)):(PCI_DEV((0x0-1),(0x18+x-32),fn))) void cf9_reset_prepare(void) { @@ -32,7 +32,7 @@ pci_devfn_t dev; int i; - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = ((pci_read_config32(PCI_DEV(0x0, 0x18, 0), 0x60) >> 4) & 7) + 1; for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index b7ee613..43a4859 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -23,7 +23,7 @@ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) -#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#define NODE_PCI(x, fn) (((0x18+x)<32)?(PCI_DEV(0x0,(0x18+x),fn)):(PCI_DEV((0x0-1),(0x18+x-32),fn))) void cf9_reset_prepare(void) { @@ -32,7 +32,7 @@ pci_devfn_t dev; int i; - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = ((pci_read_config32(PCI_DEV(0x0, 0x18, 0), 0x60) >> 4) & 7) + 1; for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); -- To view, visit https://review.coreboot.org/c/coreboot/+/30732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07bc046c74280f49e46793c119d36b87b8789949 Gerrit-Change-Number: 30732 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: soc/intel/cannonlake: Program internal SVID/SSID
by Lijian Zhao (Code Review) 14 Jan '19

14 Jan '19

Lijian Zhao has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: soc/intel/cannonlake: Program internal SVID/SSID ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 12 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: soc/intel/common: Add SSID header
by Lijian Zhao (Code Review) 14 Jan '19

14 Jan '19

Lijian Zhao has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29490 ) Change subject: soc/intel/common: Add SSID header ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bdabdd927fa477821f400e49c5787f405d0a9ea Gerrit-Change-Number: 29490 Gerrit-PatchSet: 13 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by ron minnich (Code Review) 14 Jan '19

14 Jan '19

Hello Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30348 to look at the new patch set (#2). Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... riscv: create Kconfig architecture features for new parts RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. We do not create more than we need for coreboot. With this change, and a conditional compilation of PMP as an example, hifive still builds. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M 3rdparty/blobs M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 5 files changed, 56 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30348/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Add processor power limits control support
by Sumeet R Pawnikar (Code Review) 14 Jan '19

14 Jan '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30907 Change subject: soc/intel/cannonlake: Add processor power limits control support ...................................................................... soc/intel/cannonlake: Add processor power limits control support Add processor power limits control support to configure values. BRANCH=None BUG=b:122343940 TEST=Built and tested on Arcada system Change-Id: I5990dc05b51481a0074855914cef20cf07378cde Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/msr.h M src/soc/intel/cannonlake/systemagent.c 4 files changed, 220 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/30907/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 6517b9e..63cbaf7 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -197,8 +197,22 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + + /* PL1 Override value in Watts */ + uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ uint32_t tdp_pl2_override; + /* SysPL2 Value in Watts */ + uint32_t tdp_psyspl2; + /* SysPL3 Value in Watts */ + uint32_t tdp_psyspl3; + /* SysPL3 window size */ + uint32_t tdp_psyspl3_time; + /* SysPL3 duty cycle */ + uint32_t tdp_psyspl3_dutycycle; + /* PL4 Value in Watts */ + uint32_t tdp_pl4; + /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; /* Enable VR specific mailbox command diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 9601863..8f83db6 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -30,6 +30,198 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smm.h> +#include <soc/systemagent.h> + +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + msr_t limit; + unsigned int power_unit; + unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; + u8 power_limit_1_val; + struct device *dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + + if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = 28; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (msr.lo & 0xf); + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + tdp_pl1 = ((conf->tdp_pl1_override == 0) ? + tdp : (conf->tdp_pl1_override * power_unit)); + limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); + + /* Set PL1 Pkg Power clamp bit */ + limit.lo |= PKG_POWER_LIMIT_CLAMP; + + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP if no config given */ + limit.hi = 0; + tdp_pl2 = (conf->tdp_pl2_override == 0) ? + (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); + printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit); + limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_CLAMP; + limit.hi |= PKG_POWER_LIMIT_EN; + + /* Power limit 2 time is only programmable on server SKU */ + wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Set PL2 power limit values in MCHBAR and disable PL1 */ + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); + MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; + + /* Set PsysPl2 */ + if (conf->tdp_psyspl2) { + limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); + limit.hi = 0; + printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", + conf->tdp_psyspl2); + limit.hi |= (conf->tdp_psyspl2 * power_unit) & + PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_CLAMP; + limit.hi |= PKG_POWER_LIMIT_EN; + + wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); + } + + /* Set PsysPl3 */ + if (conf->tdp_psyspl3) { + limit = rdmsr(MSR_PL3_CONTROL); + limit.lo = 0; + printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", + conf->tdp_psyspl3); + limit.lo |= (conf->tdp_psyspl3 * power_unit) & + PKG_POWER_LIMIT_MASK; + /* Enable PsysPl3 */ + limit.lo |= PKG_POWER_LIMIT_EN; + /* set PsysPl3 time window */ + limit.lo |= (conf->tdp_psyspl3_time & + PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + /* set PsysPl3 duty cycle */ + limit.lo |= (conf->tdp_psyspl3_dutycycle & + PKG_POWER_LIMIT_DUTYCYCLE_MASK) << + PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; + wrmsr(MSR_PL3_CONTROL, limit); + } + + /* Set Pl4 */ + if (conf->tdp_pl4) { + limit = rdmsr(MSR_VR_CURRENT_CONFIG); + limit.lo = 0; + printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", + conf->tdp_pl4); + limit.lo |= (conf->tdp_pl4 * power_unit) & + PKG_POWER_LIMIT_MASK; + wrmsr(MSR_VR_CURRENT_CONFIG, limit); + } + + /* Set DDR RAPL power limit by copying from MMIO to MSR */ + msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); + msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); + wrmsr(MSR_DDR_RAPL_LIMIT, msr); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + limit.hi = 0; + limit.lo = cpu_get_tdp_nominal_ratio(); + wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); + } +} static void soc_fsp_load(void) { @@ -65,6 +257,10 @@ static void configure_misc(void) { struct device *dev = SA_DEV_ROOT; + if (!dev) { + printk(BIOS_ERR, "SA_DEV_ROOT device not found!\n"); + return; + } config_t *conf = dev->chip_info; msr_t msr; diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index e3bd5f6..63595f3 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -20,6 +20,9 @@ #include <intelblocks/msr.h> #define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_VR_CURRENT_CONFIG 0x601 +#define MSR_PL3_CONTROL 0x615 #define MSR_VR_MISC_CONFIG2 0x636 +#define MSR_PLATFORM_POWER_LIMIT 0x65c #endif diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index e6310c0..26f8d9e 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -16,8 +16,10 @@ */ #include <device/device.h> +#include <delay.h> #include <device/pci.h> #include <intelblocks/systemagent.h> +#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/systemagent.h> @@ -52,6 +54,7 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + } /* @@ -66,4 +69,8 @@ /* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + set_power_limits(28); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5990dc05b51481a0074855914cef20cf07378cde Gerrit-Change-Number: 30907 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019