coreboot-gerrit January 2019

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Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by Angel Pons (Code Review) 14 Jan '19

14 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 ) Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... Patch Set 12: (4 comments) https://review.coreboot.org/#/c/30414/12/Documentation/mainboard/facebook/f… File Documentation/mainboard/facebook/fbg1701.md: https://review.coreboot.org/#/c/30414/12/Documentation/mainboard/facebook/f… PS12, Line 11: : A fully working image should be possible What does this mean? https://review.coreboot.org/#/c/30414/12/Documentation/mainboard/facebook/f… PS12, Line 39: Trailing space https://review.coreboot.org/#/c/30414/12/Documentation/mainboard/facebook/f… PS12, Line 43: DIP-8 Is it DIP-8? The linked datasheet mentions nothing about DIP-8. Maybe SOIC-8? (I don't know, I have not seen the mainboard) https://review.coreboot.org/#/c/30414/12/Documentation/mainboard/facebook/f… PS12, Line 48: 3.5V 3.3V I'd say -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 14 Jan 2019 23:27:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/eltan: Add vendor code for measured and verified boot
by Angel Pons (Code Review) 14 Jan '19

14 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30218 ) Change subject: vendorcode/eltan: Add vendor code for measured and verified boot ...................................................................... Patch Set 8: > Patch Set 8: > > > Patch Set 7: > > > > BTW, you can add all the related patches to the same gerrit topic so that it is easier to keep track of them. There is also the option of using patch trains, so that you build on previous, not yet merged patches. It is good for reviewing as well, since one can follow the order in which the code was added. > > Use same gerrit topic for all patches? > Do you have an example of 'patch train'? Or you mean to rebase a patch on other patch? A patch train is (if I understand the concept properly) a group of patches which follow each other. The idea is to divide a very large patchset into a series of steps to reach the same point as the big patchset, but with each patch doing one logical change. The idea is that each patch train builds on top of the previous one (sort of laying bricks one atop the other). I see you added a topic to all the patches already, which is good. I am not sure how you work on the patches, but to put them together in a train I would: - Clean the local git repo - Cherry-pick each patch in order (each patch is a building block) - When all are cherry-picked, push to gerrit I hope this helps. -- To view, visit https://review.coreboot.org/c/coreboot/+/30218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80 Gerrit-Change-Number: 30218 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 14 Jan 2019 23:16:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: console: Change BOOTBLOCK_CONSOLE default to `y`
by Nico Huber (Code Review) 14 Jan '19

14 Jan '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30891 Change subject: console: Change BOOTBLOCK_CONSOLE default to `y` ...................................................................... console: Change BOOTBLOCK_CONSOLE default to `y` Invert the default instead of selecting it everywhere. Restores the ability to use its Kconfig prompt. Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/Kconfig M src/cpu/allwinner/a10/Kconfig M src/cpu/ti/am335x/Kconfig M src/mainboard/emulation/qemu-armv7/Kconfig M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/google/urara/Kconfig M src/mainboard/intel/galileo/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8183/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq806x/Kconfig M src/soc/qualcomm/sdm845/Kconfig M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/Kconfig M src/soc/samsung/exynos5250/Kconfig M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 25 files changed, 1 insertion(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/30891/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 9cacab0..82f7441 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -3,7 +3,7 @@ config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." depends on C_ENVIRONMENT_BOOTBLOCK - default n + default y help Use console during the bootblock if supported diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 6451b4a..87693ed 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select BOOTBLOCK_CONSOLE select UART_OVERRIDE_REFCLK select BOOT_DEVICE_NOT_SPI_FLASH diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index 939bca7..20e7458 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -5,7 +5,6 @@ select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select BOOTBLOCK_CONSOLE select GENERIC_UDELAY select UART_OVERRIDE_REFCLK select BOOT_DEVICE_NOT_SPI_FLASH diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index c24bf68..0bb5f3a 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -25,7 +25,6 @@ def_bool y select CPU_ARMLTD_CORTEX_A9 select DRIVERS_UART_PL011 - select BOOTBLOCK_CONSOLE select CONSOLE_SERIAL select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index eb9f011..78ca2d9 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -12,7 +12,6 @@ select BOARD_ROMSIZE_KB_256 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT - select BOOTBLOCK_CONSOLE select NO_CAR_GLOBAL_MIGRATION config MAINBOARD_DIR diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 1cc7148..1ceb62c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,7 +11,6 @@ select BOARD_ROMSIZE_KB_2048 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT - select BOOTBLOCK_CONSOLE select NO_CAR_GLOBAL_MIGRATION config MAINBOARD_DIR diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index 3d415c4..19d5c41 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_512 - select BOOTBLOCK_CONSOLE select SPI_FLASH_WINBOND select CPU_IMGTEC_PISTACHIO select COMMON_CBFS_SPI_WRAPPER diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 87f82bc..bddc036 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -133,7 +133,6 @@ depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 default y # Enable display and verification for coreboot build tests - select BOOTBLOCK_CONSOLE select DISPLAY_HOBS select DISPLAY_MTRRS select DISPLAY_SMM_MEMORY_MAP diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 03a40cc..80798d9 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -52,7 +52,6 @@ select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 if HAVE_ACPI_RESUME select C_ENVIRONMENT_BOOTBLOCK - select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 24d386c..4bf2e65 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -5,7 +5,6 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 - select BOOTBLOCK_CONSOLE select DRIVERS_UART_PL011 select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index dcf1b1a..ef7fa47 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -24,7 +24,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 5b704b9..1096549 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -26,7 +26,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 7dcf8a9..442b09a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -20,7 +20,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index cf0c8d9..b0d6fa0 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -7,7 +7,6 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 select ARM64_USE_ARM_TRUSTED_FIRMWARE - select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index 51c6df3..6582e4e 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -6,7 +6,6 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 select ARM64_USE_ARM_TRUSTED_FIRMWARE - select BOOTBLOCK_CONSOLE select GENERIC_UDELAY select HAVE_UART_SPECIAL select HAVE_MONOTONIC_TIMER diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 0e83774..eecb59b 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -9,7 +9,6 @@ select HAVE_UART_SPECIAL select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY - select BOOTBLOCK_CONSOLE select ARM_LPAE select GENERIC_GPIO_LIB select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 44e4719..8883baa 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -6,7 +6,6 @@ select ARCH_VERSTAGE_ARMV4 select ARCH_ROMSTAGE_ARMV4 select ARCH_RAMSTAGE_ARMV8_64 - select BOOTBLOCK_CONSOLE select GIC select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 2cfcd2d..72e05fa 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -5,7 +5,6 @@ select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 - select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select GENERIC_GPIO_LIB select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index a6262d0..0b112d9 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -5,7 +5,6 @@ select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 - select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select GENERIC_GPIO_LIB diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index 9af1954..c0e3294 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 - select BOOTBLOCK_CONSOLE select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index e0fd718..53666c2 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -23,7 +23,6 @@ select DRIVERS_UART_8250MEM_32 select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY - select BOOTBLOCK_CONSOLE select UNCOMPRESSED_RAMSTAGE select GENERIC_GPIO_LIB select RTC diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 440981b..6e45df3 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -6,7 +6,6 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 select ARM64_USE_ARM_TRUSTED_FIRMWARE - select BOOTBLOCK_CONSOLE select DRIVERS_UART_8250MEM_32 select GENERIC_GPIO_LIB select GENERIC_UDELAY diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 1c92c71..5b39724 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -6,7 +6,6 @@ select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAVE_UART_SPECIAL - select BOOTBLOCK_CONSOLE bool default n diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 795f51b..25b4b46 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -18,7 +18,6 @@ select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV - select BOOTBLOCK_CONSOLE select DRIVERS_UART_SIFIVE select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index 99b0490..638d734 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -4,7 +4,6 @@ select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV - select BOOTBLOCK_CONSOLE select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select RISCV_USE_ARCH_TIMER -- To view, visit https://review.coreboot.org/c/coreboot/+/30891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Gerrit-Change-Number: 30891 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/variants/bobba: Add WCOM reset delay
by Justin TerAvest (Code Review) 14 Jan '19

14 Jan '19

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30924 Change subject: mb/google/octopus/variants/bobba: Add WCOM reset delay ...................................................................... mb/google/octopus/variants/bobba: Add WCOM reset delay Add reset delay in power resource for WACOM digitizers to prevent bind failure after unbind, as can currently happen in the touch firmware update flow in Chrome OS. BUG=b:117474421 BRANCH=octopus TEST=None Change-Id: I1ee03e423a6888355bb0d468d8ad140b0ad88bf8 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/variants/bobba/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/30924/1 diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 17686f6..9706e69 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -92,6 +92,7 @@ register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/30924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ee03e423a6888355bb0d468d8ad140b0ad88bf8 Gerrit-Change-Number: 30924 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Revert "mb/google/octopus: Add custom SAR values for Bobba"
by Justin TerAvest (Code Review) 14 Jan '19

14 Jan '19

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30923 Change subject: Revert "mb/google/octopus: Add custom SAR values for Bobba" ...................................................................... Revert "mb/google/octopus: Add custom SAR values for Bobba" According to the partner on this project, custom values like this are no longer necessary. BUG=b:120958726 TEST=None This reverts commit a914152fa6072c443ccd18de22412b47a228e754. Change-Id: I8da5c750e5a4e91c7f83cf3bae024ed11cd784b2 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/variants/bobba/Makefile.inc D src/mainboard/google/octopus/variants/bobba/mainboard.c 2 files changed, 0 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/30923/1 diff --git a/src/mainboard/google/octopus/variants/bobba/Makefile.inc b/src/mainboard/google/octopus/variants/bobba/Makefile.inc index 152b46e..9fb63f5 100644 --- a/src/mainboard/google/octopus/variants/bobba/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bobba/Makefile.inc @@ -1,4 +1,3 @@ bootblock-y += gpio.c ramstage-y += gpio.c -ramstage-y += mainboard.c diff --git a/src/mainboard/google/octopus/variants/bobba/mainboard.c b/src/mainboard/google/octopus/variants/bobba/mainboard.c deleted file mode 100644 index 61098b7..0000000 --- a/src/mainboard/google/octopus/variants/bobba/mainboard.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boardid.h> -#include <ec/google/chromeec/ec.h> -#include <sar.h> - -const char *get_wifi_sar_cbfs_filename(void) -{ - const char *filename = NULL; - uint32_t sku_id; - if (google_chromeec_cbi_get_sku_id(&sku_id)) - return NULL; - - switch (sku_id) { - case 9: - case 10: - case 11: - case 12: - filename = "wifi_sar-bobba360.hex"; - break; - } - return filename; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/30923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8da5c750e5a4e91c7f83cf3bae024ed11cd784b2 Gerrit-Change-Number: 30923 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by ron minnich (Code Review) 14 Jan '19

14 Jan '19

Hello Jonathan Neuschäfer, build bot (Jenkins), Martin Roth, Patrick Georgi, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30348 to look at the new patch set (#4). Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... riscv: create Kconfig architecture features for new parts RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. We do not create more than we need for coreboot. With this change, and a conditional compilation of PMP as an example, hifive still builds. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 4 files changed, 59 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30348/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 4 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/apl: Hook microcode updates up
by Angel Pons (Code Review) 14 Jan '19

14 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29902 ) Change subject: soc/intel/apl: Hook microcode updates up ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f680fc4342a9bd1cd0ba9d72e025995e25f7f2 Gerrit-Change-Number: 29902 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 14 Jan 2019 22:16:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by ron minnich (Code Review) 14 Jan '19

14 Jan '19

ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30348 ) Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... Patch Set 3: (9 comments) https://review.coreboot.org/#/c/30348/1/3rdparty/blobs File 3rdparty/blobs: https://review.coreboot.org/#/c/30348/1/3rdparty/blobs@1 PS1, Line 1: Subproject commit dd00ad1260ef1dc0ba8c55c06ab10c7639dc3eb1 > This slipped in by accident, I guess fixed. https://review.coreboot.org/#/c/30348/1/src/arch/riscv/Kconfig File src/arch/riscv/Kconfig: https://review.coreboot.org/#/c/30348/1/src/arch/riscv/Kconfig@14 PS1, Line 14: config ARCH_RISCV_M > Please add descriptions to make it clear what these options mean, either as comments or with "help" […] Done https://review.coreboot.org/#/c/30348/1/src/arch/riscv/Kconfig@15 PS1, Line 15: bool > ARCH_RISCV_M seems unnecessary, because M-mode is mandated (RISC-V Priv. Arch. spec. 1. […] There is a SOC in the works that won't have M. https://review.coreboot.org/#/c/30348/1/src/arch/riscv/Kconfig@22 PS1, Line 22: config ARCH_RISCV_H > H-mode has been dropped, it's gone in the Privileged Architecture spec 1.10. Done https://review.coreboot.org/#/c/30348/1/src/arch/riscv/Kconfig@26 PS1, Line 26: config ARCH_RISCV_U > I'm not sure about the purpose of ARCH_RISCV_S and ARCH_RISCV_U. […] They are required for an SOC I will be pushing but in general for, e.g., rv32 that don't have those modes. Leaving them out was a mistake I made at the start. https://review.coreboot.org/#/c/30348/1/src/arch/riscv/Kconfig@30 PS1, Line 30: config ARCH_RISCV_RV64 That's seeming less likely all the time but we'll see. https://review.coreboot.org/#/c/30348/2/src/arch/riscv/Kconfig File src/arch/riscv/Kconfig: https://review.coreboot.org/#/c/30348/2/src/arch/riscv/Kconfig@14 PS2, Line 14: config ARCH_RISCV_M : # Whether a SOC implements M mode. : # M mode is the most privileged mode, it is : # the equivalent in some ways of x86 SMM mode : # save that in M mode it is impossible to turn : # on paging. : # While the spec requires it, there is at least : # one implementation that will not have it due : # to security concerns. : bool : default y > Maybe add another config option to allow this to be disabled via a select: […] excellent idea. https://review.coreboot.org/#/c/30348/2/src/arch/riscv/Kconfig@40 PS2, Line 40: config ARCH_RISCV_RV32 : bool : default n > maybe default this to y unless 64-bit is selected? let's not. I don't want people to pick it by accident https://review.coreboot.org/#/c/30348/1/src/arch/riscv/Makefile.inc File src/arch/riscv/Makefile.inc: https://review.coreboot.org/#/c/30348/1/src/arch/riscv/Makefile.inc@40 PS1, Line 40: $(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32") > You're in the if branch for clang analyzer, here. […] i can't figure out this makefile. But I'll give it a try. -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Jan 2019 22:15:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by ron minnich (Code Review) 14 Jan '19

14 Jan '19

Hello Jonathan Neuschäfer, build bot (Jenkins), Martin Roth, Patrick Georgi, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30348 to look at the new patch set (#3). Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... riscv: create Kconfig architecture features for new parts RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. We do not create more than we need for coreboot. With this change, and a conditional compilation of PMP as an example, hifive still builds. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M 3rdparty/blobs M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 5 files changed, 60 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30348/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/kukui: add flapjack on top of kukui
by Julius Werner (Code Review) 14 Jan '19

14 Jan '19

Julius Werner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30837 ) Change subject: mb/google/kukui: add flapjack on top of kukui ...................................................................... Abandoned replaced by CB:30859 -- To view, visit https://review.coreboot.org/c/coreboot/+/30837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70f3c6e0450db5768d8ecb200effba84cca52dcc Gerrit-Change-Number: 30837 Gerrit-PatchSet: 2 Gerrit-Owner: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Nick Sanders <nsanders(a)chromium.org> Gerrit-MessageType: abandon

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coreboot-gerrit January 2019