coreboot-gerrit January 2019

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Change in ...coreboot[master]: lib/boot_device: Add API for write protect a region
by Patrick Rudolph (Code Review) 14 Jan '19

14 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28724 ) Change subject: lib/boot_device: Add API for write protect a region ...................................................................... Patch Set 15: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/28724/15/src/lib/boot_device.c File src/lib/boot_device.c: https://review.coreboot.org/#/c/28724/15/src/lib/boot_device.c@24 PS15, Line 24: enum bootdev_prot_type type) align with ( -- To view, visit https://review.coreboot.org/c/coreboot/+/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 15 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 14 Jan 2019 15:38:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29973 ) Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 4: (39 comments) https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py File util/qualcomm/createxbl.py: https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@25 PS4, Line 25: # 09/04/15 et Added -x and -d to embed xbl_sec ELF trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@68 PS4, Line 68: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@84 PS4, Line 84: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@103 PS4, Line 103: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@113 PS4, Line 113: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@121 PS4, Line 121: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@144 PS4, Line 144: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@164 PS4, Line 164: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@172 PS4, Line 172: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@192 PS4, Line 192: header_format = 'reg' trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@223 PS4, Line 223: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@231 PS4, Line 231: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@232 PS4, Line 232: # Create hash table trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@235 PS4, Line 235: target_hash, trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@237 PS4, Line 237: secure_type = image_header_secflag) trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@245 PS4, Line 245: target_hash_hd, trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@254 PS4, Line 254: # Add the hash segment into the ELF trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@272 PS4, Line 272: def merge_elfs(env, trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@284 PS4, Line 284: mbn_tools.preprocess_elf_file(elf_in_file_name1) trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@289 PS4, Line 289: mbn_tools.preprocess_elf_file(elf_in_file_name2) trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@290 PS4, Line 290: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@294 PS4, Line 294: mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@325 PS4, Line 325: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@364 PS4, Line 364: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@400 PS4, Line 400: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@477 PS4, Line 477: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@512 PS4, Line 512: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@614 PS4, Line 614: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@618 PS4, Line 618: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@621 PS4, Line 621: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@640 PS4, Line 640: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@674 PS4, Line 674: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@675 PS4, Line 675: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@681 PS4, Line 681: inp_data_offset = 0 trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@682 PS4, Line 682: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@689 PS4, Line 689: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@706 PS4, Line 706: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/createxbl.py@708 PS4, Line 708: trailing whitespace https://review.coreboot.org/#/c/29973/4/util/qualcomm/mbn_tools.py File util/qualcomm/mbn_tools.py: https://review.coreboot.org/#/c/29973/4/util/qualcomm/mbn_tools.py@1167 PS4, Line 1167: # Check if a shifting is required to accomodate for the hash segment. 'accomodate' may be misspelled - perhaps 'accommodate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 4 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:28:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 4: (95 comments) https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/clock.c@206 PS4, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/clock.c@206 PS4, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/clock.c@207 PS4, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/clock.c@207 PS4, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/clock.c@208 PS4, Line 208: BLSP2_AHB_CLK_ENA); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/clock.c@208 PS4, Line 208: BLSP2_AHB_CLK_ENA); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/qup.h: https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 161: unsigned clk_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 162: unsigned src_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 164: unsigned initialized; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 173: unsigned data_len; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 178: unsigned size; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@63 PS4, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@63 PS4, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@63 PS4, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@64 PS4, Line 64: /* BLSP5 registers for SPI interface */ code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@65 PS4, Line 65: { code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@65 PS4, Line 65: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@66 PS4, Line 66: BLSP5_SPI_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@66 PS4, Line 66: BLSP5_SPI_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@67 PS4, Line 67: BLSP5_SPI_IO_CONTROL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@67 PS4, Line 67: BLSP5_SPI_IO_CONTROL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@68 PS4, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@68 PS4, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@69 PS4, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@69 PS4, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@70 PS4, Line 70: BLSP5_QUP_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@70 PS4, Line 70: BLSP5_QUP_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@71 PS4, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@71 PS4, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@72 PS4, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@72 PS4, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@73 PS4, Line 73: BLSP5_QUP_OPERATIONAL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@73 PS4, Line 73: BLSP5_QUP_OPERATIONAL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@74 PS4, Line 74: BLSP5_QUP_IO_MODES_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@74 PS4, Line 74: BLSP5_QUP_IO_MODES_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@75 PS4, Line 75: BLSP5_QUP_STATE_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@75 PS4, Line 75: BLSP5_QUP_STATE_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@76 PS4, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@76 PS4, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@77 PS4, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@77 PS4, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@78 PS4, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@78 PS4, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@79 PS4, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@79 PS4, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@80 PS4, Line 80: BLSP5_QUP_SW_RESET_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@80 PS4, Line 80: BLSP5_QUP_SW_RESET_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@81 PS4, Line 81: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@81 PS4, Line 81: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@82 PS4, Line 82: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@82 PS4, Line 82: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@83 PS4, Line 83: BLSP5_QUP_OPERATIONAL_MASK, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@83 PS4, Line 83: BLSP5_QUP_OPERATIONAL_MASK, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@84 PS4, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@84 PS4, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@85 PS4, Line 85: }, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@85 PS4, Line 85: }, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@273 PS4, Line 273: SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); line over 80 characters https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@310 PS4, Line 310: switch(slave->bus) { switch and case should be at the same indent https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@310 PS4, Line 310: switch(slave->bus) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@311 PS4, Line 311: case 5: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@311 PS4, Line 311: case 5: please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@313 PS4, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@313 PS4, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@313 PS4, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@314 PS4, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@314 PS4, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@314 PS4, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@315 PS4, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@315 PS4, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@315 PS4, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@316 PS4, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@316 PS4, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@316 PS4, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@318 PS4, Line 318: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@318 PS4, Line 318: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@319 PS4, Line 319: default: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@320 PS4, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); line over 80 characters https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@320 PS4, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@320 PS4, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@321 PS4, Line 321: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@321 PS4, Line 321: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@322 PS4, Line 322: } code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@322 PS4, Line 322: } please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@354 PS4, Line 354: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@428 PS4, Line 428: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@684 PS4, Line 684: "or chipselect\n", bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@684 PS4, Line 684: "or chipselect\n", bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@713 PS4, Line 713: static int xfer_vectors(const struct spi_slave *slave, open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@714 PS4, Line 714: struct spi_op vectors[], size_t count) code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@714 PS4, Line 714: struct spi_op vectors[], size_t count) please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@715 PS4, Line 715: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@716 PS4, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@716 PS4, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/4/src/soc/qualcomm/qcs405/spi.c@717 PS4, Line 717: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 4 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:28:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/#/c/29966/4/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/4/src/soc/qualcomm/qcs405/usb.c@137 PS4, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/4/src/soc/qualcomm/qcs405/usb.c@138 PS4, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/4/src/soc/qualcomm/qcs405/usb.c@139 PS4, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/4/src/soc/qualcomm/qcs405/usb.c@140 PS4, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 4 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:28:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 4: (14 comments) https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 43: struct prog pmic = code indent should use tabs where possible https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 43: struct prog pmic = please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); code indent should use tabs where possible https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 52: if (prog_locate(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 52: if (prog_locate(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 53: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 53: goto fail; please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 55: if (cbfs_prog_stage_load(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 55: if (cbfs_prog_stage_load(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 56: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/4/src/soc/qualcomm/qcs405/qclib_execu… PS4, Line 56: goto fail; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 4 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 14 Jan 2019 15:28:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp uart driver
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add blsp uart driver ...................................................................... Patch Set 4: (25 comments) https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/cdp.h: https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 36: unsigned smem_get_board_machtype(void); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 89: SPI_CS_0 , space prohibited before that ',' (ctx:WxE) https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 119: unsigned count; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 124: unsigned base; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 126: unsigned is_macsec; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 127: unsigned mac_pwr0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 128: unsigned mac_pwr1; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 129: unsigned mac_conn_to_phy; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 172: unsigned int get_board_index(unsigned machid); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 173: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/iomap.h: https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/include/soc… PS4, Line 49: #define writel_i(v,a) write32((void *)a, v) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c File src/soc/qualcomm/qcs405/uart.c: https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@50 PS4, Line 50: unsigned blsp_uart; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@54 PS4, Line 54: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@56 PS4, Line 56: int i; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@56 PS4, Line 56: int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@58 PS4, Line 58: for (i = 0; i < count; i++) { code indent should use tabs where possible https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@58 PS4, Line 58: for (i = 0; i < count; i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@59 PS4, Line 59: gpio_configure(gpio->gpio, gpio->func, code indent should use tabs where possible https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@59 PS4, Line 59: gpio_configure(gpio->gpio, gpio->func, please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@60 PS4, Line 60: gpio->pull, gpio->drvstr, gpio->enable); code indent should use tabs where possible https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@60 PS4, Line 60: gpio->pull, gpio->drvstr, gpio->enable); please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@61 PS4, Line 61: gpio++; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@61 PS4, Line 61: gpio++; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@62 PS4, Line 62: } code indent should use tabs where possible https://review.coreboot.org/#/c/29964/4/src/soc/qualcomm/qcs405/uart.c@62 PS4, Line 62: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 4 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:27:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by build bot (Jenkins) (Code Review) 14 Jan '19

14 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29959 ) Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... Patch Set 4: (6 comments) https://review.coreboot.org/#/c/29959/4/src/soc/qualcomm/qcs405/flash_contr… File src/soc/qualcomm/qcs405/flash_controller.c: https://review.coreboot.org/#/c/29959/4/src/soc/qualcomm/qcs405/flash_contr… PS4, Line 37: static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) line over 80 characters https://review.coreboot.org/#/c/29959/4/src/soc/qualcomm/qcs405/flash_contr… PS4, Line 68: { that open brace { should be on the previous line https://review.coreboot.org/#/c/29959/4/src/soc/qualcomm/qcs405/flash_contr… PS4, Line 78: static char name[] = "ram_flash"; static char array declaration should probably be static const char https://review.coreboot.org/#/c/29959/4/src/soc/qualcomm/qcs405/flash_contr… PS4, Line 80: printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/4/src/soc/qualcomm/qcs405/flash_contr… PS4, Line 82: printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/4/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29959/4/src/soc/qualcomm/qcs405/mmu.c@40 PS4, Line 40: mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 4 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Mon, 14 Jan 2019 15:27:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has uploaded a new patch set (#4) to the change originally created by nsekar(a)codeaurora.org. ( https://review.coreboot.org/c/coreboot/+/29957 ) Change subject: libpayload: Add UART for qcs405 ...................................................................... libpayload: Add UART for qcs405 TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.mistral M payloads/libpayload/drivers/Makefile.inc 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29957/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 4 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: binaryPI: Drop CONFIG_CBB and CONFIG_CDB
by Kyösti Mälkki (Code Review) 14 Jan '19

14 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30731 Change subject: binaryPI: Drop CONFIG_CBB and CONFIG_CDB ...................................................................... binaryPI: Drop CONFIG_CBB and CONFIG_CDB Static values, copy paste from multi-node fam15 code. Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 6 files changed, 15 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30731/1 diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index f3ed237..75a8441 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -23,14 +23,6 @@ int default 48 -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index d57cfb1..a6eca07 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -23,14 +23,6 @@ int default 48 -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index a455a3e..054523e 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -23,14 +23,6 @@ int default 40 -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 11158d0..db369b0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -104,7 +104,7 @@ static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); } static void get_fx_devs(void) @@ -147,7 +147,7 @@ static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -855,9 +855,9 @@ printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics)); - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(0x18, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0x0, 0x18); die(""); } sysconf_init(dev_mc); @@ -880,7 +880,7 @@ unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = 0x18 + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index d107964..a5bfac7 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -102,7 +102,7 @@ static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); } static void get_fx_devs(void) @@ -145,7 +145,7 @@ static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -844,9 +844,9 @@ ioapic_count = (int)options->CfgPlatNumIoApics; ASSERT(ioapic_count > 0); - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(0x18, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0x0, 0x18); die(""); } sysconf_init(dev_mc); @@ -869,7 +869,7 @@ unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = 0x18 + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8030a3f..ddaa94f 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -104,7 +104,7 @@ static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); } static void get_fx_devs(void) @@ -147,7 +147,7 @@ static u32 amdfam16_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -1090,9 +1090,9 @@ printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics); - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(0x18, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0x0, 0x18); die(""); } sysconf_init(dev_mc); @@ -1115,7 +1115,7 @@ unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = 0x18 + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Gerrit-Change-Number: 30731 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/x4x: Use parallel MP init
by HAOUAS Elyes (Code Review) 14 Jan '19

14 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25601 ) Change subject: nb/intel/x4x: Use parallel MP init ...................................................................... Patch Set 37: (2 comments) https://review.coreboot.org/#/c/25601/37/src/cpu/intel/model_f4x/model_f4x_… File src/cpu/intel/model_f4x/model_f4x_init.c: https://review.coreboot.org/#/c/25601/37/src/cpu/intel/model_f4x/model_f4x_… PS37, Line 16: #include <cpu/x86/mtrr.h> I think you can remove this include https://review.coreboot.org/#/c/25601/37/src/cpu/intel/model_f4x/model_f4x_… PS37, Line 18: #include <cpu/intel/microcode.h> : #include <cpu/intel/hyperthreading.h> here also -- To view, visit https://review.coreboot.org/c/coreboot/+/25601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921 Gerrit-Change-Number: 25601 Gerrit-PatchSet: 37 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 14 Jan 2019 15:10:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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