coreboot-gerrit January 2019

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Change in ...coreboot[master]: cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's
by Patrick Georgi (Code Review) 14 Jan '19

14 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30868 ) Change subject: cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/30868/1/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/30868/1/src/cpu/intel/smm/gen1/smmrelocate.… PS1, Line 79: /* Both model_6fx and model_1067x SMRR function slightly differently : from the rest. The MSR are at different location from the rest : and need to be explicitly enabled. */ move that comment to cpu_has_alternative_smrr -- To view, visit https://review.coreboot.org/c/coreboot/+/30868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa Gerrit-Change-Number: 30868 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Jan 2019 11:39:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/amd/south_station: Fix coding style
by HAOUAS Elyes (Code Review) 14 Jan '19

14 Jan '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/26466 ) Change subject: mainboard/amd/south_station: Fix coding style ...................................................................... Abandoned oops, sorry -- To view, visit https://review.coreboot.org/c/coreboot/+/26466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae457237ef104736478eface4d91dd282fd866ea Gerrit-Change-Number: 26466 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mainboard/amd/south_station: Fix coding style
by HAOUAS Elyes (Code Review) 14 Jan '19

14 Jan '19

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/26466 ) Change subject: mainboard/amd/south_station: Fix coding style ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/26466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae457237ef104736478eface4d91dd282fd866ea Gerrit-Change-Number: 26466 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in ...coreboot[master]: nb/intel/i945: Put stage cache in TSEG
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25603 ) Change subject: nb/intel/i945: Put stage cache in TSEG ...................................................................... Patch Set 37: (1 comment) https://review.coreboot.org/#/c/25603/37//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/25603/37//COMMIT_MSG@16 PS37, Line 16: > So was resume broken, or is it some preparation work? No this is simply a different and supposedly better place in ram to put the cached postcar stage and ramstage. Before those were put in cbmem, now in TSEG. -- To view, visit https://review.coreboot.org/c/coreboot/+/25603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da Gerrit-Change-Number: 25603 Gerrit-PatchSet: 37 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Jan 2019 11:18:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/kblrvp: Add new Kaby lake RVP11 support
by Arthur Heymans (Code Review) 14 Jan '19

14 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29809 ) Change subject: mb/intel/kblrvp: Add new Kaby lake RVP11 support ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id86f56df06795601cc9d7830766e54396d218e00 Gerrit-Change-Number: 29809 Gerrit-PatchSet: 15 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 14 Jan 2019 11:11:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] AGESA: Fix SMM support in ASEG
by Paul Menzel (Code Review) 14 Jan '19

14 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21624 ) Change subject: [WIP] AGESA: Fix SMM support in ASEG ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/21624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Gerrit-Change-Number: 21624 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Jan 2019 11:08:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: binaryPI: Drop invalid northbridge.h file
by Kyösti Mälkki (Code Review) 14 Jan '19

14 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30900 Change subject: binaryPI: Drop invalid northbridge.h file ...................................................................... binaryPI: Drop invalid northbridge.h file Pointless to declare static struct in a header. Change-Id: I757f6346017681e32900f67b25fb5700a68d86b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/amd/pi/00630F01/northbridge.c D src/northbridge/amd/pi/00630F01/northbridge.h M src/northbridge/amd/pi/00660F01/northbridge.c D src/northbridge/amd/pi/00660F01/northbridge.h M src/northbridge/amd/pi/00730F01/northbridge.c D src/northbridge/amd/pi/00730F01/northbridge.h 6 files changed, 0 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30900/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 11158d0..9ce811b 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -40,8 +40,6 @@ #include <northbridge/amd/pi/agesawrapper_call.h> #endif -#include "northbridge.h" - #define MAX_NODE_NUMS MAX_NODES typedef struct dram_base_mask { diff --git a/src/northbridge/amd/pi/00630F01/northbridge.h b/src/northbridge/amd/pi/00630F01/northbridge.h deleted file mode 100644 index 003fed1..0000000 --- a/src/northbridge/amd/pi/00630F01/northbridge.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H -#define NORTHBRIDGE_AMD_AGESA_FAM15H_H - -static struct device_operations pci_domain_ops; -static struct device_operations cpu_bus_ops; - -#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index d107964..696c653 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -38,7 +38,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #endif -#include "northbridge.h" #define MAX_NODE_NUMS MAX_NODES diff --git a/src/northbridge/amd/pi/00660F01/northbridge.h b/src/northbridge/amd/pi/00660F01/northbridge.h deleted file mode 100644 index e095f9a..0000000 --- a/src/northbridge/amd/pi/00660F01/northbridge.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H -#define NORTHBRIDGE_AMD_AGESA_FAM16H_H - -static struct device_operations pci_domain_ops; -static struct device_operations cpu_bus_ops; - -#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8030a3f..ebc1ca4 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -40,7 +40,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #endif -#include "northbridge.h" #define MAX_NODE_NUMS MAX_NODES diff --git a/src/northbridge/amd/pi/00730F01/northbridge.h b/src/northbridge/amd/pi/00730F01/northbridge.h deleted file mode 100644 index 4a42f6d..0000000 --- a/src/northbridge/amd/pi/00730F01/northbridge.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H -#define NORTHBRIDGE_AMD_AGESA_FAM16H_H - -static struct device_operations pci_domain_ops; -static struct device_operations cpu_bus_ops; - -#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I757f6346017681e32900f67b25fb5700a68d86b8 Gerrit-Change-Number: 30900 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: AGESA: Remove ACPI for IMC we don't run
by Paul Menzel (Code Review) 14 Jan '19

14 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18536 ) Change subject: AGESA: Remove ACPI for IMC we don't run ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/18536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae21e0294f0155f07fb4f4348ebc5b3120d50fd1 Gerrit-Change-Number: 18536 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Jan 2019 10:56:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Put stage cache in TSEG
by Paul Menzel (Code Review) 14 Jan '19

14 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25603 ) Change subject: nb/intel/i945: Put stage cache in TSEG ...................................................................... Patch Set 37: (1 comment) https://review.coreboot.org/#/c/25603/37//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/25603/37//COMMIT_MSG@16 PS37, Line 16: So was resume broken, or is it some preparation work? -- To view, visit https://review.coreboot.org/c/coreboot/+/25603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da Gerrit-Change-Number: 25603 Gerrit-PatchSet: 37 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Jan 2019 10:55:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mainboard/pcengines/apu1: Enable LPC TPM
by Paul Menzel (Code Review) 14 Jan '19

14 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30354 ) Change subject: src/mainboard/pcengines/apu1: Enable LPC TPM ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd Gerrit-Change-Number: 30354 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 14 Jan 2019 10:54:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2019