coreboot-gerrit January 2019

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Change in ...coreboot[master]: util/superiotool: Add ITE8528
by Kyösti Mälkki (Code Review) 14 Jan '19

14 Jan '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30801 ) Change subject: util/superiotool: Add ITE8528 ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b12c0032157a4959336f8b51dadbe7b2e09d66 Gerrit-Change-Number: 30801 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 14 Jan 2019 09:50:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/superiotool: Add ITE8528
by Patrick Rudolph (Code Review) 14 Jan '19

14 Jan '19

Hello Felix Held, Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30801 to look at the new patch set (#5). Change subject: util/superiotool: Add ITE8528 ...................................................................... util/superiotool: Add ITE8528 Add ITE8528 which can be found on the wedge100s. Most registers are dumped from hardware. No datasheet is publicy available. Change-Id: I24b12c0032157a4959336f8b51dadbe7b2e09d66 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/superiotool/ite.c M util/superiotool/superiotool.h 2 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30801/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/30801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b12c0032157a4959336f8b51dadbe7b2e09d66 Gerrit-Change-Number: 30801 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()
by Patrick Rudolph (Code Review) 14 Jan '19

14 Jan '19

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30828 ) Change subject: soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry() ...................................................................... soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry() Move early_mainboard_romstage_entry before console_init. Allows to setup a SuperIO, if any, for serial console. Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/30828 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/ocp/wedge100s/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 2 files changed, 6 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index 1d77036..9e294d9 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -40,6 +40,7 @@ */ msr_t msr = rdmsr(IA32_FEATURE_CONTROL); if (msr.lo & 1) { + console_init(); printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); full_reset(); } diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 003ae22..8ddca26 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -68,14 +68,16 @@ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_EN, 0x340f); } - console_init(); - init_rtc(); - setup_gpio_io_address(); /* Call into mainboard. */ post_code(0x41); early_mainboard_romstage_entry(); + post_code(0x42); + console_init(); + init_rtc(); + setup_gpio_io_address(); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB -- To view, visit https://review.coreboot.org/c/coreboot/+/30828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247 Gerrit-Change-Number: 30828 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()
by Patrick Rudolph (Code Review) 14 Jan '19

14 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30828 ) Change subject: soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry() ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/30828/1/src/soc/intel/fsp_broadwell_de/roms… File src/soc/intel/fsp_broadwell_de/romstage/romstage.c: https://review.coreboot.org/#/c/30828/1/src/soc/intel/fsp_broadwell_de/roms… PS1, Line 69: LPC_EN, 0x340f); > Not the scope of the patch, but perhaps these should be read-modify-writes instead of wiping out pre […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/30828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247 Gerrit-Change-Number: 30828 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Jan 2019 09:13:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel/fsp1_0: Add option to select FSP debug level
by Patrick Rudolph (Code Review) 14 Jan '19

14 Jan '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30741 Change subject: intel/fsp1_0: Add option to select FSP debug level ...................................................................... intel/fsp1_0: Add option to select FSP debug level Useful for debugging FSP. Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp1_0/Kconfig M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/30741/1 diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index c7f6c18..de26782 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -41,6 +41,16 @@ help The path and filename of the Intel FSP binary for this platform. +config FSP_1_0_DEBUG_LEVEL + int "FSP debug level (0-3)" + default 0 + help + Select the debug level, where: + 0: DISABLED + 1: MINIMUM + 2: NORMAL + 3: MAXIMUM + endif #HAVE_FSP_BIN config FSP_LOC diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 578a0d0..7e00338 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -76,6 +76,8 @@ UpdData->SerialPortConfigure = 0; } + UpdData->DebugOutputLevel = CONFIG_FSP_1_0_DEBUG_LEVEL; + /* * Memory Down */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526 Gerrit-Change-Number: 30741 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/ocp/wedge100s: Disable internal uart
by Patrick Rudolph (Code Review) 14 Jan '19

14 Jan '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30706 Change subject: mb/ocp/wedge100s: Disable internal uart ...................................................................... mb/ocp/wedge100s: Disable internal uart Fix romstage serial console by disabling internal uart default setting. That redirects the uart to the LPC ITE superio. Tested on wedge100s. Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/wedge100s/Kconfig 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30706/1 diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index 5d4349d..18251c9 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -37,7 +37,7 @@ default 0x1000000 config DRIVERS_UART_8250IO - def_bool n + def_bool y config FSP_PACKAGE_DEFAULT bool "Configure defaults for the Intel FSP package" @@ -47,4 +47,7 @@ string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" +config INTEGRATED_UART + def_bool n + endif # BOARD_OCP_WEDGE100S -- To view, visit https://review.coreboot.org/c/coreboot/+/30706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b Gerrit-Change-Number: 30706 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: 2nd version, reworked based on Asus P8H61-M LX as a template and the ...
by Balázs Vinarz (Code Review) 14 Jan '19

14 Jan '19

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30896 Change subject: 2nd version, reworked based on Asus P8H61-M LX as a template and the old wiki ...................................................................... 2nd version, reworked based on Asus P8H61-M LX as a template and the old wiki Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com> Change-Id: I35fdc87fe167c6c6ca605860aa4914d39407546f --- A Documentation/mainboard/asus/f2a85-m.md 1 file changed, 271 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30896/1 diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md new file mode 100644 index 0000000..c4ee0cf --- /dev/null +++ b/Documentation/mainboard/asus/f2a85-m.md @@ -0,0 +1,271 @@ +Disclaimer: This board is not widely sold any longer. However, refer to F2A85 series status for newer models. ASUS F2A85 PRO should be work in progress (WIP). +Contents + + 1 Status + 1.1 Supported processing units + 1.1.1 CPUs + 1.1.2 APUs + 1.2 Notes + 1.3 TODOs + 2 UEFI builds that allow flash chip access + 3 Hardware info + 3.1 DDR voltage controller + 3.2 The ASUS digi VRM + 3.3 Memory + 4 See also + 4.1 F2A85 series status + 5 References + +Status +Device/functionality Status Comments +CPU +CPU works OK the board will start with an AMD A8-5500 +L1 cache enabled OK +L2 cache enabled OK +L3 cache enabled N/A +Multiple CPU support OK +Multi-core support OK +Hardware virtualization Untested +RAM +EDO N/A +SDRAM N/A +SO-DIMM N/A +DDR N/A +DDR2 N/A +DDR3 OK Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less! +Dual channel support OK +ECC support N/A +On-board Hardware +On-board IDE 3.5" N/A +On-board IDE 2.5" N/A +On-board SATA OK Tested all ports of sixpack. +On-board SCSI N/A +On-board USB OK Issues with XHCI exist with Asus' BIOS as well +On-board VGA OK Use dd to extract the legacy BIOS, HDMI untested +On-board Ethernet OK +On-board Audio OK tested with headphones in line-out (lime colored) +On-board Modem N/A +On-board FireWire N/A +On-board Smartcard reader N/A +On-board CompactFlash N/A +On-board PCMCIA N/A +On-board Wifi N/A +On-board Bluetooth N/A +On-board SD card reader N/A +Add-on slots/cards +ISA add-on cards N/A +Audio/Modem-Riser (AMR/CNR) cards N/A +PCI add-on cards OK +Mini-PCI add-on cards N/A +Mini-PCI-Express add-on cards Unknown +PCI-X add-on cards N/A +AGP graphics cards N/A +PCI Express x1 add-on cards OK +PCI Express x2 add-on cards N/A +PCI Express x4 add-on cards OK +PCI Express x8 add-on cards N/A +PCI Express x16 add-on cards OK +PCI Express x32 add-on cards N/A +HTX add-on cards N/A +Legacy / Super I/O +Floppy N/A +Serial port 1 (COM1) OK +Serial port 2 (COM2) N/A +Parallel port N/A +PS/2 keyboard OK +PS/2 mouse Untested +Game port N/A +Infrared ? +PC speaker OK +DiskOnChip N/A +Input +Trackpoint N/A +Touchpad N/A +Fn Hotkeys N/A +Fingerprint Reader N/A +Laptop +Docking VGA N/A +Docking LAN N/A +Docking USB N/A +Docking Audio N/A +Docking Displayport N/A +Thinklight N/A +Webcam N/A +Miscellaneous +Sensors / fan control Untested +Hardware watchdog Unknown +SMBus Unknown +CAN bus N/A +CPU frequency scaling OK +Other powersaving features ? +ACPI OK ACPI power button event works, suspend is WIP (work in progress). +Reboot OK warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot +Poweroff OK +Suspend OK +Nonstandard LEDs OK +High precision event timers (HPET) OK +Random number generator (RNG) ? +Wake on modem ring Untested +Wake on LAN Untested +Wake on keyboard Untested +Wake on mouse Untested +TPM Unknown +Flashrom OK +Supported processing units + +ASUS F2A85-M CPU specification:[1] + + AMD Socket FM2 Athlon�/A- Series Processors + Supports CPU up to 4 cores + Supports AMD� Turbo Core 3.0 Technology + Addenum: AMD Sempron X2 250[2] + +Note: Only AMD Virgo: "Trinity" desktop processing units are supported (see list below) but with a hack also Richland desktop processing units might work (contact via mailing list for details). Wikipedia's list of Trinity processors might be more actively maintained. +CPUs + + AMD Athlon X2 340 + AMD Athlon X4 740 + AMD Athlon X4 750k + +APUs + +The CPU architecture in these APUs are Piledriver, and their GPU is TeraScale 3 (VLIW4-based). + + AMD A4-5300 + AMD A4-5300B + AMD A6-5400K + AMD A6-5400B + AMD A8-5500 + AMD A8-5500B + AMD A8-5600K + AMD A10-5700 + AMD A10-5800B + AMD A10-5800K + AMD FirePro A300 - Only sold by OEM + AMD FirePro A320 - Only sold by OEM + +Notes + + Retrieve the VGA optionrom from the vendor EFI binary by running: + +dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768 + +(source) + +For internal VGA: Boot the legacy BIOS, and use VGA_support chapter + + Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID. + If you use PS/2 de-select legacy free + De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios + It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read SeaBIOS for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload. + its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings: + CONFIG_VGA_ROM_RUN=y + CONFIG_PCI_ROM_RUN=y + CONFIG_ON_DEVICE_ROM_RUN=y + Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues. + +TODOs + + test virtualization + test IOMMU + test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested. + blink in suspend mode (GP43, program LDN7 F8=23 and blink with F9=2 for 1s blinks) + fix mptable + fix resume with USB3.0 used (perhaps there is a bug in resume.c) + fix immediate resume after suspend (perhaps PCIe STS needs to be cleared) + +UEFI builds that allow flash chip access + + v5016 is untested, but expected to work as well + v5018 + v5103 + v5104 + v5107 + v5202 + v6002 + v6004 + v6102 + v6402 + v6404 (requires downgrading to v6402 to flash coreboot) + v6501 (requires downgrading to v6402 to flash coreboot) + v6502 (requires downgrading to v6402 to flash coreboot) + +Build v6502, v6501 and v6404 do not allow access to the flash chip. + +Fortunately it is possible to downgrade build v6502, v6501 and v6404 to v6402, with EZFlash. + +Downgrading is done by downloading build v6402 from ASUS' F2A85-M download page and copying it to (the root directory of) a FAT32 formatted USB flash drive. + +Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility". +Hardware info + +This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package: +Winbond 25Q64F + +The chip manual is available here + +For out of band flashing, I use a + + 3M test clip model 923739-08-ND + +It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever: + +\# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom +flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64) +flashrom is free software, get the source code at http://www.flashrom.org + +Calibrating delay loop... OK. +Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... Erase/write done. +Verifying flash... VERIFIED. + +real 35m35.409s +user 0m55.976s +sys 0m12.920s + +DDR voltage controller + +The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website). +The ASUS digi VRM + +The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded) +Memory + +If you use single dimm plug it to DIMM_A2 or DIMM_B2. + +I use: + +2x 2GB DDR3 modules in blue slots: + +\#modprobe i2c-piix4 +\#modprobe eeprom +\#decode-dimms + +---=== Memory Characteristics ===--- +Fine time base 2.500 ps +Medium time base 0.125 ns +Maximum module speed 1333MHz (PC3-10666) +Size 2048 MB +Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 +Ranks 2 +SDRAM Device Width 8 bits +tCL-tRCD-tRP-tRAS 8-8-8-24 +Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T + +See also +F2A85 series status + +Only boards with internal wiki page links are Supported Motherboards. + + ASUS F2A85-M + ASUS F2A85-M LE + ASUS F2A85-M PRO[3] - the most available model in the entire F2A85 series. Be sure to check its status to see what works and what doesn't. + ASUS F2A85-M2 - Confirmed working in the #coreboot IRC channel 2015-03-04. Unsure if WIP. + ASUS F2A85-M/CSM - Unsure if WIP. + +References + + Jump up ↑ https://www.asus.com/Motherboards/F2A85M/specifications/ + Jump up ↑ http://support.asus.com/Cpusupport/List.aspx?SLanguage=en&m=F2A85-M&p=1&s=43 + Jump up ↑ http://www.asus.com/Motherboards/F2A85M_PRO/ -- To view, visit https://review.coreboot.org/c/coreboot/+/30896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35fdc87fe167c6c6ca605860aa4914d39407546f Gerrit-Change-Number: 30896 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/ocp/wedge100s: Fix uart
by Patrick Rudolph (Code Review) 14 Jan '19

14 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30827 ) Change subject: mainboard/ocp/wedge100s: Fix uart ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/30827/1/src/mainboard/ocp/wedge100s/romstag… File src/mainboard/ocp/wedge100s/romstage.c: https://review.coreboot.org/#/c/30827/1/src/mainboard/ocp/wedge100s/romstag… PS1, Line 77: if (IS_ENABLED(CONFIG_FSP_USES_UPD)) { > What is this??? it makes FspRtBuffer.Common.UpdDataRgnPtr non NULL. https://review.coreboot.org/#/c/30827/1/src/mainboard/ocp/wedge100s/romstag… PS1, Line 96: } > yeah, moving this to the common code and making it dependent on !CONFIG_INTEGRATED_UART would be a g […] That should probably be configured in common code depending on devicetree.cb. I don't like the CONFIG_INTEGRATED_UART option. I'll do the cleanup in a separate commit, as this one only makes the serial work on wedge100s. -- To view, visit https://review.coreboot.org/c/coreboot/+/30827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59cd83ed43dbf4ee26685e4a573de153291f7074 Gerrit-Change-Number: 30827 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrea Barberio <insomniac(a)slackware.it> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 14 Jan 2019 08:55:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 14 Jan '19

14 Jan '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 33: (2 comments) > Patch Set 33: > > (1 comment) > > The more I'm thinking about this the more I realize that I don't > understand the purpose of this update mechanism. > > For being able to perform the update, you already need a RO MCU that > works good enough to get you to ramstage. At this point, you can > already apply additional MCUs from any RW partition. So what kind of > issue would have to be fixed by an update that makes use of this > mechanism? > > In other words, what problem can this new update mechanism fix, that > current mechanisms can't? And is it worth the added complexity and > accompanying security degradation (more code is always more error- > prone)? Microcode patch contains patch for Punit as well, and that has to be applied prior to reset. Hence the effort to load the updated microcode via FIT. https://review.coreboot.org/#/c/27369/30//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27369/30//COMMIT_MSG@10 PS30, Line 10: them > microcode updates. Done https://review.coreboot.org/#/c/27369/30//COMMIT_MSG@22 PS30, Line 22: I > Added an option to cbfs tool to do that. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 33 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 14 Jan 2019 08:01:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/eltan: Add vendor code for measured and verified boot
by Frans Hendriks (Code Review) 14 Jan '19

14 Jan '19

Hello Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30218 to look at the new patch set (#8). Change subject: vendorcode/eltan: Add vendor code for measured and verified boot ...................................................................... vendorcode/eltan: Add vendor code for measured and verified boot This patch contains the general files for the vendorcode/eltan that has been uploaded recently: - Add maintainer for the vendorcode - Add eltan directory to vendorcode - Add documentation about the support in the vendorcode directories. - Add the Makefile.inc and Kconfig for the vendorcode/eltan and vendorcode/eltan/security BUG=N/A TEST=Created verified binary and verify logging on Portwell PQ-M107 Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A Documentation/vendorcode/eltan/index.md A Documentation/vendorcode/eltan/security.md M MAINTAINERS M src/vendorcode/Makefile.inc A src/vendorcode/eltan/Kconfig A src/vendorcode/eltan/Makefile.inc A src/vendorcode/eltan/security/Kconfig A src/vendorcode/eltan/security/Makefile.inc 8 files changed, 132 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30218/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/30218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80 Gerrit-Change-Number: 30218 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2019