Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17656 )
Change subject: buildsystem: Promote rules.h to default include
......................................................................
Patch Set 10: Code-Review+2
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Angel Pons has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/29565 )
Change subject: lenovo/h8,thinkpads: Re-do USB Always On
......................................................................
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Angel Pons has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/26863 )
Change subject: vboot: Fix linking error with USE_OPTION_TABLE enabled
......................................................................
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Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29917
to look at the new patch set (#22).
Change subject: src: Fix - Remove unused variables
......................................................................
src: Fix - Remove unused variables
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/quadcore/quadcore.c
M src/device/dram/ddr3.c
M src/drivers/spi/sst.c
M src/lib/selfboot.c
M src/northbridge/amd/amdmct/mct/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/haswell/raminit.c
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/x4x/dq_dqs.c
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/via/vx900/raminit_ddr3.c
M src/soc/cavium/common/bootblock.c
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/acpi.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/amd/common/amd_pci_util.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/i82371eb/fadt.c
21 files changed, 51 insertions(+), 87 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/22
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Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29917
to look at the new patch set (#21).
Change subject: src: Fix unused variables
......................................................................
src: Fix unused variables
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/quadcore/quadcore.c
M src/device/dram/ddr3.c
M src/drivers/spi/sst.c
M src/lib/selfboot.c
M src/northbridge/amd/amdmct/mct/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/haswell/raminit.c
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/x4x/dq_dqs.c
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/via/vx900/raminit_ddr3.c
M src/soc/cavium/common/bootblock.c
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/acpi.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/amd/common/amd_pci_util.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/i82371eb/fadt.c
21 files changed, 51 insertions(+), 87 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/21
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28971 )
Change subject: src/superio/smsc/smscsuperio/superio.c: Add SCH5504
......................................................................
Patch Set 3:
> Patch Set 1: Code-Review+1
>
> looks good to me; I'd like to wait with +2ing this until there is a patch adding mainboard with this superio in the review system though
Tested with dell/gx520, serial port works for logging stuff. The mainboard is not merged yet, however.
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25603 )
Change subject: nb/intel/i945: Put stage cache in TSEG
......................................................................
Patch Set 37: Code-Review+1
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30801 )
Change subject: util/superiotool: Add ITE8528
......................................................................
Patch Set 5: Code-Review+2
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