coreboot-gerrit September 2018

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Change in coreboot[master]: riscv: add physical memory protection (PMP) support
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28569 ) Change subject: riscv: add physical memory protection (PMP) support ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c File src/arch/riscv/pmp.c: https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c@24 PS4, Line 24: /* trailing whitespace https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c@32 PS4, Line 32: * When generating a TOR type configuration, code indent should use tabs where possible https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c@34 PS4, Line 34: * used to record the value of pmpaddr[i - 1] trailing whitespace https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c@35 PS4, Line 35: */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/28569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Gerrit-Change-Number: 28569 Gerrit-PatchSet: 4 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Sep 2018 14:23:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: temporarily block multiple-threads
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27358 ) Change subject: riscv: temporarily block multiple-threads ...................................................................... Patch Set 28: (4 comments) https://review.coreboot.org/#/c/27358/28/src/arch/riscv/include/arch/smp/sm… File src/arch/riscv/include/arch/smp/smp.h: https://review.coreboot.org/#/c/27358/28/src/arch/riscv/include/arch/smp/sm… PS28, Line 62: if (arrived > 1) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/27358/28/src/arch/riscv/include/arch/smp/sm… PS28, Line 66: while (bar->wait[gen] == 0) ; space prohibited before semicolon https://review.coreboot.org/#/c/27358/28/src/arch/riscv/include/arch/smp/sm… PS28, Line 66: while (bar->wait[gen] == 0) ; trailing statements should be on next line https://review.coreboot.org/#/c/27358/28/src/arch/riscv/include/arch/smp/sm… PS28, Line 68: if (atomic_fetch_add(&(bar->entered[gen]), -1) == 1) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia0eeed51e0952c66a9a9f25a90105fe471ffa70e Gerrit-Change-Number: 27358 Gerrit-PatchSet: 28 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 11 Sep 2018 09:37:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add physical memory protection(PMP) support
by Xiang Wang (Code Review) 11 Sep '18

11 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28569 to look at the new patch set (#3). Change subject: riscv: add physical memory protection(PMP) support ...................................................................... riscv: add physical memory protection(PMP) support Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/arch/riscv/include/arch/pmp.h A src/arch/riscv/pmp.c 2 files changed, 340 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28569/3 -- To view, visit https://review.coreboot.org/28569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Gerrit-Change-Number: 28569 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add physical memory protection(PMP) support
by Xiang Wang (Code Review) 11 Sep '18

11 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28569 to look at the new patch set (#2). Change subject: riscv: add physical memory protection(PMP) support ...................................................................... riscv: add physical memory protection(PMP) support Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/arch/riscv/include/arch/pmp.h A src/arch/riscv/pmp.c 2 files changed, 340 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28569/2 -- To view, visit https://review.coreboot.org/28569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Gerrit-Change-Number: 28569 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add physical memory protection(PMP) support
by Xiang Wang (Code Review) 11 Sep '18

11 Sep '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28569 Change subject: riscv: add physical memory protection(PMP) support ...................................................................... riscv: add physical memory protection(PMP) support Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/arch/riscv/include/arch/pmp.h A src/arch/riscv/pmp.c 2 files changed, 342 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28569/1 diff --git a/src/arch/riscv/include/arch/pmp.h b/src/arch/riscv/include/arch/pmp.h new file mode 100644 index 0000000..bac8e9d --- /dev/null +++ b/src/arch/riscv/include/arch/pmp.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __RISCV_PMP_H__ +#define __RISCV_PMP_H__ + +/* this function needs to be implemented by a specific SoC. + * return number of pmp entries for current hart */ +extern int pmp_entries_num(void); + +/* reset PMP setting */ +void reset_pmp(void); + +/* this function used to setup pmp record */ +void setup_pmp(uintptr_t base, uintptr_t size, uintptr_t flags); + +#endif /* __RISCV_PMP_H__ */ + diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c new file mode 100644 index 0000000..c4ee8d3 --- /dev/null +++ b/src/arch/riscv/pmp.c @@ -0,0 +1,312 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/encoding.h> +#include <stdint.h> +#include <arch/pmp.h> +#include <console/console.h> + +#define GRANULE (1 << PMP_SHIFT) +#define IS2POW(n) ((n != 0) && ((n & (n - 1)) == 0)) + +/* This structure is used to temporarily record PMP + * configuration information. */ +typedef struct { + /* used to record the value of pmpcfg[i] */ + uintptr_t cfg; + /* When generating a TOR type configuration, + * the previous entry needs to record the starting address. + * used to record the value of pmpaddr[i - 1] */ + uintptr_t before_address; + /* used to record the value of pmpaddr[i] */ + uintptr_t address; +} pmpcfg_t; + +/* This variable is used to record which entries have been used. */ +static uintptr_t pmp_entry_used_mask; + +/* helper function used to read pmpcfg[idx] */ +static uintptr_t read_pmpcfg(int idx) +{ +#if __riscv_xlen == 32 + int shift = 8 * (idx & 3); + switch (idx >> 2) { + case 0: + return (read_csr(pmpcfg0) >> shift) & 0xff; + case 1: + return (read_csr(pmpcfg1) >> shift) & 0xff; + case 2: + return (read_csr(pmpcfg2) >> shift) & 0xff; + case 3: + return (read_csr(pmpcfg3) >> shift) & 0xff; + } +#elif __riscv_xlen == 64 + int shift = 8 * (idx & 7); + switch (idx >> 3) { + case 0: + return (read_csr(pmpcfg0) >> shift) & 0xff; + case 1: + return (read_csr(pmpcfg2) >> shift) & 0xff; + } +#endif + return -1; +} + + +/* helper function used to write pmpcfg[idx] */ +static void write_pmpcfg(int idx, uintptr_t cfg) +{ + uintptr_t old; + uintptr_t new; +#if __riscv_xlen == 32 + int shift = 8 * (idx & 3); + switch (idx >> 2) { + case 0: + old = read_csr(pmpcfg0); + new = (old & ~(0xff << shift)) | ((cfg & 0xff) << shift); + write_csr(pmpcfg0, new); + break; + case 1: + old = read_csr(pmpcfg1); + new = (old & ~(0xff << shift)) | ((cfg & 0xff) << shift); + write_csr(pmpcfg1, new); + break; + case 2: + old = read_csr(pmpcfg2); + new = (old & ~(0xff << shift)) | ((cfg & 0xff) << shift); + write_csr(pmpcfg2, new); + break; + case 3: + old = read_csr(pmpcfg3); + new = (old & ~(0xff << shift)) | ((cfg & 0xff) << shift); + write_csr(pmpcfg3, new); + break; + } +#elif __riscv_xlen == 64 + int shift = 8 * (idx & 7); + switch (idx >> 3) { + case 0: + old = read_csr(pmpcfg0); + new = (old & ~(0xff << shift)) | ((cfg & 0xff) << shift); + write_csr(pmpcfg0, new); + break; + case 1: + old = read_csr(pmpcfg2); + new = (old & ~(0xff << shift)) | ((cfg & 0xff) << shift); + write_csr(pmpcfg2, new); + break; + } +#endif +} + +/* helper function used to read pmpaddr[idx] */ +/* +static uintptr_t read_pmpaddr(int idx) +{ + switch(idx) { + case 0: + return read_csr(pmpaddr0); + case 1: + return read_csr(pmpaddr1); + case 2: + return read_csr(pmpaddr2); + case 3: + return read_csr(pmpaddr3); + case 4: + return read_csr(pmpaddr4); + case 5: + return read_csr(pmpaddr5); + case 6: + return read_csr(pmpaddr6); + case 7: + return read_csr(pmpaddr7); + case 8: + return read_csr(pmpaddr8); + case 9: + return read_csr(pmpaddr9); + case 10: + return read_csr(pmpaddr10); + case 11: + return read_csr(pmpaddr11); + case 12: + return read_csr(pmpaddr12); + case 13: + return read_csr(pmpaddr13); + case 14: + return read_csr(pmpaddr14); + case 15: + return read_csr(pmpaddr15); + } +} +*/ + +/* helper function used to write pmpaddr[idx] */ +static void write_pmpaddr(int idx, uintptr_t val) +{ + switch (idx) { + case 0: + write_csr(pmpaddr0, val); + break; + case 1: + write_csr(pmpaddr1, val); + break; + case 2: + write_csr(pmpaddr2, val); + break; + case 3: + write_csr(pmpaddr3, val); + break; + case 4: + write_csr(pmpaddr4, val); + break; + case 5: + write_csr(pmpaddr5, val); + break; + case 6: + write_csr(pmpaddr6, val); + break; + case 7: + write_csr(pmpaddr7, val); + break; + case 8: + write_csr(pmpaddr8, val); + break; + case 9: + write_csr(pmpaddr9, val); + break; + case 10: + write_csr(pmpaddr10, val); + break; + case 11: + write_csr(pmpaddr11, val); + break; + case 12: + write_csr(pmpaddr12, val); + break; + case 13: + write_csr(pmpaddr13, val); + break; + case 14: + write_csr(pmpaddr14, val); + break; + case 15: + write_csr(pmpaddr15, val); + break; + } +} + + +/* Generate a pmp configuration of type NA4/NAPOT */ +static pmpcfg_t generate_pmp_napot( + uintptr_t base, uintptr_t size, uintptr_t flags) +{ + pmpcfg_t p; + flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L); + p.cfg = flags | (size > GRANULE ? PMP_NAPOT : PMP_NA4); + p.before_address = 0; + p.address = (base + (size / 2 - 1)) >> PMP_SHIFT; + return p; +} + + +/* Generate a pmp configuration of type TOR */ +static pmpcfg_t generate_pmp_range( + uintptr_t base, uintptr_t size, uintptr_t flags) +{ + pmpcfg_t p; + flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L); + p.cfg = flags | PMP_TOR; + p.before_address = base >> PMP_SHIFT; + p.address = (base + size) >> PMP_SHIFT; + return p; +} + + +/* Generate a pmp configuration */ +static pmpcfg_t generate_pmp(uintptr_t base, uintptr_t size, uintptr_t flags) +{ + if (IS2POW(size) && (size >= 4) && ((base & (size - 1)) == 0)) + return generate_pmp_napot(base, size, flags); + else + return generate_pmp_range(base, size, flags); +} + + + +/* find empty pmp entry by type + * TOR type configuration requires two consecutive PMP entries, + * others requires one. */ +static int find_empty_pmp_entry(int is_range) +{ + int status = 0; + for (int i = 0; i < pmp_entries_num(); i++) { + if (pmp_entry_used_mask & (1 << i)) + status = 0; + else + status++; + if (is_range && (status == 2)) + return i; + if (!is_range && (status == 1)) + return i; + } + die("Too many pmp configurations, no free entries can be used!"); + return -1; +} + +/* mark pmp entry has be used + * this function need be used with find_entry_pmp_entry + * + * n = find_empty_pmp_entry(is_range) + * ... // pmp set operate + * mask_pmp_entry_used(n, is_range); + */ +static void mask_pmp_entry_used(int idx, int is_range) +{ + pmp_entry_used_mask |= 1 << idx; + if (is_range) + pmp_entry_used_mask |= 1 << (idx - 1); +} + +/* reset PMP setting */ +void reset_pmp(void) +{ + for (int i = 0; i < pmp_entries_num(); i++) { + if (read_pmpcfg(i) & PMP_L) + die("Some PMP configurations are locked " + "and cannot be reset!"); + write_pmpcfg(i, 0); + write_pmpaddr(i, 0); + } +} + +/* this function used to setup pmp record */ +void setup_pmp(uintptr_t base, uintptr_t size, uintptr_t flags) +{ + pmpcfg_t p; + int is_range, n; + + p = generate_pmp(base, size, flags); + is_range = ((p.cfg & PMP_A) == PMP_TOR); + + n = find_empty_pmp_entry(is_range); + + write_pmpaddr(n, p.address); + if (is_range) + write_pmpaddr(n - 1, p.before_address); + write_pmpcfg(n, p.cfg); + + mask_pmp_entry_used(n, is_range); +} + -- To view, visit https://review.coreboot.org/28569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Gerrit-Change-Number: 28569 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: [WIP] new board: Dell Latitude E6230
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22693 ) Change subject: [WIP] new board: Dell Latitude E6230 ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/22693/4/src/mainboard/dell/latitude_e6230/e… File src/mainboard/dell/latitude_e6230/ec.c: https://review.coreboot.org/#/c/22693/4/src/mainboard/dell/latitude_e6230/e… PS4, Line 89: static int write_send(u8 *sdata, u8 c, unsigned count) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/22693/4/src/mainboard/dell/latitude_e6230/r… File src/mainboard/dell/latitude_e6230/romstage.c: https://review.coreboot.org/#/c/22693/4/src/mainboard/dell/latitude_e6230/r… PS4, Line 25: pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); line over 80 characters -- To view, visit https://review.coreboot.org/22693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8cdc01e902e670310628809416290045c2102340 Gerrit-Change-Number: 22693 Gerrit-PatchSet: 4 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Sep 2018 07:49:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy: Set UPD CmdTriStateDis for rammus
by Marx Wang (Code Review) 11 Sep '18

11 Sep '18

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/28568 Change subject: mb/google/poppy: Set UPD CmdTriStateDis for rammus ...................................................................... mb/google/poppy: Set UPD CmdTriStateDis for rammus This patch sets the MRC UPD CmdTriStateDis for the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL BUG=none TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236 Signed-off-by: marxwang <marx.wang(a)intel.com> --- M src/mainboard/google/poppy/variants/rammus/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28568/1 diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 7c1b02f..f94b30d 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -27,6 +27,9 @@ # Enable S0ix register "s0ix_enable" = "1" + # Disable Command TriState + register "CmdTriStateDis" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" -- To view, visit https://review.coreboot.org/28568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236 Gerrit-Change-Number: 28568 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com>

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Change in coreboot[master]: soc/sifive/fu540: Makefile: include mtime_init in ramstage
by Xiang Wang (Code Review) 11 Sep '18

11 Sep '18

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/28551 ) Change subject: soc/sifive/fu540: Makefile: include mtime_init in ramstage ...................................................................... Patch Set 5: Code-Review+1 > @Xiang This fixes a compilation issue that appeared due to your 2 > CR that have been merged. > Does my fix look ok to you? Yes, This is OK! Thank you! -- To view, visit https://review.coreboot.org/28551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Gerrit-Change-Number: 28551 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Sep 2018 00:25:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27602 ) Change subject: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/27602/11/src/northbridge/amd/pi/00730F01/no… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/27602/11/src/northbridge/amd/pi/00730F01/no… PS11, Line 629: printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/27602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Gerrit-Change-Number: 27602 Gerrit-PatchSet: 11 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 10 Sep 2018 23:24:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/amd/pi/00730F01: Add initial native IVRS support
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15164 ) Change subject: nb/amd/pi/00730F01: Add initial native IVRS support ...................................................................... Patch Set 24: (9 comments) https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 488: unsigned int depth, int linknum, int8_t *root_level, line over 80 characters https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 511: add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x97); line over 80 characters https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 517: add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); line over 80 characters https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 521: is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); line over 80 characters https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 526: add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); line over 80 characters https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 527: } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && line over 80 characters https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 529: add_ivhd_dev_entry(parent, dev, current, length, 0x42, 0x0); line over 80 characters https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 589: printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); line over 80 characters https://review.coreboot.org/#/c/15164/24/src/northbridge/amd/pi/00730F01/no… PS24, Line 590: printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/15164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Gerrit-Change-Number: 15164 Gerrit-PatchSet: 24 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 10 Sep 2018 23:23:54 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018