coreboot-gerrit September 2018

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Change in coreboot[master]: nb/intel/x4x: Program read training results to all ranks
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28577 ) Change subject: nb/intel/x4x: Program read training results to all ranks ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/28577/3/src/northbridge/intel/x4x/dq_dqs.c File src/northbridge/intel/x4x/dq_dqs.c: https://review.coreboot.org/#/c/28577/3/src/northbridge/intel/x4x/dq_dqs.c@… PS3, Line 524: /* Later on separate settings for each rank are used so program line over 80 characters -- To view, visit https://review.coreboot.org/28577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7965a068ef4779847e62e966154764370c91302a Gerrit-Change-Number: 28577 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Sep 2018 21:35:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/x4x: Program read training results to all ranks
by Arthur Heymans (Code Review) 11 Sep '18

11 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28577 to look at the new patch set (#3). Change subject: nb/intel/x4x: Program read training results to all ranks ...................................................................... nb/intel/x4x: Program read training results to all ranks While during the read training itself only the settings for rank 0 are used for all ranks, the controller does use the separate settings for each rank later on. It is unknown which register is responsible for this. Therefore program the results for all ranks. TESTED: Fixes DG43GT not booting with only the second DIMM slot of a channel populated. Change-Id: I7965a068ef4779847e62e966154764370c91302a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/dq_dqs.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28577/3 -- To view, visit https://review.coreboot.org/28577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7965a068ef4779847e62e966154764370c91302a Gerrit-Change-Number: 28577 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/x4x: Program read training results to all ranks
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28577 ) Change subject: nb/intel/x4x: Program read training results to all ranks ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28577/2/src/northbridge/intel/x4x/dq_dqs.c File src/northbridge/intel/x4x/dq_dqs.c: https://review.coreboot.org/#/c/28577/2/src/northbridge/intel/x4x/dq_dqs.c@… PS2, Line 503: /* Later on separate settings for each rank are used so program line over 80 characters -- To view, visit https://review.coreboot.org/28577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7965a068ef4779847e62e966154764370c91302a Gerrit-Change-Number: 28577 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Sep 2018 21:35:20 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/x4x: Program read training results to all ranks
by Arthur Heymans (Code Review) 11 Sep '18

11 Sep '18

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/28577 ) Change subject: nb/intel/x4x: Program read training results to all ranks ...................................................................... nb/intel/x4x: Program read training results to all ranks While during the read training itself only the settings for rank 0 are used for all ranks, the controller does use the separate settings for each rank later on. It is unknown which register is responsible for this. Therefore program the results for all ranks. TESTED: Fixes DG43GT not booting with only the second DIMM slot of a channel populated. Change-Id: I7965a068ef4779847e62e966154764370c91302a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/dq_dqs.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28577/2 -- To view, visit https://review.coreboot.org/28577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7965a068ef4779847e62e966154764370c91302a Gerrit-Change-Number: 28577 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/x4x: Program read training results to all ranks
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28577 ) Change subject: nb/intel/x4x: Program read training results to all ranks ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28577/1/src/northbridge/intel/x4x/dq_dqs.c File src/northbridge/intel/x4x/dq_dqs.c: https://review.coreboot.org/#/c/28577/1/src/northbridge/intel/x4x/dq_dqs.c@… PS1, Line 504: /* Later on separate settings for each rank are used so program line over 80 characters -- To view, visit https://review.coreboot.org/28577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7965a068ef4779847e62e966154764370c91302a Gerrit-Change-Number: 28577 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Sep 2018 21:31:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/x4x: Program read training results to all ranks
by Arthur Heymans (Code Review) 11 Sep '18

11 Sep '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28577 Change subject: nb/intel/x4x: Program read training results to all ranks ...................................................................... nb/intel/x4x: Program read training results to all ranks While during the read training itself only the settings for rank 0 are used for all ranks, the controller does use the separate settings for each rank later on. It is unknown which register is responsible for this. Therefore program the results for all ranks. TESTED: Fixes DG43GT not booting with only the second DIMM slot of a channel populated. Change-Id: I7965a068ef4779847e62e966154764370c91302a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/dq_dqs.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28577/1 diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 8704d39..e4aacfa 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -447,7 +447,10 @@ * - use the mean between the saved succeeding and failing value * - note0: bytelanes cannot be trained independently, so the delays need to be * adjusted and tested for all of them at the same time - * - note1: this memory controller appears to have per rank registers for these + * - note1: At this stage all ranks effectively use the rank0's rt_dqs settings, + * but later on their respective setting is used (TODO where??). + * So programming the results for all ranks at the end of the training. + * - note2: this memory controller appears to have per rank registers for these * DQS rx delays, but only the one rank 0 seems to be used for all of them */ int do_read_training(struct sysinfo *s) @@ -498,6 +501,8 @@ } printk(RAM_DEBUG, "Centered values, loop %d:\n", loop); + /* Later on separate settings for each rank are used so program + all of them */ FOR_EACH_BYTELANE(lane) { u8 center = (dqs_lower[lane] + dqs_upper[lane]) / 2; printk(RAM_DEBUG, "\t lane%d: #%d\n", lane, center); @@ -519,7 +524,7 @@ printk(BIOS_ERR, "Huh? read training overflowed!!\n"); } - FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) + FOR_EACH_RANK_IN_CHANNEL(rank) rt_set_dqs(channel, lane, rank, &s->rt_dqs[channel][lane]); printk(BIOS_DEBUG, "\tlane%d: %d.%d\n", -- To view, visit https://review.coreboot.org/28577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7965a068ef4779847e62e966154764370c91302a Gerrit-Change-Number: 28577 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: ec/google/chromeec: Update google_chromeec_get_board_version prototype
by Karthik Ramasubramanian (Code Review) 11 Sep '18

11 Sep '18

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/28576 Change subject: ec/google/chromeec: Update google_chromeec_get_board_version prototype ...................................................................... ec/google/chromeec: Update google_chromeec_get_board_version prototype The helper function to get the board version from EC returns 0 on failure. But 0 is also a valid board version. Update the helper function to return -1 on failure and update the use-cases. BUG=b:114001972,b:114677884,b:114677887 Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_boardid.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/slippy/onboard.h M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/zoombini/boardid.c M src/mainboard/google/zoombini/variants/baseboard/boardid.c M src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h 11 files changed, 29 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28576/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 449eaf3..24a597d 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -633,10 +633,11 @@ } #ifndef __SMM__ -u16 google_chromeec_get_board_version(void) +int google_chromeec_get_board_version(void) { struct chromeec_command cmd; struct ec_response_board_version board_v; + int rv; cmd.cmd_code = EC_CMD_GET_BOARD_VERSION; cmd.cmd_version = 0; @@ -645,8 +646,9 @@ cmd.cmd_data_out = &board_v; cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) - return 0; + rv = google_chromeec_command(&cmd); + if (rv) + return -1; return board_v.board_version; } diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 2c6f1d6..6a63b14 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -46,7 +46,15 @@ int google_chromeec_check_feature(int feature); uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); -u16 google_chromeec_get_board_version(void); + +/** + * google_chromeec_get_board_version() - Get the board version + * + * Return: non-negative board version on success, -1 on failure. + * + * This function is used to get the board version information from EC. + */ +int google_chromeec_get_board_version(void); u32 google_chromeec_get_sku_id(void); int google_chromeec_set_sku_id(u32 skuid); uint64_t google_chromeec_get_events_b(void); diff --git a/src/ec/google/chromeec/ec_boardid.c b/src/ec/google/chromeec/ec_boardid.c index 9ec058d..09e7f99 100644 --- a/src/ec/google/chromeec/ec_boardid.c +++ b/src/ec/google/chromeec/ec_boardid.c @@ -19,9 +19,12 @@ uint32_t board_id(void) { MAYBE_STATIC int id = -1; + MAYBE_STATIC bool done_once = false; - if (id < 0) + if (!done_once) { id = google_chromeec_get_board_version(); + done_once = true; + } return id; } diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 91b7e59..a5a9e05 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -144,7 +144,7 @@ /* Initialize the Embedded Controller */ link_ec_init(); - if (google_chromeec_get_board_version() == 0) { + if (google_chromeec_get_board_version() <= 0) { /* If running on proto1 - enable reversion of gpio11. */ u32 gpio_inv; u16 gpio_base = pci_read_config16 diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h index 9e1dc8b..cd48f6b 100644 --- a/src/mainboard/google/slippy/onboard.h +++ b/src/mainboard/google/slippy/onboard.h @@ -33,6 +33,7 @@ #define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */ #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a +#define PEPPY_BOARD_VERSION_UNKNOWN -1 #define PEPPY_BOARD_VERSION_PROTO 0 #define PEPPY_BOARD_VERSION_EVT 1 diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index bf21cbc..6447174 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -96,6 +96,7 @@ memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); switch (google_chromeec_get_board_version()) { + case PEPPY_BOARD_VERSION_UNKNOWN: case PEPPY_BOARD_VERSION_PROTO: /* Index 0 is 2GB config with CH0 only. */ if (spd_index == 0) diff --git a/src/mainboard/google/zoombini/boardid.c b/src/mainboard/google/zoombini/boardid.c index 4b05c52..4f39444 100644 --- a/src/mainboard/google/zoombini/boardid.c +++ b/src/mainboard/google/zoombini/boardid.c @@ -20,9 +20,12 @@ uint32_t board_id(void) { MAYBE_STATIC int id = -1; + MAYBE_STATIC bool done_once = false; - if (id < 0) + if (!done_once) { id = variant_board_id(); + done_once = true; + } return id; } diff --git a/src/mainboard/google/zoombini/variants/baseboard/boardid.c b/src/mainboard/google/zoombini/variants/baseboard/boardid.c index c8a5cf1..ad7e3ad 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/boardid.c +++ b/src/mainboard/google/zoombini/variants/baseboard/boardid.c @@ -17,7 +17,7 @@ #include <compiler.h> #include <ec/google/chromeec/ec.h> -uint8_t __weak variant_board_id(void) +int __weak variant_board_id(void) { return google_chromeec_get_board_version(); } diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h index eac0fee..e8c7c20 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h @@ -23,7 +23,7 @@ #include <vendorcode/google/chromeos/chromeos.h> /* Return the board id for the current variant board. */ -uint8_t variant_board_id(void); +int variant_board_id(void); /* * The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index 530c06a..1aac275 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -17,7 +17,7 @@ #include <compiler.h> #include <ec/google/chromeec/ec.h> -uint8_t __weak variant_board_id(void) +int __weak variant_board_id(void) { if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) return google_chromeec_get_board_version(); diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h index c278cde..4ed7a73 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h @@ -22,7 +22,7 @@ #include <vendorcode/google/chromeos/chromeos.h> /* Return the board id for the current variant board. */ -uint8_t variant_board_id(void); +int variant_board_id(void); /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ -- To view, visit https://review.coreboot.org/28576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Gerrit-Change-Number: 28576 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>

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Change in coreboot[master]: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/28573 ) Change subject: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves ...................................................................... Abandoned Too mixed up -- To view, visit https://review.coreboot.org/28573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ibef28cee53068569482e3ea255fd85f97d1d1a30 Gerrit-Change-Number: 28573 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/28571 ) Change subject: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code ...................................................................... Abandoned Too mixed up -- To view, visit https://review.coreboot.org/28571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I825b6380fb658c3ea5fc669117ae04d2dc181819 Gerrit-Change-Number: 28571 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28575 Change subject: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves ...................................................................... mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves Use the new I2C slave reset function and reset all slaves connected to all 4 I2C. BUG=b:114479395 TEST=Added debug code. Build and boot grunt. Examined output, confirmed GPIO pins changing as required. Removed debug code. Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h 3 files changed, 24 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28575/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 2540bcd..c2e0f68 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -31,6 +31,7 @@ #include <variant/ec.h> #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <gpio.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -123,6 +124,7 @@ printk(BIOS_INFO, "Board ID: %d\n", boardid); + variant_reset_i2c_devices(); mainboard_ec_init(); gpios = variant_gpio_table(&num_gpios); diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 75a8ab5..0b77e8f 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -62,9 +62,8 @@ /* GPIO_74 - LPC_CLK0_EC_R */ PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN), - /* GPIO_76 - EN_PP3300_TOUCHSCREEN */ - /* Init low to reset the chip */ - PAD_GPO(GPIO_76, LOW), + /* GPIO_85 - TOUCHSCREEN_RST (Active High) */ + PAD_GPO(GPIO_85, LOW), /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), @@ -164,9 +163,6 @@ /* GPIO_84 - HUB_RST (Active High) */ PAD_GPO(GPIO_84, LOW), - /* GPIO_85 - TOUCHSCREEN_RST (Active High) */ - PAD_GPO(GPIO_85, LOW), - /* GPIO_86 - Unused (TP109) */ PAD_GPI(GPIO_86, PULL_UP), @@ -252,6 +248,20 @@ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; +struct soc_amd_force_toggle i2c_pins[] = { + /* GPIO_85 - TOUCHSCREEN_RST (Active High) */ + PAD_RESET_DEVICE(GPIO_85), + + /* GPIO_113 - APU_I2C_SCL2 (Pen & Trackpad) */ + PAD_RESET_I2C_SLAVE(GPIO_113), + + /* GPIO_145 - PCH_I2C_AUDIO_SCL */ + PAD_RESET_I2C_SLAVE(GPIO_145), + + /* GPIO_147 - PCH_I2C_H1_TPM_SCL */ + PAD_RESET_I2C_SLAVE(GPIO_147), +}; + const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size) { @@ -266,6 +276,11 @@ return gpio_set_stage_ram; } +__weak void variant_reset_i2c_devices(void) +{ + sb_reset_i2c_slaves(i2c_pins, ARRAY_SIZE(i2c_pins)); +} + /* * This function is still needed for boards that sets gevents above 23 * that will generate SCI or SMI, such as kahlee. Normally this function diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 6e89105..cc73d3e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -30,6 +30,7 @@ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); const struct soc_amd_gpio *variant_gpio_table(size_t *size); void variant_romstage_entry(int s3_resume); +void variant_reset_i2c_devices(void); #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) void variant_mainboard_suspend_resume(void); #endif -- To view, visit https://review.coreboot.org/28575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359 Gerrit-Change-Number: 28575 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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coreboot-gerrit September 2018