coreboot-gerrit September 2018

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Change in coreboot[master]: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28574 Change subject: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code ...................................................................... soc/amd/stoneyridge/gpio.c: Create I2C slave reset code AMD soc does not wait for I2C transaction to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement either solution. BUG=b:114479395 TEST=Build and boot grunt. Change-Id: I7f74b7e45c509044825355874753969f074e2382 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28574/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 88e7d3b..1da7ab4 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -22,6 +22,7 @@ #include <soc/southbridge.h> #include <assert.h> #include <compiler.h> +#include <delay.h> static const struct soc_amd_event gpio_event_table[] = { { GPIO_1, GEVENT_19 }, @@ -297,6 +298,85 @@ edge_level, mask); } +static const struct soc_amd_gpio gpo_i2c_2_gpo[] = { + PAD_GPO(GPIO_19, HIGH), + PAD_GPI(GPIO_20, PULL_UP), + PAD_GPO(GPIO_113, HIGH), + PAD_GPI(GPIO_114, PULL_UP), + PAD_GPO(GPIO_145, HIGH), + PAD_GPI(GPIO_146, PULL_UP), + PAD_GPO(GPIO_147, HIGH), + PAD_GPI(GPIO_148, PULL_UP), +}; + +static void save_i2c_pin_registers(uint8_t gpio, + struct soc_amd_i2c_save *save_table) +{ + uint32_t *gpio_ptr; + uint8_t *mux_ptr; + + mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX); + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + save_table->mux_pointer = mux_ptr; + save_table->mux_value = read8(mux_ptr); + save_table->control_pointer = gpio_ptr; + save_table->control_value = read32(gpio_ptr); +} + +void sb_reset_i2c_slaves(const struct soc_amd_force_toggle *pin_table, + size_t size) +{ + struct soc_amd_i2c_save save_table[8]; + struct soc_and_pointer_count control_table[8]; + uint32_t reg32, *reg_ptr; + uint8_t i, j, remain; + + for (i = 0; i < 8; i++) { + save_i2c_pin_registers(gpo_i2c_2_gpo[i].gpio, &save_table[i]); + control_table[i].ptr = NULL; + } + sb_program_gpios(gpo_i2c_2_gpo, ARRAY_SIZE(gpo_i2c_2_gpo)); + + if (size > 8) { + printk(BIOS_WARNING, "Maximum reset size is 8 elements\n"); + j = 8; + } else + j = size; + for (i = 0; i < j; i++) { + reg_ptr = (uint32_t *)gpio_get_address(pin_table[i].gpio); + control_table[i].ptr = reg_ptr; + control_table[i].count = pin_table[i].count; + } + + remain = 1; /* at least 1 pin needs to be toggled */ + while (remain) { + for (i = 0; i < j; i++) { + if (control_table[i].count) { + reg32 = read32(control_table[i].ptr); + reg32 ^= GPIO_OUTPUT_VALUE; + write32(control_table[i].ptr, reg32); + } + } + udelay(5); + remain = 0; + for (i = 0; i < j; i++) { + if (control_table[i].count) { + reg32 = read32(control_table[i].ptr); + reg32 ^= GPIO_OUTPUT_VALUE; + write32(control_table[i].ptr, reg32); + control_table[i].count--; + } + remain += control_table[i].count; + } + udelay(5); + } + + for (i = 0; i < 8; i++) { + write8(save_table->mux_pointer, save_table->mux_value); + write32(save_table->control_pointer, save_table->control_value); + } +} + int gpio_interrupt_status(gpio_t gpio) { uintptr_t gpio_address = gpio_get_address(gpio); diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 6e72293..d4383f8 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -36,6 +36,23 @@ uint8_t event; }; +struct soc_amd_i2c_save { + uint32_t *control_pointer; + uint32_t control_value; + uint8_t *mux_pointer; + uint8_t mux_value; +}; + +struct soc_and_pointer_count { + uint32_t *ptr; + uint8_t count; +}; + +struct soc_amd_force_toggle { + uint8_t gpio; + uint8_t count; +}; + #define GPIO_TOTAL_PINS 149 #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ @@ -558,6 +575,15 @@ .control = (GPIO_IN ## _ ## type | GPIO_IN ## _ ## time), \ .flags = GPIO_FLAG_DEBOUNCE } +/* Use these to define GPIO to be toggled, to solve I2C reset issues */ +#define PAD_RESET_I2C_SLAVE(pin) \ + { .gpio = (pin), \ + .count = 9 } + +#define PAD_RESET_DEVICE(pin) \ + { .gpio = (pin), \ + .count = 1 } + typedef uint32_t gpio_t; /* Get the address of the control register of a particular pin */ uintptr_t gpio_get_address(gpio_t gpio_num); @@ -571,6 +597,8 @@ * @return none */ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size); +void sb_reset_i2c_slaves(const struct soc_amd_force_toggle *pin_table, + size_t size); /* Return the interrupt status and clear if set. */ int gpio_interrupt_status(gpio_t gpio); -- To view, visit https://review.coreboot.org/28574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7f74b7e45c509044825355874753969f074e2382 Gerrit-Change-Number: 28574 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28573 ) Change subject: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28573/2/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/28573/2/src/mainboard/google/kahlee/variant… PS2, Line 1: <<</* spaces required around that '<' (ctx:OxC) -- To view, visit https://review.coreboot.org/28573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibef28cee53068569482e3ea255fd85f97d1d1a30 Gerrit-Change-Number: 28573 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Sep 2018 18:12:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28573 to look at the new patch set (#2). Change subject: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves ...................................................................... mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves Use the new I2C slave reset function and reset all slaves connected to all 4 I2C. BUG=b:114479395 TEST=Added debug code. Build and boot grunt. Examined output, confirmed GPIO pins changing as required. Removed debug code. Change-Id: Ibef28cee53068569482e3ea255fd85f97d1d1a30 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h 3 files changed, 25 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28573/2 -- To view, visit https://review.coreboot.org/28573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibef28cee53068569482e3ea255fd85f97d1d1a30 Gerrit-Change-Number: 28573 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/28572 ) Change subject: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code ...................................................................... Abandoned Wrong code, got mixed and missing files. -- To view, visit https://review.coreboot.org/28572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I9a0bc00c55ecc8ec660c74794bee48302663e72b Gerrit-Change-Number: 28572 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28572 to look at the new patch set (#2). Change subject: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code ...................................................................... soc/amd/stoneyridge/gpio.c: Create I2C slave reset code AMD soc does not wait for I2C transaction to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement either solution. BUG=b:114479395 TEST=Build and boot grunt. Change-Id: I9a0bc00c55ecc8ec660c74794bee48302663e72b Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28572/2 -- To view, visit https://review.coreboot.org/28572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9a0bc00c55ecc8ec660c74794bee48302663e72b Gerrit-Change-Number: 28572 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code
by build bot (Jenkins) (Code Review) 11 Sep '18

11 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28571 ) Change subject: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28571/1/src/soc/amd/stoneyridge/gpio.c File src/soc/amd/stoneyridge/gpio.c: https://review.coreboot.org/#/c/28571/1/src/soc/amd/stoneyridge/gpio.c@352 PS1, Line 352: while(remain) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28571/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/gpio.h: https://review.coreboot.org/#/c/28571/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 39: struct soc_amd_i2c_save{ missing space after struct definition -- To view, visit https://review.coreboot.org/28571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I825b6380fb658c3ea5fc669117ae04d2dc181819 Gerrit-Change-Number: 28571 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Sep 2018 17:20:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28573 Change subject: mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves ...................................................................... mv/google/kahlee/variants/baseboard/gpio.c: Reset I2C slaves Use the new I2C slave reset function and reset all slaves connected to all 4 I2C. BUG=b:114479395 TEST=Added debug code. Build and boot grunt. Examined output, confirmed GPIO pins changing as required. Removed debug code. Change-Id: Ibef28cee53068569482e3ea255fd85f97d1d1a30 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h 3 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28573/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 2540bcd..c2e0f68 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -31,6 +31,7 @@ #include <variant/ec.h> #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <gpio.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -123,6 +124,7 @@ printk(BIOS_INFO, "Board ID: %d\n", boardid); + variant_reset_i2c_devices(); mainboard_ec_init(); gpios = variant_gpio_table(&num_gpios); diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index db68fa4..cd115b1 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -58,6 +58,9 @@ /* GPIO_74 - LPC_CLK0_EC_R */ PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN), + /* GPIO_85 - TOUCHSCREEN_RST (Active High) */ + PAD_GPO(GPIO_85, LOW), + /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), @@ -156,9 +159,6 @@ /* GPIO_84 - HUB_RST (Active High) */ PAD_GPO(GPIO_84, LOW), - /* GPIO_85 - TOUCHSCREEN_RST (Active High) */ - PAD_GPO(GPIO_85, LOW), - /* GPIO_86 - Unused (TP109) */ PAD_GPI(GPIO_86, PULL_UP), @@ -244,6 +244,20 @@ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; +struct soc_amd_force_toggle i2c_pins[] = { + /* GPIO_85 - TOUCHSCREEN_RST (Active High) */ + PAD_RESET_DEVICE(GPIO_85), + + /* GPIO_113 - APU_I2C_SCL2 (Pen & Trackpad) */ + PAD_RESET_I2C_SLAVE(GPIO_113), + + /* GPIO_145 - PCH_I2C_AUDIO_SCL */ + PAD_RESET_I2C_SLAVE(GPIO_145), + + /* GPIO_147 - PCH_I2C_H1_TPM_SCL */ + PAD_RESET_I2C_SLAVE(GPIO_147), +}; + const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size) { @@ -258,6 +272,11 @@ return gpio_set_stage_ram; } +__weak void variant_reset_i2c_devices(void) +{ + sb_reset_i2c_slaves(i2c_pins, ARRAY_SIZE(i2c_pins)); +} + /* * This function is still needed for boards that sets gevents above 23 * that will generate SCI or SMI, such as kahlee. Normally this function diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 6e89105..cc73d3e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -30,6 +30,7 @@ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); const struct soc_amd_gpio *variant_gpio_table(size_t *size); void variant_romstage_entry(int s3_resume); +void variant_reset_i2c_devices(void); #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) void variant_mainboard_suspend_resume(void); #endif -- To view, visit https://review.coreboot.org/28573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibef28cee53068569482e3ea255fd85f97d1d1a30 Gerrit-Change-Number: 28573 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28572 Change subject: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code ...................................................................... soc/amd/stoneyridge/gpio.c: Create I2C slave reset code AMD soc does not wait for I2C transaction to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement either solution. BUG=b:114479395 TEST=Build and boot grunt. Change-Id: I9a0bc00c55ecc8ec660c74794bee48302663e72b Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28572/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index d846315..1da7ab4 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -349,7 +349,7 @@ } remain = 1; /* at least 1 pin needs to be toggled */ - while(remain) { + while (remain) { for (i = 0; i < j; i++) { if (control_table[i].count) { reg32 = read32(control_table[i].ptr); -- To view, visit https://review.coreboot.org/28572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9a0bc00c55ecc8ec660c74794bee48302663e72b Gerrit-Change-Number: 28572 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code
by Richard Spiegel (Code Review) 11 Sep '18

11 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28571 Change subject: soc/amd/stoneyridge/gpio.c: Create I2C slave reset code ...................................................................... soc/amd/stoneyridge/gpio.c: Create I2C slave reset code AMD soc does not wait for I2C transaction to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement either solution. BUG=b:114479395 TEST=Build and boot grunt. Change-Id: I825b6380fb658c3ea5fc669117ae04d2dc181819 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28571/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 88e7d3b..d846315 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -22,6 +22,7 @@ #include <soc/southbridge.h> #include <assert.h> #include <compiler.h> +#include <delay.h> static const struct soc_amd_event gpio_event_table[] = { { GPIO_1, GEVENT_19 }, @@ -297,6 +298,85 @@ edge_level, mask); } +static const struct soc_amd_gpio gpo_i2c_2_gpo[] = { + PAD_GPO(GPIO_19, HIGH), + PAD_GPI(GPIO_20, PULL_UP), + PAD_GPO(GPIO_113, HIGH), + PAD_GPI(GPIO_114, PULL_UP), + PAD_GPO(GPIO_145, HIGH), + PAD_GPI(GPIO_146, PULL_UP), + PAD_GPO(GPIO_147, HIGH), + PAD_GPI(GPIO_148, PULL_UP), +}; + +static void save_i2c_pin_registers(uint8_t gpio, + struct soc_amd_i2c_save *save_table) +{ + uint32_t *gpio_ptr; + uint8_t *mux_ptr; + + mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX); + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + save_table->mux_pointer = mux_ptr; + save_table->mux_value = read8(mux_ptr); + save_table->control_pointer = gpio_ptr; + save_table->control_value = read32(gpio_ptr); +} + +void sb_reset_i2c_slaves(const struct soc_amd_force_toggle *pin_table, + size_t size) +{ + struct soc_amd_i2c_save save_table[8]; + struct soc_and_pointer_count control_table[8]; + uint32_t reg32, *reg_ptr; + uint8_t i, j, remain; + + for (i = 0; i < 8; i++) { + save_i2c_pin_registers(gpo_i2c_2_gpo[i].gpio, &save_table[i]); + control_table[i].ptr = NULL; + } + sb_program_gpios(gpo_i2c_2_gpo, ARRAY_SIZE(gpo_i2c_2_gpo)); + + if (size > 8) { + printk(BIOS_WARNING, "Maximum reset size is 8 elements\n"); + j = 8; + } else + j = size; + for (i = 0; i < j; i++) { + reg_ptr = (uint32_t *)gpio_get_address(pin_table[i].gpio); + control_table[i].ptr = reg_ptr; + control_table[i].count = pin_table[i].count; + } + + remain = 1; /* at least 1 pin needs to be toggled */ + while(remain) { + for (i = 0; i < j; i++) { + if (control_table[i].count) { + reg32 = read32(control_table[i].ptr); + reg32 ^= GPIO_OUTPUT_VALUE; + write32(control_table[i].ptr, reg32); + } + } + udelay(5); + remain = 0; + for (i = 0; i < j; i++) { + if (control_table[i].count) { + reg32 = read32(control_table[i].ptr); + reg32 ^= GPIO_OUTPUT_VALUE; + write32(control_table[i].ptr, reg32); + control_table[i].count--; + } + remain += control_table[i].count; + } + udelay(5); + } + + for (i = 0; i < 8; i++) { + write8(save_table->mux_pointer, save_table->mux_value); + write32(save_table->control_pointer, save_table->control_value); + } +} + int gpio_interrupt_status(gpio_t gpio) { uintptr_t gpio_address = gpio_get_address(gpio); diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 6e72293..e49db6f 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -36,6 +36,23 @@ uint8_t event; }; +struct soc_amd_i2c_save{ + uint32_t *control_pointer; + uint32_t control_value; + uint8_t *mux_pointer; + uint8_t mux_value; +}; + +struct soc_and_pointer_count { + uint32_t *ptr; + uint8_t count; +}; + +struct soc_amd_force_toggle { + uint8_t gpio; + uint8_t count; +}; + #define GPIO_TOTAL_PINS 149 #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ @@ -558,6 +575,15 @@ .control = (GPIO_IN ## _ ## type | GPIO_IN ## _ ## time), \ .flags = GPIO_FLAG_DEBOUNCE } +/* Use these to define GPIO to be toggled, to solve I2C reset issues */ +#define PAD_RESET_I2C_SLAVE(pin) \ + { .gpio = (pin), \ + .count = 9 } + +#define PAD_RESET_DEVICE(pin) \ + { .gpio = (pin), \ + .count = 1 } + typedef uint32_t gpio_t; /* Get the address of the control register of a particular pin */ uintptr_t gpio_get_address(gpio_t gpio_num); @@ -571,6 +597,8 @@ * @return none */ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size); +void sb_reset_i2c_slaves(const struct soc_amd_force_toggle *pin_table, + size_t size); /* Return the interrupt status and clear if set. */ int gpio_interrupt_status(gpio_t gpio); -- To view, visit https://review.coreboot.org/28571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I825b6380fb658c3ea5fc669117ae04d2dc181819 Gerrit-Change-Number: 28571 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Fix more GPIO functions
by Jonathan Neuschäfer (Code Review) 11 Sep '18

11 Sep '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28570 Change subject: soc/amd/stoneyridge: Fix more GPIO functions ...................................................................... soc/amd/stoneyridge: Fix more GPIO functions commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed one instance of this bug, but it was more widespread. TEST=None Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/amd/stoneyridge/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28570/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 88e7d3b..16e046d 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -173,7 +173,7 @@ reg = read32((void *)gpio_address); reg &= ~GPIO_PULLUP_ENABLE; reg |= GPIO_PULLDOWN_ENABLE; - write32((void *)(uintptr_t)gpio_num, reg); + write32((void *)(uintptr_t)gpio_address, reg); } void gpio_input_pullup(gpio_t gpio_num) @@ -184,7 +184,7 @@ reg = read32((void *)gpio_address); reg &= ~GPIO_PULLDOWN_ENABLE; reg |= GPIO_PULLUP_ENABLE; - write32((void *)(uintptr_t)gpio_num, reg); + write32((void *)(uintptr_t)gpio_address, reg); } void gpio_input(gpio_t gpio_num) @@ -194,7 +194,7 @@ reg = read32((void *)gpio_address); reg &= ~GPIO_OUTPUT_ENABLE; - write32((void *)(uintptr_t)gpio_num, reg); + write32((void *)(uintptr_t)gpio_address, reg); } void gpio_output(gpio_t gpio_num, int value) @@ -204,7 +204,7 @@ reg = read32((void *)gpio_address); reg |= GPIO_OUTPUT_ENABLE; - write32((void *)(uintptr_t)gpio_num, reg); + write32((void *)(uintptr_t)gpio_address, reg); gpio_set(gpio_num, value); } -- To view, visit https://review.coreboot.org/28570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b Gerrit-Change-Number: 28570 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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coreboot-gerrit September 2018