coreboot-gerrit September 2018

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Change in coreboot[master]: payloads/external: Add yabits payload
by Patrick Georgi (Code Review) 13 Sep '18

13 Sep '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/28590 ) Change subject: payloads/external: Add yabits payload ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/28590/1/payloads/external/Yabits/Kconfig File payloads/external/Yabits/Kconfig: https://review.coreboot.org/#/c/28590/1/payloads/external/Yabits/Kconfig@17 PS1, Line 17: Newest Memtest86+ version. copy & paste? -- To view, visit https://review.coreboot.org/28590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899 Gerrit-Change-Number: 28590 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 13 Sep 2018 10:15:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: payloads/external: Add yabits payload
by Martin Roth (Code Review) 13 Sep '18

13 Sep '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28590 Change subject: payloads/external: Add yabits payload ...................................................................... payloads/external: Add yabits payload Yabits (Yet another UEFI bootloader) is designed to be a slim and quick alternative to Tianocore. It is still under heavy development. https://web.archive.org/web/https://yabits.github.io/ Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899 Signed-off-by: Martin Roth <martin(a)coreboot.org> --- M payloads/Makefile.inc M payloads/external/Makefile.inc A payloads/external/Yabits/Kconfig A payloads/external/Yabits/Kconfig.name A payloads/external/Yabits/Makefile 5 files changed, 140 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28590/1 diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index 0d142d6..83d3910 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -36,6 +36,7 @@ payloads/external/tianocore \ payloads/external/GRUB2 \ payloads/external/LinuxBoot \ +payloads/external/Yabits \ payloads/coreinfo/build/coreinfo.elf coreinfo: $(MAKE) -C payloads/coreinfo defaultbuild diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 8bd0dc3..a5dbfdf 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -282,3 +282,15 @@ payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz: linuxboot payloads/external/LinuxBoot/linuxboot/kernel/.config: linuxboot payloads/external/LinuxBoot/linuxboot/go/src/github.com/u-root/u-root/.git: linuxboot + +payloads/external/Yabits/uefi/build/uefi.elf yabits: + $(MAKE) -C payloads/external/Yabits all \ + CC="$(CC_x86_32)" \ + LD="$(LD_x86_32)" \ + OBJCOPY="$(OBJCOPY_x86_32)" \ + AS="$(AS_x86_32)" \ + CONFIG_YABITS_REVISION=$(CONFIG_YABITS_REVISION) \ + CONFIG_YABITS_REVISION_ID=$(CONFIG_YABITS_REVISION_ID) \ + CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \ + CONFIG_YABITS_STABLE=$(CONFIG_YABITS_STABLE) \ + MFLAGS= MAKEFLAGS= diff --git a/payloads/external/Yabits/Kconfig b/payloads/external/Yabits/Kconfig new file mode 100644 index 0000000..00b8a9e --- /dev/null +++ b/payloads/external/Yabits/Kconfig @@ -0,0 +1,47 @@ +if PAYLOAD_YABITS + +choice + prompt "Yabits version" + default YABITS_STABLE + +config YABITS_STABLE + bool "Stable" + help + Stable Yabits version. + + For reproducible builds, this option must be selected. + +config YABITS_MASTER + bool "Master" + help + Newest Memtest86+ version. + + This option will fetch the newest version of the Memtest86+ code, + updating as new changes are committed. This makes the build + non-reproducible, as it can fetch different code each time. + +config YABITS_REVISION + bool "git revision" + help + Select this option if you have a specific commit or branch + that you want to use as the revision from which to + build Memtest86+. Using a branch name makes the build + non-reproducible, as it can fetch different code as the + branch changes. + + You will be able to specify the name of a branch or a commit id + later. + +endchoice + +config YABITS_REVISION_ID + string "Insert a commit's SHA-1 or a branch name" + depends on YABITS_REVISION + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. + +config PAYLOAD_FILE + default "payloads/external/Yabits/uefi/build/uefi.elf" + +endif diff --git a/payloads/external/Yabits/Kconfig.name b/payloads/external/Yabits/Kconfig.name new file mode 100644 index 0000000..84f860f --- /dev/null +++ b/payloads/external/Yabits/Kconfig.name @@ -0,0 +1,11 @@ +config PAYLOAD_YABITS + bool "Yabits - Yet another UEFI Bootloader (Under Development)" + depends on ARCH_X86 + help + Yabits - yabits.github.io + yabits is a pure UEFI coreboot payload. Compared with + TianoCore, it is fast and lightweight. yabits is based on the + part of Minoca OS. It can run GRUB2, Linux, OpenBSD, and other + UEFI applications. + + It is still under the development and not ready for production. diff --git a/payloads/external/Yabits/Makefile b/payloads/external/Yabits/Makefile new file mode 100644 index 0000000..e425dd2 --- /dev/null +++ b/payloads/external/Yabits/Makefile @@ -0,0 +1,69 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +TAG-$(CONFIG_YABITS_MASTER)=origin/master +NAME-$(CONFIG_YABITS_MASTER)=Master +TAG-$(CONFIG_YABITS_STABLE)=d25abb067431dee9af9f8a874a209730ab7f0e91 +NAME-$(CONFIG_YABITS_STABLE)=Stable +TAG-$(CONFIG_YABITS_REVISION)=$(CONFIG_YABITS_REVISION_ID) + +project_name=Yabits +project_dir=$(CURDIR)/uefi +project_git_repo=https://github.com/yabits/uefi.git +LIBCONFIG_PATH="../../../libpayload" + +all: build + +$(project_dir): + echo " Cloning $(project_name) from Git" + git clone $(project_git_repo) $(project_dir) + +fetch: $(project_dir) +ifeq ($(TAG-y),) + echo "Error: The specified tag is invalid" +ifeq ($(CONFIG_YABITS_REVISION),y) + echo "Error: There is no revision specified for $(project_name)" + false +endif + false +endif + -cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \ + if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \ + echo " Fetching new commits from the $(project_name) git repo"; \ + git fetch; fi + +checkout: fetch + echo " Checking out $(project_name) revision $(NAME-y) ($(TAG-y))" + cd $(project_dir); \ + git checkout master; \ + git branch -D coreboot 2>/dev/null; \ + git checkout -b coreboot $(TAG-y) + +build: checkout + echo " MAKE $(project_name) $(NAME-y)" + $(if $(wildcard uefi/.xcompile),,$(shell bash ../../../util/xcompile/xcompile > uefi/.xcompile)) + $(MAKE) -C $(project_dir) defconfig LIBCONFIG_PATH=$(LIBCONFIG_PATH) XGCC=$(XGCCPATH) + $(MAKE) -C $(project_dir) all LIBCONFIG_PATH=$(LIBCONFIG_PATH) XGCC=$(XGCCPATH) + +clean: + test -d $(project_dir) && $(MAKE) -C $(project_dir) clean LIBCONFIG_PATH=$(LIBCONFIG_PATH) || exit 0 + +distclean: + rm -rf $(project_dir) + +print-repo-info: + echo "$(project_git_repo) $(project_dir)" + +.PHONY: all build checkout clean distclean fetch print-repo-info -- To view, visit https://review.coreboot.org/28590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899 Gerrit-Change-Number: 28590 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume
by Patrick Rudolph (Code Review) 13 Sep '18

13 Sep '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28589 ) Change subject: nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icac6e696efa1721933a1963b45d608d9ae735149 Gerrit-Change-Number: 28589 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Sep 2018 09:51:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: device/ddr3: Prevent overflow when adding SMBUS Table 17 entries
by Patrick Rudolph (Code Review) 13 Sep '18

13 Sep '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28588 ) Change subject: device/ddr3: Prevent overflow when adding SMBUS Table 17 entries ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If84c6849011106b2a50e504b79cda9cd6a3a9cc3 Gerrit-Change-Number: 28588 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Sep 2018 09:51:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume
by Nico Huber (Code Review) 13 Sep '18

13 Sep '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28589 Change subject: nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume ...................................................................... nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume Change-Id: Icac6e696efa1721933a1963b45d608d9ae735149 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/28589/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0f72d88..46d5de8 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -437,7 +437,8 @@ halt(); } - fill_smbios17(&ctrl); + if (!s3resume) + fill_smbios17(&ctrl); } void perform_raminit(int s3resume) -- To view, visit https://review.coreboot.org/28589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icac6e696efa1721933a1963b45d608d9ae735149 Gerrit-Change-Number: 28589 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: device/ddr3: Prevent overflow when adding SMBUS Table 17 entries
by Nico Huber (Code Review) 13 Sep '18

13 Sep '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28588 Change subject: device/ddr3: Prevent overflow when adding SMBUS Table 17 entries ...................................................................... device/ddr3: Prevent overflow when adding SMBUS Table 17 entries Change-Id: If84c6849011106b2a50e504b79cda9cd6a3a9cc3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/dram/ddr3.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/28588/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 63ca964..f27fdcb 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -559,6 +559,12 @@ memset(mem_info, 0, sizeof(*mem_info)); } + if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) { + printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n", + __func__); + return CB_ERR; + } + dimm = &mem_info->dimm[mem_info->dimm_cnt]; if (info->size_mb) { dimm->ddr_type = MEMORY_TYPE_DDR3; -- To view, visit https://review.coreboot.org/28588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If84c6849011106b2a50e504b79cda9cd6a3a9cc3 Gerrit-Change-Number: 28588 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: arch/riscv: provide a monotonic timer
by build bot (Jenkins) (Code Review) 13 Sep '18

13 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27434 ) Change subject: arch/riscv: provide a monotonic timer ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/#/c/27434/10/src/arch/riscv/include/arch/io.h File src/arch/riscv/include/arch/io.h: https://review.coreboot.org/#/c/27434/10/src/arch/riscv/include/arch/io.h@34 PS10, Line 34: static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr) line over 80 characters https://review.coreboot.org/#/c/27434/10/src/arch/riscv/include/arch/io.h@54 PS10, Line 54: static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value) line over 80 characters -- To view, visit https://review.coreboot.org/27434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Gerrit-Change-Number: 27434 Gerrit-PatchSet: 10 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Comment-Date: Thu, 13 Sep 2018 07:29:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: fetch DRAM part number from CBI for phaser after D...
by Peichao Li (Code Review) 13 Sep '18

13 Sep '18

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/28586 Change subject: mb/google/octopus: fetch DRAM part number from CBI for phaser after DVT phase ...................................................................... mb/google/octopus: fetch DRAM part number from CBI for phaser after DVT phase This modification for DVT build and use CBI method enable all memory particles. BUG=b:112870780 TEST=verify it under the EVT unit and pre-test EVT unit(rework RAM ID follow the proposal) respectively. Change-Id: Ie05c4a68c1118d75fb52d3df1de55e3e2b552a69 Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28586/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3ed88bd..0ed6ed4 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -110,6 +110,7 @@ config DRAM_PART_NUM_IN_CBI bool + default y if BOARD_GOOGLE_PHASER config DRAM_PART_NUM_ALWAYS_IN_CBI bool @@ -120,7 +121,7 @@ depends on DRAM_PART_NUM_IN_CBI && !DRAM_PART_NUM_ALWAYS_IN_CBI default 255 if BOARD_GOOGLE_YORP default 255 if BOARD_GOOGLE_BIP - default 9 if BOARD_GOOGLE_PHASER + default 2 if BOARD_GOOGLE_PHASER default 9 if BOARD_GOOGLE_FLEEX default 9 if BOARD_GOOGLE_BOBBA default 9 if BOARD_GOOGLE_MEEP -- To view, visit https://review.coreboot.org/28586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie05c4a68c1118d75fb52d3df1de55e3e2b552a69 Gerrit-Change-Number: 28586 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>

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Change in coreboot[master]: soc/amd/common/block/psp/psp.c: Remove use of PspBaseLib
by build bot (Jenkins) (Code Review) 12 Sep '18

12 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27619 ) Change subject: soc/amd/common/block/psp/psp.c: Remove use of PspBaseLib ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/#/c/27619/10/src/soc/amd/common/block/include/a… File src/soc/amd/common/block/include/amdblocks/psp.h: https://review.coreboot.org/#/c/27619/10/src/soc/amd/common/block/include/a… PS10, Line 35: #define MAGIC_ENABLE_BITS 0x34 /* Extra PCI HDR Ctl Enables */ trailing whitespace https://review.coreboot.org/#/c/27619/10/src/soc/amd/common/block/psp/psp.c File src/soc/amd/common/block/psp/psp.c: https://review.coreboot.org/#/c/27619/10/src/soc/amd/common/block/psp/psp.c… PS10, Line 49: if (value32 == 0xFFFFFFFF) { suspect code indent for conditional statements (8, 10) https://review.coreboot.org/#/c/27619/10/src/soc/amd/common/block/psp/psp.c… PS10, Line 56: if (pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & ~0x0F) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a Gerrit-Change-Number: 27619 Gerrit-PatchSet: 10 Gerrit-Owner: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)se-eng.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 13 Sep 2018 02:00:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee/variants/baseboard: Set STAPM percentage
by build bot (Jenkins) (Code Review) 12 Sep '18

12 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28564 ) Change subject: mb/google/kahlee/variants/baseboard: Set STAPM percentage ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/28564/3/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c: https://review.coreboot.org/#/c/28564/3/src/mainboard/google/kahlee/variant… PS3, Line 161: PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; Avoid multiple line dereference - prefer 'InitEarly->PlatformConfig.PlatStapmConfig.CfgStapmScalar' https://review.coreboot.org/#/c/28564/3/src/mainboard/google/kahlee/variant… PS3, Line 164: PlatStapmConfig.CfgStapmTimeConstant = cfg->stapm_time; Avoid multiple line dereference - prefer 'InitEarly->PlatformConfig.PlatStapmConfig.CfgStapmTimeConstant' -- To view, visit https://review.coreboot.org/28564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504 Gerrit-Change-Number: 28564 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Sep 2018 21:28:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018