coreboot-gerrit September 2018

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Change in coreboot[master]: soc/sifive/fu540: add SiFive supplied header files for SDRAM initiali...
by Philipp Hug (Code Review) 13 Sep '18

13 Sep '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/28594 ) Change subject: soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization ...................................................................... Patch Set 2: What kind of header would make jenkins happy? -- To view, visit https://review.coreboot.org/28594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716 Gerrit-Change-Number: 28594 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Sep 2018 20:34:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/sifive/fu540: add SiFive supplied header files for SDRAM initiali...
by Philipp Hug (Code Review) 13 Sep '18

13 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28594 to look at the new patch set (#2). Change subject: soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization ...................................................................... soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization Add original files from SiFive bootloader. Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- A src/soc/sifive/fu540/ddrregs.h A src/soc/sifive/fu540/regconfig-ctl.h A src/soc/sifive/fu540/regconfig-phy.h 3 files changed, 1,664 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/28594/2 -- To view, visit https://review.coreboot.org/28594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716 Gerrit-Change-Number: 28594 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/sifive/fu540: add SiFive supplied header files for SDRAM intializ...
by build bot (Jenkins) (Code Review) 13 Sep '18

13 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28594 ) Change subject: soc/sifive/fu540: add SiFive supplied header files for SDRAM intialization ...................................................................... Patch Set 1: (150 comments) https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h File src/soc/sifive/fu540/ddrregs.h: https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@8 PS1, Line 8: uint32_t DENALI_PHY_DATA [1215] = { space prohibited before open square bracket '[' https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@9 PS1, Line 9: DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, DENALI_PHY_02_DATA, DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, DENALI_PHY_05_DATA, DENALI_PHY_06_DATA, DENALI_PHY_07_DATA, DENALI_PHY_08_DATA, DENALI_PHY_09_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@10 PS1, Line 10: DENALI_PHY_10_DATA, DENALI_PHY_11_DATA, DENALI_PHY_12_DATA, DENALI_PHY_13_DATA, DENALI_PHY_14_DATA, DENALI_PHY_15_DATA, DENALI_PHY_16_DATA, DENALI_PHY_17_DATA, DENALI_PHY_18_DATA, DENALI_PHY_19_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@11 PS1, Line 11: DENALI_PHY_20_DATA, DENALI_PHY_21_DATA, DENALI_PHY_22_DATA, DENALI_PHY_23_DATA, DENALI_PHY_24_DATA, DENALI_PHY_25_DATA, DENALI_PHY_26_DATA, DENALI_PHY_27_DATA, DENALI_PHY_28_DATA, DENALI_PHY_29_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@12 PS1, Line 12: DENALI_PHY_30_DATA, DENALI_PHY_31_DATA, DENALI_PHY_32_DATA, DENALI_PHY_33_DATA, DENALI_PHY_34_DATA, DENALI_PHY_35_DATA, DENALI_PHY_36_DATA, DENALI_PHY_37_DATA, DENALI_PHY_38_DATA, DENALI_PHY_39_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@13 PS1, Line 13: DENALI_PHY_40_DATA, DENALI_PHY_41_DATA, DENALI_PHY_42_DATA, DENALI_PHY_43_DATA, DENALI_PHY_44_DATA, DENALI_PHY_45_DATA, DENALI_PHY_46_DATA, DENALI_PHY_47_DATA, DENALI_PHY_48_DATA, DENALI_PHY_49_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@14 PS1, Line 14: DENALI_PHY_50_DATA, DENALI_PHY_51_DATA, DENALI_PHY_52_DATA, DENALI_PHY_53_DATA, DENALI_PHY_54_DATA, DENALI_PHY_55_DATA, DENALI_PHY_56_DATA, DENALI_PHY_57_DATA, DENALI_PHY_58_DATA, DENALI_PHY_59_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@15 PS1, Line 15: DENALI_PHY_60_DATA, DENALI_PHY_61_DATA, DENALI_PHY_62_DATA, DENALI_PHY_63_DATA, DENALI_PHY_64_DATA, DENALI_PHY_65_DATA, DENALI_PHY_66_DATA, DENALI_PHY_67_DATA, DENALI_PHY_68_DATA, DENALI_PHY_69_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@16 PS1, Line 16: DENALI_PHY_70_DATA, DENALI_PHY_71_DATA, DENALI_PHY_72_DATA, DENALI_PHY_73_DATA, DENALI_PHY_74_DATA, DENALI_PHY_75_DATA, DENALI_PHY_76_DATA, DENALI_PHY_77_DATA, DENALI_PHY_78_DATA, DENALI_PHY_79_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@17 PS1, Line 17: DENALI_PHY_80_DATA, DENALI_PHY_81_DATA, DENALI_PHY_82_DATA, DENALI_PHY_83_DATA, DENALI_PHY_84_DATA, DENALI_PHY_85_DATA, DENALI_PHY_86_DATA, DENALI_PHY_87_DATA, DENALI_PHY_88_DATA, DENALI_PHY_89_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@18 PS1, Line 18: DENALI_PHY_90_DATA, DENALI_PHY_91_DATA, DENALI_PHY_92_DATA, DENALI_PHY_93_DATA, DENALI_PHY_94_DATA, DENALI_PHY_95_DATA, DENALI_PHY_96_DATA, DENALI_PHY_97_DATA, DENALI_PHY_98_DATA, DENALI_PHY_99_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@20 PS1, Line 20: DENALI_PHY_100_DATA, DENALI_PHY_101_DATA, DENALI_PHY_102_DATA, DENALI_PHY_103_DATA, DENALI_PHY_104_DATA, DENALI_PHY_105_DATA, DENALI_PHY_106_DATA, DENALI_PHY_107_DATA, DENALI_PHY_108_DATA, DENALI_PHY_109_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@21 PS1, Line 21: DENALI_PHY_110_DATA, DENALI_PHY_111_DATA, DENALI_PHY_112_DATA, DENALI_PHY_113_DATA, DENALI_PHY_114_DATA, DENALI_PHY_115_DATA, DENALI_PHY_116_DATA, DENALI_PHY_117_DATA, DENALI_PHY_118_DATA, DENALI_PHY_119_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@22 PS1, Line 22: DENALI_PHY_120_DATA, DENALI_PHY_121_DATA, DENALI_PHY_122_DATA, DENALI_PHY_123_DATA, DENALI_PHY_124_DATA, DENALI_PHY_125_DATA, DENALI_PHY_126_DATA, DENALI_PHY_127_DATA, DENALI_PHY_128_DATA, DENALI_PHY_129_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@23 PS1, Line 23: DENALI_PHY_130_DATA, DENALI_PHY_131_DATA, DENALI_PHY_132_DATA, DENALI_PHY_133_DATA, DENALI_PHY_134_DATA, DENALI_PHY_135_DATA, DENALI_PHY_136_DATA, DENALI_PHY_137_DATA, DENALI_PHY_138_DATA, DENALI_PHY_139_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@24 PS1, Line 24: DENALI_PHY_140_DATA, DENALI_PHY_141_DATA, DENALI_PHY_142_DATA, DENALI_PHY_143_DATA, DENALI_PHY_144_DATA, DENALI_PHY_145_DATA, DENALI_PHY_146_DATA, DENALI_PHY_147_DATA, DENALI_PHY_148_DATA, DENALI_PHY_149_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@25 PS1, Line 25: DENALI_PHY_150_DATA, DENALI_PHY_151_DATA, DENALI_PHY_152_DATA, DENALI_PHY_153_DATA, DENALI_PHY_154_DATA, DENALI_PHY_155_DATA, DENALI_PHY_156_DATA, DENALI_PHY_157_DATA, DENALI_PHY_158_DATA, DENALI_PHY_159_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@26 PS1, Line 26: DENALI_PHY_160_DATA, DENALI_PHY_161_DATA, DENALI_PHY_162_DATA, DENALI_PHY_163_DATA, DENALI_PHY_164_DATA, DENALI_PHY_165_DATA, DENALI_PHY_166_DATA, DENALI_PHY_167_DATA, DENALI_PHY_168_DATA, DENALI_PHY_169_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@27 PS1, Line 27: DENALI_PHY_170_DATA, DENALI_PHY_171_DATA, DENALI_PHY_172_DATA, DENALI_PHY_173_DATA, DENALI_PHY_174_DATA, DENALI_PHY_175_DATA, DENALI_PHY_176_DATA, DENALI_PHY_177_DATA, DENALI_PHY_178_DATA, DENALI_PHY_179_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@28 PS1, Line 28: DENALI_PHY_180_DATA, DENALI_PHY_181_DATA, DENALI_PHY_182_DATA, DENALI_PHY_183_DATA, DENALI_PHY_184_DATA, DENALI_PHY_185_DATA, DENALI_PHY_186_DATA, DENALI_PHY_187_DATA, DENALI_PHY_188_DATA, DENALI_PHY_189_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@29 PS1, Line 29: DENALI_PHY_190_DATA, DENALI_PHY_191_DATA, DENALI_PHY_192_DATA, DENALI_PHY_193_DATA, DENALI_PHY_194_DATA, DENALI_PHY_195_DATA, DENALI_PHY_196_DATA, DENALI_PHY_197_DATA, DENALI_PHY_198_DATA, DENALI_PHY_199_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@31 PS1, Line 31: DENALI_PHY_200_DATA, DENALI_PHY_201_DATA, DENALI_PHY_202_DATA, DENALI_PHY_203_DATA, DENALI_PHY_204_DATA, DENALI_PHY_205_DATA, DENALI_PHY_206_DATA, DENALI_PHY_207_DATA, DENALI_PHY_208_DATA, DENALI_PHY_209_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@32 PS1, Line 32: DENALI_PHY_210_DATA, DENALI_PHY_211_DATA, DENALI_PHY_212_DATA, DENALI_PHY_213_DATA, DENALI_PHY_214_DATA, DENALI_PHY_215_DATA, DENALI_PHY_216_DATA, DENALI_PHY_217_DATA, DENALI_PHY_218_DATA, DENALI_PHY_219_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@33 PS1, Line 33: DENALI_PHY_220_DATA, DENALI_PHY_221_DATA, DENALI_PHY_222_DATA, DENALI_PHY_223_DATA, DENALI_PHY_224_DATA, DENALI_PHY_225_DATA, DENALI_PHY_226_DATA, DENALI_PHY_227_DATA, DENALI_PHY_228_DATA, DENALI_PHY_229_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@34 PS1, Line 34: DENALI_PHY_230_DATA, DENALI_PHY_231_DATA, DENALI_PHY_232_DATA, DENALI_PHY_233_DATA, DENALI_PHY_234_DATA, DENALI_PHY_235_DATA, DENALI_PHY_236_DATA, DENALI_PHY_237_DATA, DENALI_PHY_238_DATA, DENALI_PHY_239_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@35 PS1, Line 35: DENALI_PHY_240_DATA, DENALI_PHY_241_DATA, DENALI_PHY_242_DATA, DENALI_PHY_243_DATA, DENALI_PHY_244_DATA, DENALI_PHY_245_DATA, DENALI_PHY_246_DATA, DENALI_PHY_247_DATA, DENALI_PHY_248_DATA, DENALI_PHY_249_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@36 PS1, Line 36: DENALI_PHY_250_DATA, DENALI_PHY_251_DATA, DENALI_PHY_252_DATA, DENALI_PHY_253_DATA, DENALI_PHY_254_DATA, DENALI_PHY_255_DATA, DENALI_PHY_256_DATA, DENALI_PHY_257_DATA, DENALI_PHY_258_DATA, DENALI_PHY_259_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@37 PS1, Line 37: DENALI_PHY_260_DATA, DENALI_PHY_261_DATA, DENALI_PHY_262_DATA, DENALI_PHY_263_DATA, DENALI_PHY_264_DATA, DENALI_PHY_265_DATA, DENALI_PHY_266_DATA, DENALI_PHY_267_DATA, DENALI_PHY_268_DATA, DENALI_PHY_269_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@38 PS1, Line 38: DENALI_PHY_270_DATA, DENALI_PHY_271_DATA, DENALI_PHY_272_DATA, DENALI_PHY_273_DATA, DENALI_PHY_274_DATA, DENALI_PHY_275_DATA, DENALI_PHY_276_DATA, DENALI_PHY_277_DATA, DENALI_PHY_278_DATA, DENALI_PHY_279_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@39 PS1, Line 39: DENALI_PHY_280_DATA, DENALI_PHY_281_DATA, DENALI_PHY_282_DATA, DENALI_PHY_283_DATA, DENALI_PHY_284_DATA, DENALI_PHY_285_DATA, DENALI_PHY_286_DATA, DENALI_PHY_287_DATA, DENALI_PHY_288_DATA, DENALI_PHY_289_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@40 PS1, Line 40: DENALI_PHY_290_DATA, DENALI_PHY_291_DATA, DENALI_PHY_292_DATA, DENALI_PHY_293_DATA, DENALI_PHY_294_DATA, DENALI_PHY_295_DATA, DENALI_PHY_296_DATA, DENALI_PHY_297_DATA, DENALI_PHY_298_DATA, DENALI_PHY_299_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@42 PS1, Line 42: DENALI_PHY_300_DATA, DENALI_PHY_301_DATA, DENALI_PHY_302_DATA, DENALI_PHY_303_DATA, DENALI_PHY_304_DATA, DENALI_PHY_305_DATA, DENALI_PHY_306_DATA, DENALI_PHY_307_DATA, DENALI_PHY_308_DATA, DENALI_PHY_309_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@43 PS1, Line 43: DENALI_PHY_310_DATA, DENALI_PHY_311_DATA, DENALI_PHY_312_DATA, DENALI_PHY_313_DATA, DENALI_PHY_314_DATA, DENALI_PHY_315_DATA, DENALI_PHY_316_DATA, DENALI_PHY_317_DATA, DENALI_PHY_318_DATA, DENALI_PHY_319_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@44 PS1, Line 44: DENALI_PHY_320_DATA, DENALI_PHY_321_DATA, DENALI_PHY_322_DATA, DENALI_PHY_323_DATA, DENALI_PHY_324_DATA, DENALI_PHY_325_DATA, DENALI_PHY_326_DATA, DENALI_PHY_327_DATA, DENALI_PHY_328_DATA, DENALI_PHY_329_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@45 PS1, Line 45: DENALI_PHY_330_DATA, DENALI_PHY_331_DATA, DENALI_PHY_332_DATA, DENALI_PHY_333_DATA, DENALI_PHY_334_DATA, DENALI_PHY_335_DATA, DENALI_PHY_336_DATA, DENALI_PHY_337_DATA, DENALI_PHY_338_DATA, DENALI_PHY_339_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@46 PS1, Line 46: DENALI_PHY_340_DATA, DENALI_PHY_341_DATA, DENALI_PHY_342_DATA, DENALI_PHY_343_DATA, DENALI_PHY_344_DATA, DENALI_PHY_345_DATA, DENALI_PHY_346_DATA, DENALI_PHY_347_DATA, DENALI_PHY_348_DATA, DENALI_PHY_349_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@47 PS1, Line 47: DENALI_PHY_350_DATA, DENALI_PHY_351_DATA, DENALI_PHY_352_DATA, DENALI_PHY_353_DATA, DENALI_PHY_354_DATA, DENALI_PHY_355_DATA, DENALI_PHY_356_DATA, DENALI_PHY_357_DATA, DENALI_PHY_358_DATA, DENALI_PHY_359_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@48 PS1, Line 48: DENALI_PHY_360_DATA, DENALI_PHY_361_DATA, DENALI_PHY_362_DATA, DENALI_PHY_363_DATA, DENALI_PHY_364_DATA, DENALI_PHY_365_DATA, DENALI_PHY_366_DATA, DENALI_PHY_367_DATA, DENALI_PHY_368_DATA, DENALI_PHY_369_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@49 PS1, Line 49: DENALI_PHY_370_DATA, DENALI_PHY_371_DATA, DENALI_PHY_372_DATA, DENALI_PHY_373_DATA, DENALI_PHY_374_DATA, DENALI_PHY_375_DATA, DENALI_PHY_376_DATA, DENALI_PHY_377_DATA, DENALI_PHY_378_DATA, DENALI_PHY_379_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@50 PS1, Line 50: DENALI_PHY_380_DATA, DENALI_PHY_381_DATA, DENALI_PHY_382_DATA, DENALI_PHY_383_DATA, DENALI_PHY_384_DATA, DENALI_PHY_385_DATA, DENALI_PHY_386_DATA, DENALI_PHY_387_DATA, DENALI_PHY_388_DATA, DENALI_PHY_389_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@51 PS1, Line 51: DENALI_PHY_390_DATA, DENALI_PHY_391_DATA, DENALI_PHY_392_DATA, DENALI_PHY_393_DATA, DENALI_PHY_394_DATA, DENALI_PHY_395_DATA, DENALI_PHY_396_DATA, DENALI_PHY_397_DATA, DENALI_PHY_398_DATA, DENALI_PHY_399_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@53 PS1, Line 53: DENALI_PHY_400_DATA, DENALI_PHY_401_DATA, DENALI_PHY_402_DATA, DENALI_PHY_403_DATA, DENALI_PHY_404_DATA, DENALI_PHY_405_DATA, DENALI_PHY_406_DATA, DENALI_PHY_407_DATA, DENALI_PHY_408_DATA, DENALI_PHY_409_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@54 PS1, Line 54: DENALI_PHY_410_DATA, DENALI_PHY_411_DATA, DENALI_PHY_412_DATA, DENALI_PHY_413_DATA, DENALI_PHY_414_DATA, DENALI_PHY_415_DATA, DENALI_PHY_416_DATA, DENALI_PHY_417_DATA, DENALI_PHY_418_DATA, DENALI_PHY_419_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@55 PS1, Line 55: DENALI_PHY_420_DATA, DENALI_PHY_421_DATA, DENALI_PHY_422_DATA, DENALI_PHY_423_DATA, DENALI_PHY_424_DATA, DENALI_PHY_425_DATA, DENALI_PHY_426_DATA, DENALI_PHY_427_DATA, DENALI_PHY_428_DATA, DENALI_PHY_429_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@56 PS1, Line 56: DENALI_PHY_430_DATA, DENALI_PHY_431_DATA, DENALI_PHY_432_DATA, DENALI_PHY_433_DATA, DENALI_PHY_434_DATA, DENALI_PHY_435_DATA, DENALI_PHY_436_DATA, DENALI_PHY_437_DATA, DENALI_PHY_438_DATA, DENALI_PHY_439_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@57 PS1, Line 57: DENALI_PHY_440_DATA, DENALI_PHY_441_DATA, DENALI_PHY_442_DATA, DENALI_PHY_443_DATA, DENALI_PHY_444_DATA, DENALI_PHY_445_DATA, DENALI_PHY_446_DATA, DENALI_PHY_447_DATA, DENALI_PHY_448_DATA, DENALI_PHY_449_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@58 PS1, Line 58: DENALI_PHY_450_DATA, DENALI_PHY_451_DATA, DENALI_PHY_452_DATA, DENALI_PHY_453_DATA, DENALI_PHY_454_DATA, DENALI_PHY_455_DATA, DENALI_PHY_456_DATA, DENALI_PHY_457_DATA, DENALI_PHY_458_DATA, DENALI_PHY_459_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@59 PS1, Line 59: DENALI_PHY_460_DATA, DENALI_PHY_461_DATA, DENALI_PHY_462_DATA, DENALI_PHY_463_DATA, DENALI_PHY_464_DATA, DENALI_PHY_465_DATA, DENALI_PHY_466_DATA, DENALI_PHY_467_DATA, DENALI_PHY_468_DATA, DENALI_PHY_469_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@60 PS1, Line 60: DENALI_PHY_470_DATA, DENALI_PHY_471_DATA, DENALI_PHY_472_DATA, DENALI_PHY_473_DATA, DENALI_PHY_474_DATA, DENALI_PHY_475_DATA, DENALI_PHY_476_DATA, DENALI_PHY_477_DATA, DENALI_PHY_478_DATA, DENALI_PHY_479_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@61 PS1, Line 61: DENALI_PHY_480_DATA, DENALI_PHY_481_DATA, DENALI_PHY_482_DATA, DENALI_PHY_483_DATA, DENALI_PHY_484_DATA, DENALI_PHY_485_DATA, DENALI_PHY_486_DATA, DENALI_PHY_487_DATA, DENALI_PHY_488_DATA, DENALI_PHY_489_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@62 PS1, Line 62: DENALI_PHY_490_DATA, DENALI_PHY_491_DATA, DENALI_PHY_492_DATA, DENALI_PHY_493_DATA, DENALI_PHY_494_DATA, DENALI_PHY_495_DATA, DENALI_PHY_496_DATA, DENALI_PHY_497_DATA, DENALI_PHY_498_DATA, DENALI_PHY_499_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@64 PS1, Line 64: DENALI_PHY_500_DATA, DENALI_PHY_501_DATA, DENALI_PHY_502_DATA, DENALI_PHY_503_DATA, DENALI_PHY_504_DATA, DENALI_PHY_505_DATA, DENALI_PHY_506_DATA, DENALI_PHY_507_DATA, DENALI_PHY_508_DATA, DENALI_PHY_509_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@65 PS1, Line 65: DENALI_PHY_510_DATA, DENALI_PHY_511_DATA, DENALI_PHY_512_DATA, DENALI_PHY_513_DATA, DENALI_PHY_514_DATA, DENALI_PHY_515_DATA, DENALI_PHY_516_DATA, DENALI_PHY_517_DATA, DENALI_PHY_518_DATA, DENALI_PHY_519_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@66 PS1, Line 66: DENALI_PHY_520_DATA, DENALI_PHY_521_DATA, DENALI_PHY_522_DATA, DENALI_PHY_523_DATA, DENALI_PHY_524_DATA, DENALI_PHY_525_DATA, DENALI_PHY_526_DATA, DENALI_PHY_527_DATA, DENALI_PHY_528_DATA, DENALI_PHY_529_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@67 PS1, Line 67: DENALI_PHY_530_DATA, DENALI_PHY_531_DATA, DENALI_PHY_532_DATA, DENALI_PHY_533_DATA, DENALI_PHY_534_DATA, DENALI_PHY_535_DATA, DENALI_PHY_536_DATA, DENALI_PHY_537_DATA, DENALI_PHY_538_DATA, DENALI_PHY_539_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@68 PS1, Line 68: DENALI_PHY_540_DATA, DENALI_PHY_541_DATA, DENALI_PHY_542_DATA, DENALI_PHY_543_DATA, DENALI_PHY_544_DATA, DENALI_PHY_545_DATA, DENALI_PHY_546_DATA, DENALI_PHY_547_DATA, DENALI_PHY_548_DATA, DENALI_PHY_549_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@69 PS1, Line 69: DENALI_PHY_550_DATA, DENALI_PHY_551_DATA, DENALI_PHY_552_DATA, DENALI_PHY_553_DATA, DENALI_PHY_554_DATA, DENALI_PHY_555_DATA, DENALI_PHY_556_DATA, DENALI_PHY_557_DATA, DENALI_PHY_558_DATA, DENALI_PHY_559_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@70 PS1, Line 70: DENALI_PHY_560_DATA, DENALI_PHY_561_DATA, DENALI_PHY_562_DATA, DENALI_PHY_563_DATA, DENALI_PHY_564_DATA, DENALI_PHY_565_DATA, DENALI_PHY_566_DATA, DENALI_PHY_567_DATA, DENALI_PHY_568_DATA, DENALI_PHY_569_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@71 PS1, Line 71: DENALI_PHY_570_DATA, DENALI_PHY_571_DATA, DENALI_PHY_572_DATA, DENALI_PHY_573_DATA, DENALI_PHY_574_DATA, DENALI_PHY_575_DATA, DENALI_PHY_576_DATA, DENALI_PHY_577_DATA, DENALI_PHY_578_DATA, DENALI_PHY_579_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@72 PS1, Line 72: DENALI_PHY_580_DATA, DENALI_PHY_581_DATA, DENALI_PHY_582_DATA, DENALI_PHY_583_DATA, DENALI_PHY_584_DATA, DENALI_PHY_585_DATA, DENALI_PHY_586_DATA, DENALI_PHY_587_DATA, DENALI_PHY_588_DATA, DENALI_PHY_589_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@73 PS1, Line 73: DENALI_PHY_590_DATA, DENALI_PHY_591_DATA, DENALI_PHY_592_DATA, DENALI_PHY_593_DATA, DENALI_PHY_594_DATA, DENALI_PHY_595_DATA, DENALI_PHY_596_DATA, DENALI_PHY_597_DATA, DENALI_PHY_598_DATA, DENALI_PHY_599_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@75 PS1, Line 75: DENALI_PHY_600_DATA, DENALI_PHY_601_DATA, DENALI_PHY_602_DATA, DENALI_PHY_603_DATA, DENALI_PHY_604_DATA, DENALI_PHY_605_DATA, DENALI_PHY_606_DATA, DENALI_PHY_607_DATA, DENALI_PHY_608_DATA, DENALI_PHY_609_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@76 PS1, Line 76: DENALI_PHY_610_DATA, DENALI_PHY_611_DATA, DENALI_PHY_612_DATA, DENALI_PHY_613_DATA, DENALI_PHY_614_DATA, DENALI_PHY_615_DATA, DENALI_PHY_616_DATA, DENALI_PHY_617_DATA, DENALI_PHY_618_DATA, DENALI_PHY_619_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@77 PS1, Line 77: DENALI_PHY_620_DATA, DENALI_PHY_621_DATA, DENALI_PHY_622_DATA, DENALI_PHY_623_DATA, DENALI_PHY_624_DATA, DENALI_PHY_625_DATA, DENALI_PHY_626_DATA, DENALI_PHY_627_DATA, DENALI_PHY_628_DATA, DENALI_PHY_629_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@78 PS1, Line 78: DENALI_PHY_630_DATA, DENALI_PHY_631_DATA, DENALI_PHY_632_DATA, DENALI_PHY_633_DATA, DENALI_PHY_634_DATA, DENALI_PHY_635_DATA, DENALI_PHY_636_DATA, DENALI_PHY_637_DATA, DENALI_PHY_638_DATA, DENALI_PHY_639_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@79 PS1, Line 79: DENALI_PHY_640_DATA, DENALI_PHY_641_DATA, DENALI_PHY_642_DATA, DENALI_PHY_643_DATA, DENALI_PHY_644_DATA, DENALI_PHY_645_DATA, DENALI_PHY_646_DATA, DENALI_PHY_647_DATA, DENALI_PHY_648_DATA, DENALI_PHY_649_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@80 PS1, Line 80: DENALI_PHY_650_DATA, DENALI_PHY_651_DATA, DENALI_PHY_652_DATA, DENALI_PHY_653_DATA, DENALI_PHY_654_DATA, DENALI_PHY_655_DATA, DENALI_PHY_656_DATA, DENALI_PHY_657_DATA, DENALI_PHY_658_DATA, DENALI_PHY_659_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@81 PS1, Line 81: DENALI_PHY_660_DATA, DENALI_PHY_661_DATA, DENALI_PHY_662_DATA, DENALI_PHY_663_DATA, DENALI_PHY_664_DATA, DENALI_PHY_665_DATA, DENALI_PHY_666_DATA, DENALI_PHY_667_DATA, DENALI_PHY_668_DATA, DENALI_PHY_669_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@82 PS1, Line 82: DENALI_PHY_670_DATA, DENALI_PHY_671_DATA, DENALI_PHY_672_DATA, DENALI_PHY_673_DATA, DENALI_PHY_674_DATA, DENALI_PHY_675_DATA, DENALI_PHY_676_DATA, DENALI_PHY_677_DATA, DENALI_PHY_678_DATA, DENALI_PHY_679_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@83 PS1, Line 83: DENALI_PHY_680_DATA, DENALI_PHY_681_DATA, DENALI_PHY_682_DATA, DENALI_PHY_683_DATA, DENALI_PHY_684_DATA, DENALI_PHY_685_DATA, DENALI_PHY_686_DATA, DENALI_PHY_687_DATA, DENALI_PHY_688_DATA, DENALI_PHY_689_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@84 PS1, Line 84: DENALI_PHY_690_DATA, DENALI_PHY_691_DATA, DENALI_PHY_692_DATA, DENALI_PHY_693_DATA, DENALI_PHY_694_DATA, DENALI_PHY_695_DATA, DENALI_PHY_696_DATA, DENALI_PHY_697_DATA, DENALI_PHY_698_DATA, DENALI_PHY_699_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@86 PS1, Line 86: DENALI_PHY_700_DATA, DENALI_PHY_701_DATA, DENALI_PHY_702_DATA, DENALI_PHY_703_DATA, DENALI_PHY_704_DATA, DENALI_PHY_705_DATA, DENALI_PHY_706_DATA, DENALI_PHY_707_DATA, DENALI_PHY_708_DATA, DENALI_PHY_709_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@87 PS1, Line 87: DENALI_PHY_710_DATA, DENALI_PHY_711_DATA, DENALI_PHY_712_DATA, DENALI_PHY_713_DATA, DENALI_PHY_714_DATA, DENALI_PHY_715_DATA, DENALI_PHY_716_DATA, DENALI_PHY_717_DATA, DENALI_PHY_718_DATA, DENALI_PHY_719_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@88 PS1, Line 88: DENALI_PHY_720_DATA, DENALI_PHY_721_DATA, DENALI_PHY_722_DATA, DENALI_PHY_723_DATA, DENALI_PHY_724_DATA, DENALI_PHY_725_DATA, DENALI_PHY_726_DATA, DENALI_PHY_727_DATA, DENALI_PHY_728_DATA, DENALI_PHY_729_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@89 PS1, Line 89: DENALI_PHY_730_DATA, DENALI_PHY_731_DATA, DENALI_PHY_732_DATA, DENALI_PHY_733_DATA, DENALI_PHY_734_DATA, DENALI_PHY_735_DATA, DENALI_PHY_736_DATA, DENALI_PHY_737_DATA, DENALI_PHY_738_DATA, DENALI_PHY_739_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@90 PS1, Line 90: DENALI_PHY_740_DATA, DENALI_PHY_741_DATA, DENALI_PHY_742_DATA, DENALI_PHY_743_DATA, DENALI_PHY_744_DATA, DENALI_PHY_745_DATA, DENALI_PHY_746_DATA, DENALI_PHY_747_DATA, DENALI_PHY_748_DATA, DENALI_PHY_749_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@91 PS1, Line 91: DENALI_PHY_750_DATA, DENALI_PHY_751_DATA, DENALI_PHY_752_DATA, DENALI_PHY_753_DATA, DENALI_PHY_754_DATA, DENALI_PHY_755_DATA, DENALI_PHY_756_DATA, DENALI_PHY_757_DATA, DENALI_PHY_758_DATA, DENALI_PHY_759_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@92 PS1, Line 92: DENALI_PHY_760_DATA, DENALI_PHY_761_DATA, DENALI_PHY_762_DATA, DENALI_PHY_763_DATA, DENALI_PHY_764_DATA, DENALI_PHY_765_DATA, DENALI_PHY_766_DATA, DENALI_PHY_767_DATA, DENALI_PHY_768_DATA, DENALI_PHY_769_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@93 PS1, Line 93: DENALI_PHY_770_DATA, DENALI_PHY_771_DATA, DENALI_PHY_772_DATA, DENALI_PHY_773_DATA, DENALI_PHY_774_DATA, DENALI_PHY_775_DATA, DENALI_PHY_776_DATA, DENALI_PHY_777_DATA, DENALI_PHY_778_DATA, DENALI_PHY_779_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@94 PS1, Line 94: DENALI_PHY_780_DATA, DENALI_PHY_781_DATA, DENALI_PHY_782_DATA, DENALI_PHY_783_DATA, DENALI_PHY_784_DATA, DENALI_PHY_785_DATA, DENALI_PHY_786_DATA, DENALI_PHY_787_DATA, DENALI_PHY_788_DATA, DENALI_PHY_789_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@95 PS1, Line 95: DENALI_PHY_790_DATA, DENALI_PHY_791_DATA, DENALI_PHY_792_DATA, DENALI_PHY_793_DATA, DENALI_PHY_794_DATA, DENALI_PHY_795_DATA, DENALI_PHY_796_DATA, DENALI_PHY_797_DATA, DENALI_PHY_798_DATA, DENALI_PHY_799_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@97 PS1, Line 97: DENALI_PHY_800_DATA, DENALI_PHY_801_DATA, DENALI_PHY_802_DATA, DENALI_PHY_803_DATA, DENALI_PHY_804_DATA, DENALI_PHY_805_DATA, DENALI_PHY_806_DATA, DENALI_PHY_807_DATA, DENALI_PHY_808_DATA, DENALI_PHY_809_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@98 PS1, Line 98: DENALI_PHY_810_DATA, DENALI_PHY_811_DATA, DENALI_PHY_812_DATA, DENALI_PHY_813_DATA, DENALI_PHY_814_DATA, DENALI_PHY_815_DATA, DENALI_PHY_816_DATA, DENALI_PHY_817_DATA, DENALI_PHY_818_DATA, DENALI_PHY_819_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@99 PS1, Line 99: DENALI_PHY_820_DATA, DENALI_PHY_821_DATA, DENALI_PHY_822_DATA, DENALI_PHY_823_DATA, DENALI_PHY_824_DATA, DENALI_PHY_825_DATA, DENALI_PHY_826_DATA, DENALI_PHY_827_DATA, DENALI_PHY_828_DATA, DENALI_PHY_829_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@100 PS1, Line 100: DENALI_PHY_830_DATA, DENALI_PHY_831_DATA, DENALI_PHY_832_DATA, DENALI_PHY_833_DATA, DENALI_PHY_834_DATA, DENALI_PHY_835_DATA, DENALI_PHY_836_DATA, DENALI_PHY_837_DATA, DENALI_PHY_838_DATA, DENALI_PHY_839_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@101 PS1, Line 101: DENALI_PHY_840_DATA, DENALI_PHY_841_DATA, DENALI_PHY_842_DATA, DENALI_PHY_843_DATA, DENALI_PHY_844_DATA, DENALI_PHY_845_DATA, DENALI_PHY_846_DATA, DENALI_PHY_847_DATA, DENALI_PHY_848_DATA, DENALI_PHY_849_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@102 PS1, Line 102: DENALI_PHY_850_DATA, DENALI_PHY_851_DATA, DENALI_PHY_852_DATA, DENALI_PHY_853_DATA, DENALI_PHY_854_DATA, DENALI_PHY_855_DATA, DENALI_PHY_856_DATA, DENALI_PHY_857_DATA, DENALI_PHY_858_DATA, DENALI_PHY_859_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@103 PS1, Line 103: DENALI_PHY_860_DATA, DENALI_PHY_861_DATA, DENALI_PHY_862_DATA, DENALI_PHY_863_DATA, DENALI_PHY_864_DATA, DENALI_PHY_865_DATA, DENALI_PHY_866_DATA, DENALI_PHY_867_DATA, DENALI_PHY_868_DATA, DENALI_PHY_869_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@104 PS1, Line 104: DENALI_PHY_870_DATA, DENALI_PHY_871_DATA, DENALI_PHY_872_DATA, DENALI_PHY_873_DATA, DENALI_PHY_874_DATA, DENALI_PHY_875_DATA, DENALI_PHY_876_DATA, DENALI_PHY_877_DATA, DENALI_PHY_878_DATA, DENALI_PHY_879_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@105 PS1, Line 105: DENALI_PHY_880_DATA, DENALI_PHY_881_DATA, DENALI_PHY_882_DATA, DENALI_PHY_883_DATA, DENALI_PHY_884_DATA, DENALI_PHY_885_DATA, DENALI_PHY_886_DATA, DENALI_PHY_887_DATA, DENALI_PHY_888_DATA, DENALI_PHY_889_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@106 PS1, Line 106: DENALI_PHY_890_DATA, DENALI_PHY_891_DATA, DENALI_PHY_892_DATA, DENALI_PHY_893_DATA, DENALI_PHY_894_DATA, DENALI_PHY_895_DATA, DENALI_PHY_896_DATA, DENALI_PHY_897_DATA, DENALI_PHY_898_DATA, DENALI_PHY_899_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@108 PS1, Line 108: DENALI_PHY_900_DATA, DENALI_PHY_901_DATA, DENALI_PHY_902_DATA, DENALI_PHY_903_DATA, DENALI_PHY_904_DATA, DENALI_PHY_905_DATA, DENALI_PHY_906_DATA, DENALI_PHY_907_DATA, DENALI_PHY_908_DATA, DENALI_PHY_909_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@109 PS1, Line 109: DENALI_PHY_910_DATA, DENALI_PHY_911_DATA, DENALI_PHY_912_DATA, DENALI_PHY_913_DATA, DENALI_PHY_914_DATA, DENALI_PHY_915_DATA, DENALI_PHY_916_DATA, DENALI_PHY_917_DATA, DENALI_PHY_918_DATA, DENALI_PHY_919_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@110 PS1, Line 110: DENALI_PHY_920_DATA, DENALI_PHY_921_DATA, DENALI_PHY_922_DATA, DENALI_PHY_923_DATA, DENALI_PHY_924_DATA, DENALI_PHY_925_DATA, DENALI_PHY_926_DATA, DENALI_PHY_927_DATA, DENALI_PHY_928_DATA, DENALI_PHY_929_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@111 PS1, Line 111: DENALI_PHY_930_DATA, DENALI_PHY_931_DATA, DENALI_PHY_932_DATA, DENALI_PHY_933_DATA, DENALI_PHY_934_DATA, DENALI_PHY_935_DATA, DENALI_PHY_936_DATA, DENALI_PHY_937_DATA, DENALI_PHY_938_DATA, DENALI_PHY_939_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@112 PS1, Line 112: DENALI_PHY_940_DATA, DENALI_PHY_941_DATA, DENALI_PHY_942_DATA, DENALI_PHY_943_DATA, DENALI_PHY_944_DATA, DENALI_PHY_945_DATA, DENALI_PHY_946_DATA, DENALI_PHY_947_DATA, DENALI_PHY_948_DATA, DENALI_PHY_949_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@113 PS1, Line 113: DENALI_PHY_950_DATA, DENALI_PHY_951_DATA, DENALI_PHY_952_DATA, DENALI_PHY_953_DATA, DENALI_PHY_954_DATA, DENALI_PHY_955_DATA, DENALI_PHY_956_DATA, DENALI_PHY_957_DATA, DENALI_PHY_958_DATA, DENALI_PHY_959_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@114 PS1, Line 114: DENALI_PHY_960_DATA, DENALI_PHY_961_DATA, DENALI_PHY_962_DATA, DENALI_PHY_963_DATA, DENALI_PHY_964_DATA, DENALI_PHY_965_DATA, DENALI_PHY_966_DATA, DENALI_PHY_967_DATA, DENALI_PHY_968_DATA, DENALI_PHY_969_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@115 PS1, Line 115: DENALI_PHY_970_DATA, DENALI_PHY_971_DATA, DENALI_PHY_972_DATA, DENALI_PHY_973_DATA, DENALI_PHY_974_DATA, DENALI_PHY_975_DATA, DENALI_PHY_976_DATA, DENALI_PHY_977_DATA, DENALI_PHY_978_DATA, DENALI_PHY_979_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@116 PS1, Line 116: DENALI_PHY_980_DATA, DENALI_PHY_981_DATA, DENALI_PHY_982_DATA, DENALI_PHY_983_DATA, DENALI_PHY_984_DATA, DENALI_PHY_985_DATA, DENALI_PHY_986_DATA, DENALI_PHY_987_DATA, DENALI_PHY_988_DATA, DENALI_PHY_989_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@117 PS1, Line 117: DENALI_PHY_990_DATA, DENALI_PHY_991_DATA, DENALI_PHY_992_DATA, DENALI_PHY_993_DATA, DENALI_PHY_994_DATA, DENALI_PHY_995_DATA, DENALI_PHY_996_DATA, DENALI_PHY_997_DATA, DENALI_PHY_998_DATA, DENALI_PHY_999_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@119 PS1, Line 119: DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA, DENALI_PHY_1002_DATA, DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA, DENALI_PHY_1005_DATA, DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA, DENALI_PHY_1008_DATA, DENALI_PHY_1009_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@120 PS1, Line 120: DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA, DENALI_PHY_1012_DATA, DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA, DENALI_PHY_1015_DATA, DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA, DENALI_PHY_1018_DATA, DENALI_PHY_1019_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@121 PS1, Line 121: DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA, DENALI_PHY_1022_DATA, DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA, DENALI_PHY_1025_DATA, DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA, DENALI_PHY_1028_DATA, DENALI_PHY_1029_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@122 PS1, Line 122: DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA, DENALI_PHY_1032_DATA, DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA, DENALI_PHY_1035_DATA, DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA, DENALI_PHY_1038_DATA, DENALI_PHY_1039_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@123 PS1, Line 123: DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA, DENALI_PHY_1042_DATA, DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA, DENALI_PHY_1045_DATA, DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA, DENALI_PHY_1048_DATA, DENALI_PHY_1049_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@124 PS1, Line 124: DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA, DENALI_PHY_1052_DATA, DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA, DENALI_PHY_1055_DATA, DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA, DENALI_PHY_1058_DATA, DENALI_PHY_1059_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@125 PS1, Line 125: DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA, DENALI_PHY_1062_DATA, DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA, DENALI_PHY_1065_DATA, DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA, DENALI_PHY_1068_DATA, DENALI_PHY_1069_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@126 PS1, Line 126: DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA, DENALI_PHY_1072_DATA, DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA, DENALI_PHY_1075_DATA, DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA, DENALI_PHY_1078_DATA, DENALI_PHY_1079_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@127 PS1, Line 127: DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA, DENALI_PHY_1082_DATA, DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA, DENALI_PHY_1085_DATA, DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA, DENALI_PHY_1088_DATA, DENALI_PHY_1089_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@128 PS1, Line 128: DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA, DENALI_PHY_1092_DATA, DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA, DENALI_PHY_1095_DATA, DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA, DENALI_PHY_1098_DATA, DENALI_PHY_1099_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@130 PS1, Line 130: DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA, DENALI_PHY_1102_DATA, DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA, DENALI_PHY_1105_DATA, DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA, DENALI_PHY_1108_DATA, DENALI_PHY_1109_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@131 PS1, Line 131: DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA, DENALI_PHY_1112_DATA, DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA, DENALI_PHY_1115_DATA, DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA, DENALI_PHY_1118_DATA, DENALI_PHY_1119_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@132 PS1, Line 132: DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA, DENALI_PHY_1122_DATA, DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA, DENALI_PHY_1125_DATA, DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA, DENALI_PHY_1128_DATA, DENALI_PHY_1129_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@133 PS1, Line 133: DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA, DENALI_PHY_1132_DATA, DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA, DENALI_PHY_1135_DATA, DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA, DENALI_PHY_1138_DATA, DENALI_PHY_1139_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@134 PS1, Line 134: DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA, DENALI_PHY_1142_DATA, DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA, DENALI_PHY_1145_DATA, DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA, DENALI_PHY_1148_DATA, DENALI_PHY_1149_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@135 PS1, Line 135: DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA, DENALI_PHY_1152_DATA, DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA, DENALI_PHY_1155_DATA, DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA, DENALI_PHY_1158_DATA, DENALI_PHY_1159_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@136 PS1, Line 136: DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA, DENALI_PHY_1162_DATA, DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA, DENALI_PHY_1165_DATA, DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA, DENALI_PHY_1168_DATA, DENALI_PHY_1169_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@137 PS1, Line 137: DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA, DENALI_PHY_1172_DATA, DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA, DENALI_PHY_1175_DATA, DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA, DENALI_PHY_1178_DATA, DENALI_PHY_1179_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@138 PS1, Line 138: DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA, DENALI_PHY_1182_DATA, DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA, DENALI_PHY_1185_DATA, DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA, DENALI_PHY_1188_DATA, DENALI_PHY_1189_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@139 PS1, Line 139: DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA, DENALI_PHY_1192_DATA, DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA, DENALI_PHY_1195_DATA, DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA, DENALI_PHY_1198_DATA, DENALI_PHY_1199_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@141 PS1, Line 141: DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA, DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA, DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA, DENALI_PHY_1209_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@142 PS1, Line 142: DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA, DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA}; line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@146 PS1, Line 146: DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA, DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA, DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA, DENALI_CTL_09_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@147 PS1, Line 147: DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA, DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA, DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA, DENALI_CTL_19_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@148 PS1, Line 148: DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA, DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA, DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA, DENALI_CTL_29_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@149 PS1, Line 149: DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA, DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA, DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA, DENALI_CTL_39_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@150 PS1, Line 150: DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA, DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA, DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA, DENALI_CTL_49_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@151 PS1, Line 151: DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA, DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA, DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA, DENALI_CTL_59_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@152 PS1, Line 152: DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA, DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA, DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA, DENALI_CTL_69_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@153 PS1, Line 153: DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA, DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA, DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA, DENALI_CTL_79_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@154 PS1, Line 154: DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA, DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA, DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA, DENALI_CTL_89_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@155 PS1, Line 155: DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA, DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA, DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA, DENALI_CTL_99_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@157 PS1, Line 157: DENALI_CTL_100_DATA, DENALI_CTL_101_DATA, DENALI_CTL_102_DATA, DENALI_CTL_103_DATA, DENALI_CTL_104_DATA, DENALI_CTL_105_DATA, DENALI_CTL_106_DATA, DENALI_CTL_107_DATA, DENALI_CTL_108_DATA, DENALI_CTL_109_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@158 PS1, Line 158: DENALI_CTL_110_DATA, DENALI_CTL_111_DATA, DENALI_CTL_112_DATA, DENALI_CTL_113_DATA, DENALI_CTL_114_DATA, DENALI_CTL_115_DATA, DENALI_CTL_116_DATA, DENALI_CTL_117_DATA, DENALI_CTL_118_DATA, DENALI_CTL_119_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@159 PS1, Line 159: DENALI_CTL_120_DATA, DENALI_CTL_121_DATA, DENALI_CTL_122_DATA, DENALI_CTL_123_DATA, DENALI_CTL_124_DATA, DENALI_CTL_125_DATA, DENALI_CTL_126_DATA, DENALI_CTL_127_DATA, DENALI_CTL_128_DATA, DENALI_CTL_129_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@160 PS1, Line 160: DENALI_CTL_130_DATA, DENALI_CTL_131_DATA, DENALI_CTL_132_DATA, DENALI_CTL_133_DATA, DENALI_CTL_134_DATA, DENALI_CTL_135_DATA, DENALI_CTL_136_DATA, DENALI_CTL_137_DATA, DENALI_CTL_138_DATA, DENALI_CTL_139_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@161 PS1, Line 161: DENALI_CTL_140_DATA, DENALI_CTL_141_DATA, DENALI_CTL_142_DATA, DENALI_CTL_143_DATA, DENALI_CTL_144_DATA, DENALI_CTL_145_DATA, DENALI_CTL_146_DATA, DENALI_CTL_147_DATA, DENALI_CTL_148_DATA, DENALI_CTL_149_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@162 PS1, Line 162: DENALI_CTL_150_DATA, DENALI_CTL_151_DATA, DENALI_CTL_152_DATA, DENALI_CTL_153_DATA, DENALI_CTL_154_DATA, DENALI_CTL_155_DATA, DENALI_CTL_156_DATA, DENALI_CTL_157_DATA, DENALI_CTL_158_DATA, DENALI_CTL_159_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@163 PS1, Line 163: DENALI_CTL_160_DATA, DENALI_CTL_161_DATA, DENALI_CTL_162_DATA, DENALI_CTL_163_DATA, DENALI_CTL_164_DATA, DENALI_CTL_165_DATA, DENALI_CTL_166_DATA, DENALI_CTL_167_DATA, DENALI_CTL_168_DATA, DENALI_CTL_169_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@164 PS1, Line 164: DENALI_CTL_170_DATA, DENALI_CTL_171_DATA, DENALI_CTL_172_DATA, DENALI_CTL_173_DATA, DENALI_CTL_174_DATA, DENALI_CTL_175_DATA, DENALI_CTL_176_DATA, DENALI_CTL_177_DATA, DENALI_CTL_178_DATA, DENALI_CTL_179_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@165 PS1, Line 165: DENALI_CTL_180_DATA, DENALI_CTL_181_DATA, DENALI_CTL_182_DATA, DENALI_CTL_183_DATA, DENALI_CTL_184_DATA, DENALI_CTL_185_DATA, DENALI_CTL_186_DATA, DENALI_CTL_187_DATA, DENALI_CTL_188_DATA, DENALI_CTL_189_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@166 PS1, Line 166: DENALI_CTL_190_DATA, DENALI_CTL_191_DATA, DENALI_CTL_192_DATA, DENALI_CTL_193_DATA, DENALI_CTL_194_DATA, DENALI_CTL_195_DATA, DENALI_CTL_196_DATA, DENALI_CTL_197_DATA, DENALI_CTL_198_DATA, DENALI_CTL_199_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@168 PS1, Line 168: DENALI_CTL_200_DATA, DENALI_CTL_201_DATA, DENALI_CTL_202_DATA, DENALI_CTL_203_DATA, DENALI_CTL_204_DATA, DENALI_CTL_205_DATA, DENALI_CTL_206_DATA, DENALI_CTL_207_DATA, DENALI_CTL_208_DATA, DENALI_CTL_209_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@169 PS1, Line 169: DENALI_CTL_210_DATA, DENALI_CTL_211_DATA, DENALI_CTL_212_DATA, DENALI_CTL_213_DATA, DENALI_CTL_214_DATA, DENALI_CTL_215_DATA, DENALI_CTL_216_DATA, DENALI_CTL_217_DATA, DENALI_CTL_218_DATA, DENALI_CTL_219_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@170 PS1, Line 170: DENALI_CTL_220_DATA, DENALI_CTL_221_DATA, DENALI_CTL_222_DATA, DENALI_CTL_223_DATA, DENALI_CTL_224_DATA, DENALI_CTL_225_DATA, DENALI_CTL_226_DATA, DENALI_CTL_227_DATA, DENALI_CTL_228_DATA, DENALI_CTL_229_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@171 PS1, Line 171: DENALI_CTL_230_DATA, DENALI_CTL_231_DATA, DENALI_CTL_232_DATA, DENALI_CTL_233_DATA, DENALI_CTL_234_DATA, DENALI_CTL_235_DATA, DENALI_CTL_236_DATA, DENALI_CTL_237_DATA, DENALI_CTL_238_DATA, DENALI_CTL_239_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@172 PS1, Line 172: DENALI_CTL_240_DATA, DENALI_CTL_241_DATA, DENALI_CTL_242_DATA, DENALI_CTL_243_DATA, DENALI_CTL_244_DATA, DENALI_CTL_245_DATA, DENALI_CTL_246_DATA, DENALI_CTL_247_DATA, DENALI_CTL_248_DATA, DENALI_CTL_249_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@173 PS1, Line 173: DENALI_CTL_250_DATA, DENALI_CTL_251_DATA, DENALI_CTL_252_DATA, DENALI_CTL_253_DATA, DENALI_CTL_254_DATA, DENALI_CTL_255_DATA, DENALI_CTL_256_DATA, DENALI_CTL_257_DATA, DENALI_CTL_258_DATA, DENALI_CTL_259_DATA, line over 80 characters https://review.coreboot.org/#/c/28594/1/src/soc/sifive/fu540/ddrregs.h@174 PS1, Line 174: DENALI_CTL_260_DATA, DENALI_CTL_261_DATA, DENALI_CTL_262_DATA, DENALI_CTL_263_DATA, DENALI_CTL_264_DATA }; line over 80 characters -- To view, visit https://review.coreboot.org/28594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716 Gerrit-Change-Number: 28594 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Sep 2018 20:32:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/sifive/fu540: add SiFive supplied header files for SDRAM intializ...
by Philipp Hug (Code Review) 13 Sep '18

13 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28594 Change subject: soc/sifive/fu540: add SiFive supplied header files for SDRAM intialization ...................................................................... soc/sifive/fu540: add SiFive supplied header files for SDRAM intialization Add original files from SiFive bootloader. Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- A src/soc/sifive/fu540/ddrregs.h A src/soc/sifive/fu540/regconfig-ctl.h A src/soc/sifive/fu540/regconfig-phy.h 3 files changed, 1,664 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/28594/1 diff --git a/src/soc/sifive/fu540/ddrregs.h b/src/soc/sifive/fu540/ddrregs.h new file mode 100644 index 0000000..5f6f35d --- /dev/null +++ b/src/soc/sifive/fu540/ddrregs.h @@ -0,0 +1,174 @@ +/* Copyright (c) 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* See the file LICENSE for further information */ + +#include <stdint.h> + +uint32_t DENALI_PHY_DATA [1215] = { +DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, DENALI_PHY_02_DATA, DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, DENALI_PHY_05_DATA, DENALI_PHY_06_DATA, DENALI_PHY_07_DATA, DENALI_PHY_08_DATA, DENALI_PHY_09_DATA, +DENALI_PHY_10_DATA, DENALI_PHY_11_DATA, DENALI_PHY_12_DATA, DENALI_PHY_13_DATA, DENALI_PHY_14_DATA, DENALI_PHY_15_DATA, DENALI_PHY_16_DATA, DENALI_PHY_17_DATA, DENALI_PHY_18_DATA, DENALI_PHY_19_DATA, +DENALI_PHY_20_DATA, DENALI_PHY_21_DATA, DENALI_PHY_22_DATA, DENALI_PHY_23_DATA, DENALI_PHY_24_DATA, DENALI_PHY_25_DATA, DENALI_PHY_26_DATA, DENALI_PHY_27_DATA, DENALI_PHY_28_DATA, DENALI_PHY_29_DATA, +DENALI_PHY_30_DATA, DENALI_PHY_31_DATA, DENALI_PHY_32_DATA, DENALI_PHY_33_DATA, DENALI_PHY_34_DATA, DENALI_PHY_35_DATA, DENALI_PHY_36_DATA, DENALI_PHY_37_DATA, DENALI_PHY_38_DATA, DENALI_PHY_39_DATA, +DENALI_PHY_40_DATA, DENALI_PHY_41_DATA, DENALI_PHY_42_DATA, DENALI_PHY_43_DATA, DENALI_PHY_44_DATA, DENALI_PHY_45_DATA, DENALI_PHY_46_DATA, DENALI_PHY_47_DATA, DENALI_PHY_48_DATA, DENALI_PHY_49_DATA, +DENALI_PHY_50_DATA, DENALI_PHY_51_DATA, DENALI_PHY_52_DATA, DENALI_PHY_53_DATA, DENALI_PHY_54_DATA, DENALI_PHY_55_DATA, DENALI_PHY_56_DATA, DENALI_PHY_57_DATA, DENALI_PHY_58_DATA, DENALI_PHY_59_DATA, +DENALI_PHY_60_DATA, DENALI_PHY_61_DATA, DENALI_PHY_62_DATA, DENALI_PHY_63_DATA, DENALI_PHY_64_DATA, DENALI_PHY_65_DATA, DENALI_PHY_66_DATA, DENALI_PHY_67_DATA, DENALI_PHY_68_DATA, DENALI_PHY_69_DATA, +DENALI_PHY_70_DATA, DENALI_PHY_71_DATA, DENALI_PHY_72_DATA, DENALI_PHY_73_DATA, DENALI_PHY_74_DATA, DENALI_PHY_75_DATA, DENALI_PHY_76_DATA, DENALI_PHY_77_DATA, DENALI_PHY_78_DATA, DENALI_PHY_79_DATA, +DENALI_PHY_80_DATA, DENALI_PHY_81_DATA, DENALI_PHY_82_DATA, DENALI_PHY_83_DATA, DENALI_PHY_84_DATA, DENALI_PHY_85_DATA, DENALI_PHY_86_DATA, DENALI_PHY_87_DATA, DENALI_PHY_88_DATA, DENALI_PHY_89_DATA, +DENALI_PHY_90_DATA, DENALI_PHY_91_DATA, DENALI_PHY_92_DATA, DENALI_PHY_93_DATA, DENALI_PHY_94_DATA, DENALI_PHY_95_DATA, DENALI_PHY_96_DATA, DENALI_PHY_97_DATA, DENALI_PHY_98_DATA, DENALI_PHY_99_DATA, + +DENALI_PHY_100_DATA, DENALI_PHY_101_DATA, DENALI_PHY_102_DATA, DENALI_PHY_103_DATA, DENALI_PHY_104_DATA, DENALI_PHY_105_DATA, DENALI_PHY_106_DATA, DENALI_PHY_107_DATA, DENALI_PHY_108_DATA, DENALI_PHY_109_DATA, +DENALI_PHY_110_DATA, DENALI_PHY_111_DATA, DENALI_PHY_112_DATA, DENALI_PHY_113_DATA, DENALI_PHY_114_DATA, DENALI_PHY_115_DATA, DENALI_PHY_116_DATA, DENALI_PHY_117_DATA, DENALI_PHY_118_DATA, DENALI_PHY_119_DATA, +DENALI_PHY_120_DATA, DENALI_PHY_121_DATA, DENALI_PHY_122_DATA, DENALI_PHY_123_DATA, DENALI_PHY_124_DATA, DENALI_PHY_125_DATA, DENALI_PHY_126_DATA, DENALI_PHY_127_DATA, DENALI_PHY_128_DATA, DENALI_PHY_129_DATA, +DENALI_PHY_130_DATA, DENALI_PHY_131_DATA, DENALI_PHY_132_DATA, DENALI_PHY_133_DATA, DENALI_PHY_134_DATA, DENALI_PHY_135_DATA, DENALI_PHY_136_DATA, DENALI_PHY_137_DATA, DENALI_PHY_138_DATA, DENALI_PHY_139_DATA, +DENALI_PHY_140_DATA, DENALI_PHY_141_DATA, DENALI_PHY_142_DATA, DENALI_PHY_143_DATA, DENALI_PHY_144_DATA, DENALI_PHY_145_DATA, DENALI_PHY_146_DATA, DENALI_PHY_147_DATA, DENALI_PHY_148_DATA, DENALI_PHY_149_DATA, +DENALI_PHY_150_DATA, DENALI_PHY_151_DATA, DENALI_PHY_152_DATA, DENALI_PHY_153_DATA, DENALI_PHY_154_DATA, DENALI_PHY_155_DATA, DENALI_PHY_156_DATA, DENALI_PHY_157_DATA, DENALI_PHY_158_DATA, DENALI_PHY_159_DATA, +DENALI_PHY_160_DATA, DENALI_PHY_161_DATA, DENALI_PHY_162_DATA, DENALI_PHY_163_DATA, DENALI_PHY_164_DATA, DENALI_PHY_165_DATA, DENALI_PHY_166_DATA, DENALI_PHY_167_DATA, DENALI_PHY_168_DATA, DENALI_PHY_169_DATA, +DENALI_PHY_170_DATA, DENALI_PHY_171_DATA, DENALI_PHY_172_DATA, DENALI_PHY_173_DATA, DENALI_PHY_174_DATA, DENALI_PHY_175_DATA, DENALI_PHY_176_DATA, DENALI_PHY_177_DATA, DENALI_PHY_178_DATA, DENALI_PHY_179_DATA, +DENALI_PHY_180_DATA, DENALI_PHY_181_DATA, DENALI_PHY_182_DATA, DENALI_PHY_183_DATA, DENALI_PHY_184_DATA, DENALI_PHY_185_DATA, DENALI_PHY_186_DATA, DENALI_PHY_187_DATA, DENALI_PHY_188_DATA, DENALI_PHY_189_DATA, +DENALI_PHY_190_DATA, DENALI_PHY_191_DATA, DENALI_PHY_192_DATA, DENALI_PHY_193_DATA, DENALI_PHY_194_DATA, DENALI_PHY_195_DATA, DENALI_PHY_196_DATA, DENALI_PHY_197_DATA, DENALI_PHY_198_DATA, DENALI_PHY_199_DATA, + +DENALI_PHY_200_DATA, DENALI_PHY_201_DATA, DENALI_PHY_202_DATA, DENALI_PHY_203_DATA, DENALI_PHY_204_DATA, DENALI_PHY_205_DATA, DENALI_PHY_206_DATA, DENALI_PHY_207_DATA, DENALI_PHY_208_DATA, DENALI_PHY_209_DATA, +DENALI_PHY_210_DATA, DENALI_PHY_211_DATA, DENALI_PHY_212_DATA, DENALI_PHY_213_DATA, DENALI_PHY_214_DATA, DENALI_PHY_215_DATA, DENALI_PHY_216_DATA, DENALI_PHY_217_DATA, DENALI_PHY_218_DATA, DENALI_PHY_219_DATA, +DENALI_PHY_220_DATA, DENALI_PHY_221_DATA, DENALI_PHY_222_DATA, DENALI_PHY_223_DATA, DENALI_PHY_224_DATA, DENALI_PHY_225_DATA, DENALI_PHY_226_DATA, DENALI_PHY_227_DATA, DENALI_PHY_228_DATA, DENALI_PHY_229_DATA, +DENALI_PHY_230_DATA, DENALI_PHY_231_DATA, DENALI_PHY_232_DATA, DENALI_PHY_233_DATA, DENALI_PHY_234_DATA, DENALI_PHY_235_DATA, DENALI_PHY_236_DATA, DENALI_PHY_237_DATA, DENALI_PHY_238_DATA, DENALI_PHY_239_DATA, +DENALI_PHY_240_DATA, DENALI_PHY_241_DATA, DENALI_PHY_242_DATA, DENALI_PHY_243_DATA, DENALI_PHY_244_DATA, DENALI_PHY_245_DATA, DENALI_PHY_246_DATA, DENALI_PHY_247_DATA, DENALI_PHY_248_DATA, DENALI_PHY_249_DATA, +DENALI_PHY_250_DATA, DENALI_PHY_251_DATA, DENALI_PHY_252_DATA, DENALI_PHY_253_DATA, DENALI_PHY_254_DATA, DENALI_PHY_255_DATA, DENALI_PHY_256_DATA, DENALI_PHY_257_DATA, DENALI_PHY_258_DATA, DENALI_PHY_259_DATA, +DENALI_PHY_260_DATA, DENALI_PHY_261_DATA, DENALI_PHY_262_DATA, DENALI_PHY_263_DATA, DENALI_PHY_264_DATA, DENALI_PHY_265_DATA, DENALI_PHY_266_DATA, DENALI_PHY_267_DATA, DENALI_PHY_268_DATA, DENALI_PHY_269_DATA, +DENALI_PHY_270_DATA, DENALI_PHY_271_DATA, DENALI_PHY_272_DATA, DENALI_PHY_273_DATA, DENALI_PHY_274_DATA, DENALI_PHY_275_DATA, DENALI_PHY_276_DATA, DENALI_PHY_277_DATA, DENALI_PHY_278_DATA, DENALI_PHY_279_DATA, +DENALI_PHY_280_DATA, DENALI_PHY_281_DATA, DENALI_PHY_282_DATA, DENALI_PHY_283_DATA, DENALI_PHY_284_DATA, DENALI_PHY_285_DATA, DENALI_PHY_286_DATA, DENALI_PHY_287_DATA, DENALI_PHY_288_DATA, DENALI_PHY_289_DATA, +DENALI_PHY_290_DATA, DENALI_PHY_291_DATA, DENALI_PHY_292_DATA, DENALI_PHY_293_DATA, DENALI_PHY_294_DATA, DENALI_PHY_295_DATA, DENALI_PHY_296_DATA, DENALI_PHY_297_DATA, DENALI_PHY_298_DATA, DENALI_PHY_299_DATA, + +DENALI_PHY_300_DATA, DENALI_PHY_301_DATA, DENALI_PHY_302_DATA, DENALI_PHY_303_DATA, DENALI_PHY_304_DATA, DENALI_PHY_305_DATA, DENALI_PHY_306_DATA, DENALI_PHY_307_DATA, DENALI_PHY_308_DATA, DENALI_PHY_309_DATA, +DENALI_PHY_310_DATA, DENALI_PHY_311_DATA, DENALI_PHY_312_DATA, DENALI_PHY_313_DATA, DENALI_PHY_314_DATA, DENALI_PHY_315_DATA, DENALI_PHY_316_DATA, DENALI_PHY_317_DATA, DENALI_PHY_318_DATA, DENALI_PHY_319_DATA, +DENALI_PHY_320_DATA, DENALI_PHY_321_DATA, DENALI_PHY_322_DATA, DENALI_PHY_323_DATA, DENALI_PHY_324_DATA, DENALI_PHY_325_DATA, DENALI_PHY_326_DATA, DENALI_PHY_327_DATA, DENALI_PHY_328_DATA, DENALI_PHY_329_DATA, +DENALI_PHY_330_DATA, DENALI_PHY_331_DATA, DENALI_PHY_332_DATA, DENALI_PHY_333_DATA, DENALI_PHY_334_DATA, DENALI_PHY_335_DATA, DENALI_PHY_336_DATA, DENALI_PHY_337_DATA, DENALI_PHY_338_DATA, DENALI_PHY_339_DATA, +DENALI_PHY_340_DATA, DENALI_PHY_341_DATA, DENALI_PHY_342_DATA, DENALI_PHY_343_DATA, DENALI_PHY_344_DATA, DENALI_PHY_345_DATA, DENALI_PHY_346_DATA, DENALI_PHY_347_DATA, DENALI_PHY_348_DATA, DENALI_PHY_349_DATA, +DENALI_PHY_350_DATA, DENALI_PHY_351_DATA, DENALI_PHY_352_DATA, DENALI_PHY_353_DATA, DENALI_PHY_354_DATA, DENALI_PHY_355_DATA, DENALI_PHY_356_DATA, DENALI_PHY_357_DATA, DENALI_PHY_358_DATA, DENALI_PHY_359_DATA, +DENALI_PHY_360_DATA, DENALI_PHY_361_DATA, DENALI_PHY_362_DATA, DENALI_PHY_363_DATA, DENALI_PHY_364_DATA, DENALI_PHY_365_DATA, DENALI_PHY_366_DATA, DENALI_PHY_367_DATA, DENALI_PHY_368_DATA, DENALI_PHY_369_DATA, +DENALI_PHY_370_DATA, DENALI_PHY_371_DATA, DENALI_PHY_372_DATA, DENALI_PHY_373_DATA, DENALI_PHY_374_DATA, DENALI_PHY_375_DATA, DENALI_PHY_376_DATA, DENALI_PHY_377_DATA, DENALI_PHY_378_DATA, DENALI_PHY_379_DATA, +DENALI_PHY_380_DATA, DENALI_PHY_381_DATA, DENALI_PHY_382_DATA, DENALI_PHY_383_DATA, DENALI_PHY_384_DATA, DENALI_PHY_385_DATA, DENALI_PHY_386_DATA, DENALI_PHY_387_DATA, DENALI_PHY_388_DATA, DENALI_PHY_389_DATA, +DENALI_PHY_390_DATA, DENALI_PHY_391_DATA, DENALI_PHY_392_DATA, DENALI_PHY_393_DATA, DENALI_PHY_394_DATA, DENALI_PHY_395_DATA, DENALI_PHY_396_DATA, DENALI_PHY_397_DATA, DENALI_PHY_398_DATA, DENALI_PHY_399_DATA, + +DENALI_PHY_400_DATA, DENALI_PHY_401_DATA, DENALI_PHY_402_DATA, DENALI_PHY_403_DATA, DENALI_PHY_404_DATA, DENALI_PHY_405_DATA, DENALI_PHY_406_DATA, DENALI_PHY_407_DATA, DENALI_PHY_408_DATA, DENALI_PHY_409_DATA, +DENALI_PHY_410_DATA, DENALI_PHY_411_DATA, DENALI_PHY_412_DATA, DENALI_PHY_413_DATA, DENALI_PHY_414_DATA, DENALI_PHY_415_DATA, DENALI_PHY_416_DATA, DENALI_PHY_417_DATA, DENALI_PHY_418_DATA, DENALI_PHY_419_DATA, +DENALI_PHY_420_DATA, DENALI_PHY_421_DATA, DENALI_PHY_422_DATA, DENALI_PHY_423_DATA, DENALI_PHY_424_DATA, DENALI_PHY_425_DATA, DENALI_PHY_426_DATA, DENALI_PHY_427_DATA, DENALI_PHY_428_DATA, DENALI_PHY_429_DATA, +DENALI_PHY_430_DATA, DENALI_PHY_431_DATA, DENALI_PHY_432_DATA, DENALI_PHY_433_DATA, DENALI_PHY_434_DATA, DENALI_PHY_435_DATA, DENALI_PHY_436_DATA, DENALI_PHY_437_DATA, DENALI_PHY_438_DATA, DENALI_PHY_439_DATA, +DENALI_PHY_440_DATA, DENALI_PHY_441_DATA, DENALI_PHY_442_DATA, DENALI_PHY_443_DATA, DENALI_PHY_444_DATA, DENALI_PHY_445_DATA, DENALI_PHY_446_DATA, DENALI_PHY_447_DATA, DENALI_PHY_448_DATA, DENALI_PHY_449_DATA, +DENALI_PHY_450_DATA, DENALI_PHY_451_DATA, DENALI_PHY_452_DATA, DENALI_PHY_453_DATA, DENALI_PHY_454_DATA, DENALI_PHY_455_DATA, DENALI_PHY_456_DATA, DENALI_PHY_457_DATA, DENALI_PHY_458_DATA, DENALI_PHY_459_DATA, +DENALI_PHY_460_DATA, DENALI_PHY_461_DATA, DENALI_PHY_462_DATA, DENALI_PHY_463_DATA, DENALI_PHY_464_DATA, DENALI_PHY_465_DATA, DENALI_PHY_466_DATA, DENALI_PHY_467_DATA, DENALI_PHY_468_DATA, DENALI_PHY_469_DATA, +DENALI_PHY_470_DATA, DENALI_PHY_471_DATA, DENALI_PHY_472_DATA, DENALI_PHY_473_DATA, DENALI_PHY_474_DATA, DENALI_PHY_475_DATA, DENALI_PHY_476_DATA, DENALI_PHY_477_DATA, DENALI_PHY_478_DATA, DENALI_PHY_479_DATA, +DENALI_PHY_480_DATA, DENALI_PHY_481_DATA, DENALI_PHY_482_DATA, DENALI_PHY_483_DATA, DENALI_PHY_484_DATA, DENALI_PHY_485_DATA, DENALI_PHY_486_DATA, DENALI_PHY_487_DATA, DENALI_PHY_488_DATA, DENALI_PHY_489_DATA, +DENALI_PHY_490_DATA, DENALI_PHY_491_DATA, DENALI_PHY_492_DATA, DENALI_PHY_493_DATA, DENALI_PHY_494_DATA, DENALI_PHY_495_DATA, DENALI_PHY_496_DATA, DENALI_PHY_497_DATA, DENALI_PHY_498_DATA, DENALI_PHY_499_DATA, + +DENALI_PHY_500_DATA, DENALI_PHY_501_DATA, DENALI_PHY_502_DATA, DENALI_PHY_503_DATA, DENALI_PHY_504_DATA, DENALI_PHY_505_DATA, DENALI_PHY_506_DATA, DENALI_PHY_507_DATA, DENALI_PHY_508_DATA, DENALI_PHY_509_DATA, +DENALI_PHY_510_DATA, DENALI_PHY_511_DATA, DENALI_PHY_512_DATA, DENALI_PHY_513_DATA, DENALI_PHY_514_DATA, DENALI_PHY_515_DATA, DENALI_PHY_516_DATA, DENALI_PHY_517_DATA, DENALI_PHY_518_DATA, DENALI_PHY_519_DATA, +DENALI_PHY_520_DATA, DENALI_PHY_521_DATA, DENALI_PHY_522_DATA, DENALI_PHY_523_DATA, DENALI_PHY_524_DATA, DENALI_PHY_525_DATA, DENALI_PHY_526_DATA, DENALI_PHY_527_DATA, DENALI_PHY_528_DATA, DENALI_PHY_529_DATA, +DENALI_PHY_530_DATA, DENALI_PHY_531_DATA, DENALI_PHY_532_DATA, DENALI_PHY_533_DATA, DENALI_PHY_534_DATA, DENALI_PHY_535_DATA, DENALI_PHY_536_DATA, DENALI_PHY_537_DATA, DENALI_PHY_538_DATA, DENALI_PHY_539_DATA, +DENALI_PHY_540_DATA, DENALI_PHY_541_DATA, DENALI_PHY_542_DATA, DENALI_PHY_543_DATA, DENALI_PHY_544_DATA, DENALI_PHY_545_DATA, DENALI_PHY_546_DATA, DENALI_PHY_547_DATA, DENALI_PHY_548_DATA, DENALI_PHY_549_DATA, +DENALI_PHY_550_DATA, DENALI_PHY_551_DATA, DENALI_PHY_552_DATA, DENALI_PHY_553_DATA, DENALI_PHY_554_DATA, DENALI_PHY_555_DATA, DENALI_PHY_556_DATA, DENALI_PHY_557_DATA, DENALI_PHY_558_DATA, DENALI_PHY_559_DATA, +DENALI_PHY_560_DATA, DENALI_PHY_561_DATA, DENALI_PHY_562_DATA, DENALI_PHY_563_DATA, DENALI_PHY_564_DATA, DENALI_PHY_565_DATA, DENALI_PHY_566_DATA, DENALI_PHY_567_DATA, DENALI_PHY_568_DATA, DENALI_PHY_569_DATA, +DENALI_PHY_570_DATA, DENALI_PHY_571_DATA, DENALI_PHY_572_DATA, DENALI_PHY_573_DATA, DENALI_PHY_574_DATA, DENALI_PHY_575_DATA, DENALI_PHY_576_DATA, DENALI_PHY_577_DATA, DENALI_PHY_578_DATA, DENALI_PHY_579_DATA, +DENALI_PHY_580_DATA, DENALI_PHY_581_DATA, DENALI_PHY_582_DATA, DENALI_PHY_583_DATA, DENALI_PHY_584_DATA, DENALI_PHY_585_DATA, DENALI_PHY_586_DATA, DENALI_PHY_587_DATA, DENALI_PHY_588_DATA, DENALI_PHY_589_DATA, +DENALI_PHY_590_DATA, DENALI_PHY_591_DATA, DENALI_PHY_592_DATA, DENALI_PHY_593_DATA, DENALI_PHY_594_DATA, DENALI_PHY_595_DATA, DENALI_PHY_596_DATA, DENALI_PHY_597_DATA, DENALI_PHY_598_DATA, DENALI_PHY_599_DATA, + +DENALI_PHY_600_DATA, DENALI_PHY_601_DATA, DENALI_PHY_602_DATA, DENALI_PHY_603_DATA, DENALI_PHY_604_DATA, DENALI_PHY_605_DATA, DENALI_PHY_606_DATA, DENALI_PHY_607_DATA, DENALI_PHY_608_DATA, DENALI_PHY_609_DATA, +DENALI_PHY_610_DATA, DENALI_PHY_611_DATA, DENALI_PHY_612_DATA, DENALI_PHY_613_DATA, DENALI_PHY_614_DATA, DENALI_PHY_615_DATA, DENALI_PHY_616_DATA, DENALI_PHY_617_DATA, DENALI_PHY_618_DATA, DENALI_PHY_619_DATA, +DENALI_PHY_620_DATA, DENALI_PHY_621_DATA, DENALI_PHY_622_DATA, DENALI_PHY_623_DATA, DENALI_PHY_624_DATA, DENALI_PHY_625_DATA, DENALI_PHY_626_DATA, DENALI_PHY_627_DATA, DENALI_PHY_628_DATA, DENALI_PHY_629_DATA, +DENALI_PHY_630_DATA, DENALI_PHY_631_DATA, DENALI_PHY_632_DATA, DENALI_PHY_633_DATA, DENALI_PHY_634_DATA, DENALI_PHY_635_DATA, DENALI_PHY_636_DATA, DENALI_PHY_637_DATA, DENALI_PHY_638_DATA, DENALI_PHY_639_DATA, +DENALI_PHY_640_DATA, DENALI_PHY_641_DATA, DENALI_PHY_642_DATA, DENALI_PHY_643_DATA, DENALI_PHY_644_DATA, DENALI_PHY_645_DATA, DENALI_PHY_646_DATA, DENALI_PHY_647_DATA, DENALI_PHY_648_DATA, DENALI_PHY_649_DATA, +DENALI_PHY_650_DATA, DENALI_PHY_651_DATA, DENALI_PHY_652_DATA, DENALI_PHY_653_DATA, DENALI_PHY_654_DATA, DENALI_PHY_655_DATA, DENALI_PHY_656_DATA, DENALI_PHY_657_DATA, DENALI_PHY_658_DATA, DENALI_PHY_659_DATA, +DENALI_PHY_660_DATA, DENALI_PHY_661_DATA, DENALI_PHY_662_DATA, DENALI_PHY_663_DATA, DENALI_PHY_664_DATA, DENALI_PHY_665_DATA, DENALI_PHY_666_DATA, DENALI_PHY_667_DATA, DENALI_PHY_668_DATA, DENALI_PHY_669_DATA, +DENALI_PHY_670_DATA, DENALI_PHY_671_DATA, DENALI_PHY_672_DATA, DENALI_PHY_673_DATA, DENALI_PHY_674_DATA, DENALI_PHY_675_DATA, DENALI_PHY_676_DATA, DENALI_PHY_677_DATA, DENALI_PHY_678_DATA, DENALI_PHY_679_DATA, +DENALI_PHY_680_DATA, DENALI_PHY_681_DATA, DENALI_PHY_682_DATA, DENALI_PHY_683_DATA, DENALI_PHY_684_DATA, DENALI_PHY_685_DATA, DENALI_PHY_686_DATA, DENALI_PHY_687_DATA, DENALI_PHY_688_DATA, DENALI_PHY_689_DATA, +DENALI_PHY_690_DATA, DENALI_PHY_691_DATA, DENALI_PHY_692_DATA, DENALI_PHY_693_DATA, DENALI_PHY_694_DATA, DENALI_PHY_695_DATA, DENALI_PHY_696_DATA, DENALI_PHY_697_DATA, DENALI_PHY_698_DATA, DENALI_PHY_699_DATA, + +DENALI_PHY_700_DATA, DENALI_PHY_701_DATA, DENALI_PHY_702_DATA, DENALI_PHY_703_DATA, DENALI_PHY_704_DATA, DENALI_PHY_705_DATA, DENALI_PHY_706_DATA, DENALI_PHY_707_DATA, DENALI_PHY_708_DATA, DENALI_PHY_709_DATA, +DENALI_PHY_710_DATA, DENALI_PHY_711_DATA, DENALI_PHY_712_DATA, DENALI_PHY_713_DATA, DENALI_PHY_714_DATA, DENALI_PHY_715_DATA, DENALI_PHY_716_DATA, DENALI_PHY_717_DATA, DENALI_PHY_718_DATA, DENALI_PHY_719_DATA, +DENALI_PHY_720_DATA, DENALI_PHY_721_DATA, DENALI_PHY_722_DATA, DENALI_PHY_723_DATA, DENALI_PHY_724_DATA, DENALI_PHY_725_DATA, DENALI_PHY_726_DATA, DENALI_PHY_727_DATA, DENALI_PHY_728_DATA, DENALI_PHY_729_DATA, +DENALI_PHY_730_DATA, DENALI_PHY_731_DATA, DENALI_PHY_732_DATA, DENALI_PHY_733_DATA, DENALI_PHY_734_DATA, DENALI_PHY_735_DATA, DENALI_PHY_736_DATA, DENALI_PHY_737_DATA, DENALI_PHY_738_DATA, DENALI_PHY_739_DATA, +DENALI_PHY_740_DATA, DENALI_PHY_741_DATA, DENALI_PHY_742_DATA, DENALI_PHY_743_DATA, DENALI_PHY_744_DATA, DENALI_PHY_745_DATA, DENALI_PHY_746_DATA, DENALI_PHY_747_DATA, DENALI_PHY_748_DATA, DENALI_PHY_749_DATA, +DENALI_PHY_750_DATA, DENALI_PHY_751_DATA, DENALI_PHY_752_DATA, DENALI_PHY_753_DATA, DENALI_PHY_754_DATA, DENALI_PHY_755_DATA, DENALI_PHY_756_DATA, DENALI_PHY_757_DATA, DENALI_PHY_758_DATA, DENALI_PHY_759_DATA, +DENALI_PHY_760_DATA, DENALI_PHY_761_DATA, DENALI_PHY_762_DATA, DENALI_PHY_763_DATA, DENALI_PHY_764_DATA, DENALI_PHY_765_DATA, DENALI_PHY_766_DATA, DENALI_PHY_767_DATA, DENALI_PHY_768_DATA, DENALI_PHY_769_DATA, +DENALI_PHY_770_DATA, DENALI_PHY_771_DATA, DENALI_PHY_772_DATA, DENALI_PHY_773_DATA, DENALI_PHY_774_DATA, DENALI_PHY_775_DATA, DENALI_PHY_776_DATA, DENALI_PHY_777_DATA, DENALI_PHY_778_DATA, DENALI_PHY_779_DATA, +DENALI_PHY_780_DATA, DENALI_PHY_781_DATA, DENALI_PHY_782_DATA, DENALI_PHY_783_DATA, DENALI_PHY_784_DATA, DENALI_PHY_785_DATA, DENALI_PHY_786_DATA, DENALI_PHY_787_DATA, DENALI_PHY_788_DATA, DENALI_PHY_789_DATA, +DENALI_PHY_790_DATA, DENALI_PHY_791_DATA, DENALI_PHY_792_DATA, DENALI_PHY_793_DATA, DENALI_PHY_794_DATA, DENALI_PHY_795_DATA, DENALI_PHY_796_DATA, DENALI_PHY_797_DATA, DENALI_PHY_798_DATA, DENALI_PHY_799_DATA, + +DENALI_PHY_800_DATA, DENALI_PHY_801_DATA, DENALI_PHY_802_DATA, DENALI_PHY_803_DATA, DENALI_PHY_804_DATA, DENALI_PHY_805_DATA, DENALI_PHY_806_DATA, DENALI_PHY_807_DATA, DENALI_PHY_808_DATA, DENALI_PHY_809_DATA, +DENALI_PHY_810_DATA, DENALI_PHY_811_DATA, DENALI_PHY_812_DATA, DENALI_PHY_813_DATA, DENALI_PHY_814_DATA, DENALI_PHY_815_DATA, DENALI_PHY_816_DATA, DENALI_PHY_817_DATA, DENALI_PHY_818_DATA, DENALI_PHY_819_DATA, +DENALI_PHY_820_DATA, DENALI_PHY_821_DATA, DENALI_PHY_822_DATA, DENALI_PHY_823_DATA, DENALI_PHY_824_DATA, DENALI_PHY_825_DATA, DENALI_PHY_826_DATA, DENALI_PHY_827_DATA, DENALI_PHY_828_DATA, DENALI_PHY_829_DATA, +DENALI_PHY_830_DATA, DENALI_PHY_831_DATA, DENALI_PHY_832_DATA, DENALI_PHY_833_DATA, DENALI_PHY_834_DATA, DENALI_PHY_835_DATA, DENALI_PHY_836_DATA, DENALI_PHY_837_DATA, DENALI_PHY_838_DATA, DENALI_PHY_839_DATA, +DENALI_PHY_840_DATA, DENALI_PHY_841_DATA, DENALI_PHY_842_DATA, DENALI_PHY_843_DATA, DENALI_PHY_844_DATA, DENALI_PHY_845_DATA, DENALI_PHY_846_DATA, DENALI_PHY_847_DATA, DENALI_PHY_848_DATA, DENALI_PHY_849_DATA, +DENALI_PHY_850_DATA, DENALI_PHY_851_DATA, DENALI_PHY_852_DATA, DENALI_PHY_853_DATA, DENALI_PHY_854_DATA, DENALI_PHY_855_DATA, DENALI_PHY_856_DATA, DENALI_PHY_857_DATA, DENALI_PHY_858_DATA, DENALI_PHY_859_DATA, +DENALI_PHY_860_DATA, DENALI_PHY_861_DATA, DENALI_PHY_862_DATA, DENALI_PHY_863_DATA, DENALI_PHY_864_DATA, DENALI_PHY_865_DATA, DENALI_PHY_866_DATA, DENALI_PHY_867_DATA, DENALI_PHY_868_DATA, DENALI_PHY_869_DATA, +DENALI_PHY_870_DATA, DENALI_PHY_871_DATA, DENALI_PHY_872_DATA, DENALI_PHY_873_DATA, DENALI_PHY_874_DATA, DENALI_PHY_875_DATA, DENALI_PHY_876_DATA, DENALI_PHY_877_DATA, DENALI_PHY_878_DATA, DENALI_PHY_879_DATA, +DENALI_PHY_880_DATA, DENALI_PHY_881_DATA, DENALI_PHY_882_DATA, DENALI_PHY_883_DATA, DENALI_PHY_884_DATA, DENALI_PHY_885_DATA, DENALI_PHY_886_DATA, DENALI_PHY_887_DATA, DENALI_PHY_888_DATA, DENALI_PHY_889_DATA, +DENALI_PHY_890_DATA, DENALI_PHY_891_DATA, DENALI_PHY_892_DATA, DENALI_PHY_893_DATA, DENALI_PHY_894_DATA, DENALI_PHY_895_DATA, DENALI_PHY_896_DATA, DENALI_PHY_897_DATA, DENALI_PHY_898_DATA, DENALI_PHY_899_DATA, + +DENALI_PHY_900_DATA, DENALI_PHY_901_DATA, DENALI_PHY_902_DATA, DENALI_PHY_903_DATA, DENALI_PHY_904_DATA, DENALI_PHY_905_DATA, DENALI_PHY_906_DATA, DENALI_PHY_907_DATA, DENALI_PHY_908_DATA, DENALI_PHY_909_DATA, +DENALI_PHY_910_DATA, DENALI_PHY_911_DATA, DENALI_PHY_912_DATA, DENALI_PHY_913_DATA, DENALI_PHY_914_DATA, DENALI_PHY_915_DATA, DENALI_PHY_916_DATA, DENALI_PHY_917_DATA, DENALI_PHY_918_DATA, DENALI_PHY_919_DATA, +DENALI_PHY_920_DATA, DENALI_PHY_921_DATA, DENALI_PHY_922_DATA, DENALI_PHY_923_DATA, DENALI_PHY_924_DATA, DENALI_PHY_925_DATA, DENALI_PHY_926_DATA, DENALI_PHY_927_DATA, DENALI_PHY_928_DATA, DENALI_PHY_929_DATA, +DENALI_PHY_930_DATA, DENALI_PHY_931_DATA, DENALI_PHY_932_DATA, DENALI_PHY_933_DATA, DENALI_PHY_934_DATA, DENALI_PHY_935_DATA, DENALI_PHY_936_DATA, DENALI_PHY_937_DATA, DENALI_PHY_938_DATA, DENALI_PHY_939_DATA, +DENALI_PHY_940_DATA, DENALI_PHY_941_DATA, DENALI_PHY_942_DATA, DENALI_PHY_943_DATA, DENALI_PHY_944_DATA, DENALI_PHY_945_DATA, DENALI_PHY_946_DATA, DENALI_PHY_947_DATA, DENALI_PHY_948_DATA, DENALI_PHY_949_DATA, +DENALI_PHY_950_DATA, DENALI_PHY_951_DATA, DENALI_PHY_952_DATA, DENALI_PHY_953_DATA, DENALI_PHY_954_DATA, DENALI_PHY_955_DATA, DENALI_PHY_956_DATA, DENALI_PHY_957_DATA, DENALI_PHY_958_DATA, DENALI_PHY_959_DATA, +DENALI_PHY_960_DATA, DENALI_PHY_961_DATA, DENALI_PHY_962_DATA, DENALI_PHY_963_DATA, DENALI_PHY_964_DATA, DENALI_PHY_965_DATA, DENALI_PHY_966_DATA, DENALI_PHY_967_DATA, DENALI_PHY_968_DATA, DENALI_PHY_969_DATA, +DENALI_PHY_970_DATA, DENALI_PHY_971_DATA, DENALI_PHY_972_DATA, DENALI_PHY_973_DATA, DENALI_PHY_974_DATA, DENALI_PHY_975_DATA, DENALI_PHY_976_DATA, DENALI_PHY_977_DATA, DENALI_PHY_978_DATA, DENALI_PHY_979_DATA, +DENALI_PHY_980_DATA, DENALI_PHY_981_DATA, DENALI_PHY_982_DATA, DENALI_PHY_983_DATA, DENALI_PHY_984_DATA, DENALI_PHY_985_DATA, DENALI_PHY_986_DATA, DENALI_PHY_987_DATA, DENALI_PHY_988_DATA, DENALI_PHY_989_DATA, +DENALI_PHY_990_DATA, DENALI_PHY_991_DATA, DENALI_PHY_992_DATA, DENALI_PHY_993_DATA, DENALI_PHY_994_DATA, DENALI_PHY_995_DATA, DENALI_PHY_996_DATA, DENALI_PHY_997_DATA, DENALI_PHY_998_DATA, DENALI_PHY_999_DATA, + +DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA, DENALI_PHY_1002_DATA, DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA, DENALI_PHY_1005_DATA, DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA, DENALI_PHY_1008_DATA, DENALI_PHY_1009_DATA, +DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA, DENALI_PHY_1012_DATA, DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA, DENALI_PHY_1015_DATA, DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA, DENALI_PHY_1018_DATA, DENALI_PHY_1019_DATA, +DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA, DENALI_PHY_1022_DATA, DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA, DENALI_PHY_1025_DATA, DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA, DENALI_PHY_1028_DATA, DENALI_PHY_1029_DATA, +DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA, DENALI_PHY_1032_DATA, DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA, DENALI_PHY_1035_DATA, DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA, DENALI_PHY_1038_DATA, DENALI_PHY_1039_DATA, +DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA, DENALI_PHY_1042_DATA, DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA, DENALI_PHY_1045_DATA, DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA, DENALI_PHY_1048_DATA, DENALI_PHY_1049_DATA, +DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA, DENALI_PHY_1052_DATA, DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA, DENALI_PHY_1055_DATA, DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA, DENALI_PHY_1058_DATA, DENALI_PHY_1059_DATA, +DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA, DENALI_PHY_1062_DATA, DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA, DENALI_PHY_1065_DATA, DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA, DENALI_PHY_1068_DATA, DENALI_PHY_1069_DATA, +DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA, DENALI_PHY_1072_DATA, DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA, DENALI_PHY_1075_DATA, DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA, DENALI_PHY_1078_DATA, DENALI_PHY_1079_DATA, +DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA, DENALI_PHY_1082_DATA, DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA, DENALI_PHY_1085_DATA, DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA, DENALI_PHY_1088_DATA, DENALI_PHY_1089_DATA, +DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA, DENALI_PHY_1092_DATA, DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA, DENALI_PHY_1095_DATA, DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA, DENALI_PHY_1098_DATA, DENALI_PHY_1099_DATA, + +DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA, DENALI_PHY_1102_DATA, DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA, DENALI_PHY_1105_DATA, DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA, DENALI_PHY_1108_DATA, DENALI_PHY_1109_DATA, +DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA, DENALI_PHY_1112_DATA, DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA, DENALI_PHY_1115_DATA, DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA, DENALI_PHY_1118_DATA, DENALI_PHY_1119_DATA, +DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA, DENALI_PHY_1122_DATA, DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA, DENALI_PHY_1125_DATA, DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA, DENALI_PHY_1128_DATA, DENALI_PHY_1129_DATA, +DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA, DENALI_PHY_1132_DATA, DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA, DENALI_PHY_1135_DATA, DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA, DENALI_PHY_1138_DATA, DENALI_PHY_1139_DATA, +DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA, DENALI_PHY_1142_DATA, DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA, DENALI_PHY_1145_DATA, DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA, DENALI_PHY_1148_DATA, DENALI_PHY_1149_DATA, +DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA, DENALI_PHY_1152_DATA, DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA, DENALI_PHY_1155_DATA, DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA, DENALI_PHY_1158_DATA, DENALI_PHY_1159_DATA, +DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA, DENALI_PHY_1162_DATA, DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA, DENALI_PHY_1165_DATA, DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA, DENALI_PHY_1168_DATA, DENALI_PHY_1169_DATA, +DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA, DENALI_PHY_1172_DATA, DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA, DENALI_PHY_1175_DATA, DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA, DENALI_PHY_1178_DATA, DENALI_PHY_1179_DATA, +DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA, DENALI_PHY_1182_DATA, DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA, DENALI_PHY_1185_DATA, DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA, DENALI_PHY_1188_DATA, DENALI_PHY_1189_DATA, +DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA, DENALI_PHY_1192_DATA, DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA, DENALI_PHY_1195_DATA, DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA, DENALI_PHY_1198_DATA, DENALI_PHY_1199_DATA, + +DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA, DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA, DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA, DENALI_PHY_1209_DATA, +DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA, DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA}; + + +uint32_t DENALI_CTL_DATA[265] = { +DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA, DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA, DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA, DENALI_CTL_09_DATA, +DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA, DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA, DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA, DENALI_CTL_19_DATA, +DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA, DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA, DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA, DENALI_CTL_29_DATA, +DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA, DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA, DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA, DENALI_CTL_39_DATA, +DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA, DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA, DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA, DENALI_CTL_49_DATA, +DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA, DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA, DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA, DENALI_CTL_59_DATA, +DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA, DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA, DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA, DENALI_CTL_69_DATA, +DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA, DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA, DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA, DENALI_CTL_79_DATA, +DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA, DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA, DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA, DENALI_CTL_89_DATA, +DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA, DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA, DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA, DENALI_CTL_99_DATA, + +DENALI_CTL_100_DATA, DENALI_CTL_101_DATA, DENALI_CTL_102_DATA, DENALI_CTL_103_DATA, DENALI_CTL_104_DATA, DENALI_CTL_105_DATA, DENALI_CTL_106_DATA, DENALI_CTL_107_DATA, DENALI_CTL_108_DATA, DENALI_CTL_109_DATA, +DENALI_CTL_110_DATA, DENALI_CTL_111_DATA, DENALI_CTL_112_DATA, DENALI_CTL_113_DATA, DENALI_CTL_114_DATA, DENALI_CTL_115_DATA, DENALI_CTL_116_DATA, DENALI_CTL_117_DATA, DENALI_CTL_118_DATA, DENALI_CTL_119_DATA, +DENALI_CTL_120_DATA, DENALI_CTL_121_DATA, DENALI_CTL_122_DATA, DENALI_CTL_123_DATA, DENALI_CTL_124_DATA, DENALI_CTL_125_DATA, DENALI_CTL_126_DATA, DENALI_CTL_127_DATA, DENALI_CTL_128_DATA, DENALI_CTL_129_DATA, +DENALI_CTL_130_DATA, DENALI_CTL_131_DATA, DENALI_CTL_132_DATA, DENALI_CTL_133_DATA, DENALI_CTL_134_DATA, DENALI_CTL_135_DATA, DENALI_CTL_136_DATA, DENALI_CTL_137_DATA, DENALI_CTL_138_DATA, DENALI_CTL_139_DATA, +DENALI_CTL_140_DATA, DENALI_CTL_141_DATA, DENALI_CTL_142_DATA, DENALI_CTL_143_DATA, DENALI_CTL_144_DATA, DENALI_CTL_145_DATA, DENALI_CTL_146_DATA, DENALI_CTL_147_DATA, DENALI_CTL_148_DATA, DENALI_CTL_149_DATA, +DENALI_CTL_150_DATA, DENALI_CTL_151_DATA, DENALI_CTL_152_DATA, DENALI_CTL_153_DATA, DENALI_CTL_154_DATA, DENALI_CTL_155_DATA, DENALI_CTL_156_DATA, DENALI_CTL_157_DATA, DENALI_CTL_158_DATA, DENALI_CTL_159_DATA, +DENALI_CTL_160_DATA, DENALI_CTL_161_DATA, DENALI_CTL_162_DATA, DENALI_CTL_163_DATA, DENALI_CTL_164_DATA, DENALI_CTL_165_DATA, DENALI_CTL_166_DATA, DENALI_CTL_167_DATA, DENALI_CTL_168_DATA, DENALI_CTL_169_DATA, +DENALI_CTL_170_DATA, DENALI_CTL_171_DATA, DENALI_CTL_172_DATA, DENALI_CTL_173_DATA, DENALI_CTL_174_DATA, DENALI_CTL_175_DATA, DENALI_CTL_176_DATA, DENALI_CTL_177_DATA, DENALI_CTL_178_DATA, DENALI_CTL_179_DATA, +DENALI_CTL_180_DATA, DENALI_CTL_181_DATA, DENALI_CTL_182_DATA, DENALI_CTL_183_DATA, DENALI_CTL_184_DATA, DENALI_CTL_185_DATA, DENALI_CTL_186_DATA, DENALI_CTL_187_DATA, DENALI_CTL_188_DATA, DENALI_CTL_189_DATA, +DENALI_CTL_190_DATA, DENALI_CTL_191_DATA, DENALI_CTL_192_DATA, DENALI_CTL_193_DATA, DENALI_CTL_194_DATA, DENALI_CTL_195_DATA, DENALI_CTL_196_DATA, DENALI_CTL_197_DATA, DENALI_CTL_198_DATA, DENALI_CTL_199_DATA, + +DENALI_CTL_200_DATA, DENALI_CTL_201_DATA, DENALI_CTL_202_DATA, DENALI_CTL_203_DATA, DENALI_CTL_204_DATA, DENALI_CTL_205_DATA, DENALI_CTL_206_DATA, DENALI_CTL_207_DATA, DENALI_CTL_208_DATA, DENALI_CTL_209_DATA, +DENALI_CTL_210_DATA, DENALI_CTL_211_DATA, DENALI_CTL_212_DATA, DENALI_CTL_213_DATA, DENALI_CTL_214_DATA, DENALI_CTL_215_DATA, DENALI_CTL_216_DATA, DENALI_CTL_217_DATA, DENALI_CTL_218_DATA, DENALI_CTL_219_DATA, +DENALI_CTL_220_DATA, DENALI_CTL_221_DATA, DENALI_CTL_222_DATA, DENALI_CTL_223_DATA, DENALI_CTL_224_DATA, DENALI_CTL_225_DATA, DENALI_CTL_226_DATA, DENALI_CTL_227_DATA, DENALI_CTL_228_DATA, DENALI_CTL_229_DATA, +DENALI_CTL_230_DATA, DENALI_CTL_231_DATA, DENALI_CTL_232_DATA, DENALI_CTL_233_DATA, DENALI_CTL_234_DATA, DENALI_CTL_235_DATA, DENALI_CTL_236_DATA, DENALI_CTL_237_DATA, DENALI_CTL_238_DATA, DENALI_CTL_239_DATA, +DENALI_CTL_240_DATA, DENALI_CTL_241_DATA, DENALI_CTL_242_DATA, DENALI_CTL_243_DATA, DENALI_CTL_244_DATA, DENALI_CTL_245_DATA, DENALI_CTL_246_DATA, DENALI_CTL_247_DATA, DENALI_CTL_248_DATA, DENALI_CTL_249_DATA, +DENALI_CTL_250_DATA, DENALI_CTL_251_DATA, DENALI_CTL_252_DATA, DENALI_CTL_253_DATA, DENALI_CTL_254_DATA, DENALI_CTL_255_DATA, DENALI_CTL_256_DATA, DENALI_CTL_257_DATA, DENALI_CTL_258_DATA, DENALI_CTL_259_DATA, +DENALI_CTL_260_DATA, DENALI_CTL_261_DATA, DENALI_CTL_262_DATA, DENALI_CTL_263_DATA, DENALI_CTL_264_DATA }; diff --git a/src/soc/sifive/fu540/regconfig-ctl.h b/src/soc/sifive/fu540/regconfig-ctl.h new file mode 100644 index 0000000..e76504d --- /dev/null +++ b/src/soc/sifive/fu540/regconfig-ctl.h @@ -0,0 +1,270 @@ +/* Copyright (c) 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* See the file LICENSE for further information */ + +#define DENALI_CTL_00_DATA 0x00000a00 +#define DENALI_CTL_01_DATA 0x00000000 +#define DENALI_CTL_02_DATA 0x00000000 +#define DENALI_CTL_03_DATA 0x00000000 +#define DENALI_CTL_04_DATA 0x00000000 +#define DENALI_CTL_05_DATA 0x00000000 +#define DENALI_CTL_06_DATA 0x0000000a +#define DENALI_CTL_07_DATA 0x0002d362 +#define DENALI_CTL_08_DATA 0x00071073 +#define DENALI_CTL_09_DATA 0x0a1c0255 +#define DENALI_CTL_10_DATA 0x1c1c0400 +#define DENALI_CTL_11_DATA 0x0404990b +#define DENALI_CTL_12_DATA 0x2b050405 +#define DENALI_CTL_13_DATA 0x0e0c081e +#define DENALI_CTL_14_DATA 0x08090914 +#define DENALI_CTL_15_DATA 0x00fde718 +#define DENALI_CTL_16_DATA 0x00180a05 +#define DENALI_CTL_17_DATA 0x008b130e +#define DENALI_CTL_18_DATA 0x01000118 +#define DENALI_CTL_19_DATA 0x0e032101 +#define DENALI_CTL_20_DATA 0x00000000 +#define DENALI_CTL_21_DATA 0x00000101 +#define DENALI_CTL_22_DATA 0x00000000 +#define DENALI_CTL_23_DATA 0x0a000000 +#define DENALI_CTL_24_DATA 0x00000000 +#define DENALI_CTL_25_DATA 0x01450100 +#define DENALI_CTL_26_DATA 0x00001c36 +#define DENALI_CTL_27_DATA 0x00000005 +#define DENALI_CTL_28_DATA 0x00170006 +#define DENALI_CTL_29_DATA 0x014e0300 +#define DENALI_CTL_30_DATA 0x03010000 +#define DENALI_CTL_31_DATA 0x000a0e00 +#define DENALI_CTL_32_DATA 0x04030200 +#define DENALI_CTL_33_DATA 0x0000031f +#define DENALI_CTL_34_DATA 0x00070004 +#define DENALI_CTL_35_DATA 0x00000000 +#define DENALI_CTL_36_DATA 0x00000000 +#define DENALI_CTL_37_DATA 0x00000000 +#define DENALI_CTL_38_DATA 0x00000000 +#define DENALI_CTL_39_DATA 0x00000000 +#define DENALI_CTL_40_DATA 0x00000000 +#define DENALI_CTL_41_DATA 0x00000000 +#define DENALI_CTL_42_DATA 0x00000000 +#define DENALI_CTL_43_DATA 0x00000000 +#define DENALI_CTL_44_DATA 0x00000000 +#define DENALI_CTL_45_DATA 0x00000000 +#define DENALI_CTL_46_DATA 0x00000000 +#define DENALI_CTL_47_DATA 0x00000000 +#define DENALI_CTL_48_DATA 0x00000000 +#define DENALI_CTL_49_DATA 0x00000000 +#define DENALI_CTL_50_DATA 0x00000000 +#define DENALI_CTL_51_DATA 0x00000000 +#define DENALI_CTL_52_DATA 0x00000000 +#define DENALI_CTL_53_DATA 0x00000000 +#define DENALI_CTL_54_DATA 0x00000000 +#define DENALI_CTL_55_DATA 0x00000000 +#define DENALI_CTL_56_DATA 0x00000000 +#define DENALI_CTL_57_DATA 0x00000000 +#define DENALI_CTL_58_DATA 0x00000000 +#define DENALI_CTL_59_DATA 0x00000000 +#define DENALI_CTL_60_DATA 0x00000424 +#define DENALI_CTL_61_DATA 0x00000201 +#define DENALI_CTL_62_DATA 0x00001008 +#define DENALI_CTL_63_DATA 0x00000000 +#define DENALI_CTL_64_DATA 0x00000200 +#define DENALI_CTL_65_DATA 0x00000000 +#define DENALI_CTL_66_DATA 0x00000481 +#define DENALI_CTL_67_DATA 0x00000400 +#define DENALI_CTL_68_DATA 0x00000424 +#define DENALI_CTL_69_DATA 0x00000201 +#define DENALI_CTL_70_DATA 0x00001008 +#define DENALI_CTL_71_DATA 0x00000000 +#define DENALI_CTL_72_DATA 0x00000200 +#define DENALI_CTL_73_DATA 0x00000000 +#define DENALI_CTL_74_DATA 0x00000481 +#define DENALI_CTL_75_DATA 0x00000400 +#define DENALI_CTL_76_DATA 0x01010000 +#define DENALI_CTL_77_DATA 0x00000000 +#define DENALI_CTL_78_DATA 0x00000000 +#define DENALI_CTL_79_DATA 0x00000000 +#define DENALI_CTL_80_DATA 0x00000000 +#define DENALI_CTL_81_DATA 0x00000000 +#define DENALI_CTL_82_DATA 0x00000000 +#define DENALI_CTL_83_DATA 0x00000000 +#define DENALI_CTL_84_DATA 0x00000000 +#define DENALI_CTL_85_DATA 0x00000000 +#define DENALI_CTL_86_DATA 0x00000000 +#define DENALI_CTL_87_DATA 0x00000000 +#define DENALI_CTL_88_DATA 0x00000000 +#define DENALI_CTL_89_DATA 0x00000000 +#define DENALI_CTL_90_DATA 0x00000000 +#define DENALI_CTL_91_DATA 0x00000000 +#define DENALI_CTL_92_DATA 0x00000000 +#define DENALI_CTL_93_DATA 0x00000000 +#define DENALI_CTL_94_DATA 0x00000000 +#define DENALI_CTL_95_DATA 0x00000000 +#define DENALI_CTL_96_DATA 0x00000000 +#define DENALI_CTL_97_DATA 0x00000000 +#define DENALI_CTL_98_DATA 0x00000000 +#define DENALI_CTL_99_DATA 0x00000000 +#define DENALI_CTL_100_DATA 0x00000000 +#define DENALI_CTL_101_DATA 0x00000000 +#define DENALI_CTL_102_DATA 0x00000000 +#define DENALI_CTL_103_DATA 0x00000000 +#define DENALI_CTL_104_DATA 0x00000000 +#define DENALI_CTL_105_DATA 0x00000003 +#define DENALI_CTL_106_DATA 0x00000000 +#define DENALI_CTL_107_DATA 0x00000000 +#define DENALI_CTL_108_DATA 0x00000000 +#define DENALI_CTL_109_DATA 0x00000000 +#define DENALI_CTL_110_DATA 0x01000000 +#define DENALI_CTL_111_DATA 0x00040000 +#define DENALI_CTL_112_DATA 0x00800200 +#define DENALI_CTL_113_DATA 0x00000200 +#define DENALI_CTL_114_DATA 0x00000040 +#define DENALI_CTL_115_DATA 0x01000100 +#define DENALI_CTL_116_DATA 0x0a000002 +#define DENALI_CTL_117_DATA 0x0101ffff +#define DENALI_CTL_118_DATA 0x01010101 +#define DENALI_CTL_119_DATA 0x01010101 +#define DENALI_CTL_120_DATA 0x0000010b +#define DENALI_CTL_121_DATA 0x00000c01 +#define DENALI_CTL_122_DATA 0x00000000 +#define DENALI_CTL_123_DATA 0x00000000 +#define DENALI_CTL_124_DATA 0x00000000 +#define DENALI_CTL_125_DATA 0x00000000 +#define DENALI_CTL_126_DATA 0x00030300 +#define DENALI_CTL_127_DATA 0x00000000 +#define DENALI_CTL_128_DATA 0x00010001 +#define DENALI_CTL_129_DATA 0x00000000 +#define DENALI_CTL_130_DATA 0x00000000 +#define DENALI_CTL_131_DATA 0x00000000 +#define DENALI_CTL_132_DATA 0x00000000 +#define DENALI_CTL_133_DATA 0x00000000 +#define DENALI_CTL_134_DATA 0x00000000 +#define DENALI_CTL_135_DATA 0x00000000 +#define DENALI_CTL_136_DATA 0x00000000 +#define DENALI_CTL_137_DATA 0x00000000 +#define DENALI_CTL_138_DATA 0x00000000 +#define DENALI_CTL_139_DATA 0x00000000 +#define DENALI_CTL_140_DATA 0x00000000 +#define DENALI_CTL_141_DATA 0x00000000 +#define DENALI_CTL_142_DATA 0x00000000 +#define DENALI_CTL_143_DATA 0x00000000 +#define DENALI_CTL_144_DATA 0x00000000 +#define DENALI_CTL_145_DATA 0x00000000 +#define DENALI_CTL_146_DATA 0x00000000 +#define DENALI_CTL_147_DATA 0x00000000 +#define DENALI_CTL_148_DATA 0x00000000 +#define DENALI_CTL_149_DATA 0x00000000 +#define DENALI_CTL_150_DATA 0x00000000 +#define DENALI_CTL_151_DATA 0x00000000 +#define DENALI_CTL_152_DATA 0x00000000 +#define DENALI_CTL_153_DATA 0x00000000 +#define DENALI_CTL_154_DATA 0x00000000 +#define DENALI_CTL_155_DATA 0x00000000 +#define DENALI_CTL_156_DATA 0x00000000 +#define DENALI_CTL_157_DATA 0x00000000 +#define DENALI_CTL_158_DATA 0x00000000 +#define DENALI_CTL_159_DATA 0x00000000 +#define DENALI_CTL_160_DATA 0x00000000 +#define DENALI_CTL_161_DATA 0x02010102 +#define DENALI_CTL_162_DATA 0x0107070d +#define DENALI_CTL_163_DATA 0x04040400 +#define DENALI_CTL_164_DATA 0x03000503 +#define DENALI_CTL_165_DATA 0x00000000 +#define DENALI_CTL_166_DATA 0x00000000 +#define DENALI_CTL_167_DATA 0x00000000 +#define DENALI_CTL_168_DATA 0x00000000 +#define DENALI_CTL_169_DATA 0x280d0000 +#define DENALI_CTL_170_DATA 0x01000000 +#define DENALI_CTL_171_DATA 0x00000000 +#define DENALI_CTL_172_DATA 0x00010001 +#define DENALI_CTL_173_DATA 0x00000000 +#define DENALI_CTL_174_DATA 0x00000000 +#define DENALI_CTL_175_DATA 0x00000000 +#define DENALI_CTL_176_DATA 0x00000000 +#define DENALI_CTL_177_DATA 0x00000000 +#define DENALI_CTL_178_DATA 0x00000000 +#define DENALI_CTL_179_DATA 0x00000000 +#define DENALI_CTL_180_DATA 0x00000000 +#define DENALI_CTL_181_DATA 0x01000000 +#define DENALI_CTL_182_DATA 0x00000001 +#define DENALI_CTL_183_DATA 0x00000100 +#define DENALI_CTL_184_DATA 0x00000101 +#define DENALI_CTL_185_DATA 0x67676701 +#define DENALI_CTL_186_DATA 0x67676767 +#define DENALI_CTL_187_DATA 0x67676767 +#define DENALI_CTL_188_DATA 0x67676767 +#define DENALI_CTL_189_DATA 0x67676767 +#define DENALI_CTL_190_DATA 0x67676767 +#define DENALI_CTL_191_DATA 0x67676767 +#define DENALI_CTL_192_DATA 0x67676767 +#define DENALI_CTL_193_DATA 0x67676767 +#define DENALI_CTL_194_DATA 0x01000067 +#define DENALI_CTL_195_DATA 0x00000001 +#define DENALI_CTL_196_DATA 0x00000101 +#define DENALI_CTL_197_DATA 0x00000000 +#define DENALI_CTL_198_DATA 0x00000000 +#define DENALI_CTL_199_DATA 0x00000000 +#define DENALI_CTL_200_DATA 0x00000000 +#define DENALI_CTL_201_DATA 0x00000000 +#define DENALI_CTL_202_DATA 0x00000000 +#define DENALI_CTL_203_DATA 0x00000000 +#define DENALI_CTL_204_DATA 0x00000000 +#define DENALI_CTL_205_DATA 0x00000000 +#define DENALI_CTL_206_DATA 0x00000000 +#define DENALI_CTL_207_DATA 0x00000000 +#define DENALI_CTL_208_DATA 0x00000001 +#define DENALI_CTL_209_DATA 0x00000000 +#define DENALI_CTL_210_DATA 0x007fffff +#define DENALI_CTL_211_DATA 0x00000000 +#define DENALI_CTL_212_DATA 0x007fffff +#define DENALI_CTL_213_DATA 0x00000000 +#define DENALI_CTL_214_DATA 0x007fffff +#define DENALI_CTL_215_DATA 0x00000000 +#define DENALI_CTL_216_DATA 0x007fffff +#define DENALI_CTL_217_DATA 0x00000000 +#define DENALI_CTL_218_DATA 0x007fffff +#define DENALI_CTL_219_DATA 0x00000000 +#define DENALI_CTL_220_DATA 0x007fffff +#define DENALI_CTL_221_DATA 0x00000000 +#define DENALI_CTL_222_DATA 0x007fffff +#define DENALI_CTL_223_DATA 0x00000000 +#define DENALI_CTL_224_DATA 0x037fffff +#define DENALI_CTL_225_DATA 0xffffffff +#define DENALI_CTL_226_DATA 0x000f000f +#define DENALI_CTL_227_DATA 0x00ffff03 +#define DENALI_CTL_228_DATA 0x000fffff +#define DENALI_CTL_229_DATA 0x0003000f +#define DENALI_CTL_230_DATA 0xffffffff +#define DENALI_CTL_231_DATA 0x000f000f +#define DENALI_CTL_232_DATA 0x00ffff03 +#define DENALI_CTL_233_DATA 0x000fffff +#define DENALI_CTL_234_DATA 0x0003000f +#define DENALI_CTL_235_DATA 0xffffffff +#define DENALI_CTL_236_DATA 0x000f000f +#define DENALI_CTL_237_DATA 0x00ffff03 +#define DENALI_CTL_238_DATA 0x000fffff +#define DENALI_CTL_239_DATA 0x0003000f +#define DENALI_CTL_240_DATA 0xffffffff +#define DENALI_CTL_241_DATA 0x000f000f +#define DENALI_CTL_242_DATA 0x00ffff03 +#define DENALI_CTL_243_DATA 0x000fffff +#define DENALI_CTL_244_DATA 0x6407000f +#define DENALI_CTL_245_DATA 0x01640001 +#define DENALI_CTL_246_DATA 0x00000000 +#define DENALI_CTL_247_DATA 0x00000000 +#define DENALI_CTL_248_DATA 0x00001700 +#define DENALI_CTL_249_DATA 0x00386c05 +#define DENALI_CTL_250_DATA 0x02000200 +#define DENALI_CTL_251_DATA 0x02000200 +#define DENALI_CTL_252_DATA 0x0000386c +#define DENALI_CTL_253_DATA 0x00023438 +#define DENALI_CTL_254_DATA 0x02020d10 +#define DENALI_CTL_255_DATA 0x00140303 +#define DENALI_CTL_256_DATA 0x00000000 +#define DENALI_CTL_257_DATA 0x00000000 +#define DENALI_CTL_258_DATA 0x00001403 +#define DENALI_CTL_259_DATA 0x00000000 +#define DENALI_CTL_260_DATA 0x00000000 +#define DENALI_CTL_261_DATA 0x00000000 +#define DENALI_CTL_262_DATA 0x00000000 +#define DENALI_CTL_263_DATA 0x0d010000 +#define DENALI_CTL_264_DATA 0x00000008 diff --git a/src/soc/sifive/fu540/regconfig-phy.h b/src/soc/sifive/fu540/regconfig-phy.h new file mode 100644 index 0000000..3deaa071 --- /dev/null +++ b/src/soc/sifive/fu540/regconfig-phy.h @@ -0,0 +1,1220 @@ +/* Copyright (c) 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* See the file LICENSE for further information */ + +#define DENALI_PHY_00_DATA 0x31706542 +#define DENALI_PHY_01_DATA 0x0004c008 +#define DENALI_PHY_02_DATA 0x000000da +#define DENALI_PHY_03_DATA 0x00000000 +#define DENALI_PHY_04_DATA 0x00000000 +#define DENALI_PHY_05_DATA 0x00010000 +#define DENALI_PHY_06_DATA 0x01DDDD90 +#define DENALI_PHY_07_DATA 0x01DDDD90 +#define DENALI_PHY_08_DATA 0x01030000 +#define DENALI_PHY_09_DATA 0x01000000 +#define DENALI_PHY_10_DATA 0x00c00000 +#define DENALI_PHY_11_DATA 0x00000007 +#define DENALI_PHY_12_DATA 0x00000000 +#define DENALI_PHY_13_DATA 0x00000000 +#define DENALI_PHY_14_DATA 0x04000408 +#define DENALI_PHY_15_DATA 0x00000408 +#define DENALI_PHY_16_DATA 0x00e4e400 +#define DENALI_PHY_17_DATA 0x00000000 +#define DENALI_PHY_18_DATA 0x00000000 +#define DENALI_PHY_19_DATA 0x00000000 +#define DENALI_PHY_20_DATA 0x00000000 +#define DENALI_PHY_21_DATA 0x00000000 +#define DENALI_PHY_22_DATA 0x00000000 +#define DENALI_PHY_23_DATA 0x00000000 +#define DENALI_PHY_24_DATA 0x00000000 +#define DENALI_PHY_25_DATA 0x00000000 +#define DENALI_PHY_26_DATA 0x00000000 +#define DENALI_PHY_27_DATA 0x00000000 +#define DENALI_PHY_28_DATA 0x00000000 +#define DENALI_PHY_29_DATA 0x00000000 +#define DENALI_PHY_30_DATA 0x00000000 +#define DENALI_PHY_31_DATA 0x00000000 +#define DENALI_PHY_32_DATA 0x00000000 +#define DENALI_PHY_33_DATA 0x00200000 +#define DENALI_PHY_34_DATA 0x00000000 +#define DENALI_PHY_35_DATA 0x00000000 +#define DENALI_PHY_36_DATA 0x00000000 +#define DENALI_PHY_37_DATA 0x00000000 +#define DENALI_PHY_38_DATA 0x00000000 +#define DENALI_PHY_39_DATA 0x00000000 +#define DENALI_PHY_40_DATA 0x02800280 +#define DENALI_PHY_41_DATA 0x02800280 +#define DENALI_PHY_42_DATA 0x02800280 +#define DENALI_PHY_43_DATA 0x02800280 +#define DENALI_PHY_44_DATA 0x00000280 +#define DENALI_PHY_45_DATA 0x00000000 +#define DENALI_PHY_46_DATA 0x00000000 +#define DENALI_PHY_47_DATA 0x00000000 +#define DENALI_PHY_48_DATA 0x00000000 +#define DENALI_PHY_49_DATA 0x00000000 +#define DENALI_PHY_50_DATA 0x00800080 +#define DENALI_PHY_51_DATA 0x00800080 +#define DENALI_PHY_52_DATA 0x00800080 +#define DENALI_PHY_53_DATA 0x00800080 +#define DENALI_PHY_54_DATA 0x00800080 +#define DENALI_PHY_55_DATA 0x00800080 +#define DENALI_PHY_56_DATA 0x00800080 +#define DENALI_PHY_57_DATA 0x00800080 +#define DENALI_PHY_58_DATA 0x00800080 +#define DENALI_PHY_59_DATA 0x000100da +#define DENALI_PHY_60_DATA 0x01000200 +#define DENALI_PHY_61_DATA 0x00000000 +#define DENALI_PHY_62_DATA 0x00000000 +#define DENALI_PHY_63_DATA 0x00000002 +#define DENALI_PHY_64_DATA 0x51313152 +#define DENALI_PHY_65_DATA 0x80013130 +#define DENALI_PHY_66_DATA 0x02000080 +#define DENALI_PHY_67_DATA 0x00100001 +#define DENALI_PHY_68_DATA 0x0c064208 +#define DENALI_PHY_69_DATA 0x000f0c0f +#define DENALI_PHY_70_DATA 0x01000140 +#define DENALI_PHY_71_DATA 0x0000000c +#define DENALI_PHY_72_DATA 0x00000000 +#define DENALI_PHY_73_DATA 0x00000000 +#define DENALI_PHY_74_DATA 0x00000000 +#define DENALI_PHY_75_DATA 0x00000000 +#define DENALI_PHY_76_DATA 0x00000000 +#define DENALI_PHY_77_DATA 0x00000000 +#define DENALI_PHY_78_DATA 0x00000000 +#define DENALI_PHY_79_DATA 0x00000000 +#define DENALI_PHY_80_DATA 0x00000000 +#define DENALI_PHY_81_DATA 0x00000000 +#define DENALI_PHY_82_DATA 0x00000000 +#define DENALI_PHY_83_DATA 0x00000000 +#define DENALI_PHY_84_DATA 0x00000000 +#define DENALI_PHY_85_DATA 0x00000000 +#define DENALI_PHY_86_DATA 0x00000000 +#define DENALI_PHY_87_DATA 0x00000000 +#define DENALI_PHY_88_DATA 0x00000000 +#define DENALI_PHY_89_DATA 0x00000000 +#define DENALI_PHY_90_DATA 0x00000000 +#define DENALI_PHY_91_DATA 0x00000000 +#define DENALI_PHY_92_DATA 0x00000000 +#define DENALI_PHY_93_DATA 0x00000000 +#define DENALI_PHY_94_DATA 0x00000000 +#define DENALI_PHY_95_DATA 0x00000000 +#define DENALI_PHY_96_DATA 0x00000000 +#define DENALI_PHY_97_DATA 0x00000000 +#define DENALI_PHY_98_DATA 0x00000000 +#define DENALI_PHY_99_DATA 0x00000000 +#define DENALI_PHY_100_DATA 0x00000000 +#define DENALI_PHY_101_DATA 0x00000000 +#define DENALI_PHY_102_DATA 0x00000000 +#define DENALI_PHY_103_DATA 0x00000000 +#define DENALI_PHY_104_DATA 0x00000000 +#define DENALI_PHY_105_DATA 0x00000000 +#define DENALI_PHY_106_DATA 0x00000000 +#define DENALI_PHY_107_DATA 0x00000000 +#define DENALI_PHY_108_DATA 0x00000000 +#define DENALI_PHY_109_DATA 0x00000000 +#define DENALI_PHY_110_DATA 0x00000000 +#define DENALI_PHY_111_DATA 0x00000000 +#define DENALI_PHY_112_DATA 0x00000000 +#define DENALI_PHY_113_DATA 0x00000000 +#define DENALI_PHY_114_DATA 0x00000000 +#define DENALI_PHY_115_DATA 0x00000000 +#define DENALI_PHY_116_DATA 0x00000000 +#define DENALI_PHY_117_DATA 0x00000000 +#define DENALI_PHY_118_DATA 0x00000000 +#define DENALI_PHY_119_DATA 0x00000000 +#define DENALI_PHY_120_DATA 0x00000000 +#define DENALI_PHY_121_DATA 0x00000000 +#define DENALI_PHY_122_DATA 0x00000000 +#define DENALI_PHY_123_DATA 0x00000000 +#define DENALI_PHY_124_DATA 0x00000000 +#define DENALI_PHY_125_DATA 0x00000000 +#define DENALI_PHY_126_DATA 0x00000000 +#define DENALI_PHY_127_DATA 0x00000000 +#define DENALI_PHY_128_DATA 0x40263571 +#define DENALI_PHY_129_DATA 0x0004c008 +#define DENALI_PHY_130_DATA 0x000000da +#define DENALI_PHY_131_DATA 0x00000000 +#define DENALI_PHY_132_DATA 0x00000000 +#define DENALI_PHY_133_DATA 0x00010000 +#define DENALI_PHY_134_DATA 0x01DDDD90 +#define DENALI_PHY_135_DATA 0x01DDDD90 +#define DENALI_PHY_136_DATA 0x01030000 +#define DENALI_PHY_137_DATA 0x01000000 +#define DENALI_PHY_138_DATA 0x00c00000 +#define DENALI_PHY_139_DATA 0x00000007 +#define DENALI_PHY_140_DATA 0x00000000 +#define DENALI_PHY_141_DATA 0x00000000 +#define DENALI_PHY_142_DATA 0x04000408 +#define DENALI_PHY_143_DATA 0x00000408 +#define DENALI_PHY_144_DATA 0x00e4e400 +#define DENALI_PHY_145_DATA 0x00000000 +#define DENALI_PHY_146_DATA 0x00000000 +#define DENALI_PHY_147_DATA 0x00000000 +#define DENALI_PHY_148_DATA 0x00000000 +#define DENALI_PHY_149_DATA 0x00000000 +#define DENALI_PHY_150_DATA 0x00000000 +#define DENALI_PHY_151_DATA 0x00000000 +#define DENALI_PHY_152_DATA 0x00000000 +#define DENALI_PHY_153_DATA 0x00000000 +#define DENALI_PHY_154_DATA 0x00000000 +#define DENALI_PHY_155_DATA 0x00000000 +#define DENALI_PHY_156_DATA 0x00000000 +#define DENALI_PHY_157_DATA 0x00000000 +#define DENALI_PHY_158_DATA 0x00000000 +#define DENALI_PHY_159_DATA 0x00000000 +#define DENALI_PHY_160_DATA 0x00000000 +#define DENALI_PHY_161_DATA 0x00200000 +#define DENALI_PHY_162_DATA 0x00000000 +#define DENALI_PHY_163_DATA 0x00000000 +#define DENALI_PHY_164_DATA 0x00000000 +#define DENALI_PHY_165_DATA 0x00000000 +#define DENALI_PHY_166_DATA 0x00000000 +#define DENALI_PHY_167_DATA 0x00000000 +#define DENALI_PHY_168_DATA 0x02800280 +#define DENALI_PHY_169_DATA 0x02800280 +#define DENALI_PHY_170_DATA 0x02800280 +#define DENALI_PHY_171_DATA 0x02800280 +#define DENALI_PHY_172_DATA 0x00000280 +#define DENALI_PHY_173_DATA 0x00000000 +#define DENALI_PHY_174_DATA 0x00000000 +#define DENALI_PHY_175_DATA 0x00000000 +#define DENALI_PHY_176_DATA 0x00000000 +#define DENALI_PHY_177_DATA 0x00000000 +#define DENALI_PHY_178_DATA 0x00800080 +#define DENALI_PHY_179_DATA 0x00800080 +#define DENALI_PHY_180_DATA 0x00800080 +#define DENALI_PHY_181_DATA 0x00800080 +#define DENALI_PHY_182_DATA 0x00800080 +#define DENALI_PHY_183_DATA 0x00800080 +#define DENALI_PHY_184_DATA 0x00800080 +#define DENALI_PHY_185_DATA 0x00800080 +#define DENALI_PHY_186_DATA 0x00800080 +#define DENALI_PHY_187_DATA 0x000100da +#define DENALI_PHY_188_DATA 0x01000200 +#define DENALI_PHY_189_DATA 0x00000000 +#define DENALI_PHY_190_DATA 0x00000000 +#define DENALI_PHY_191_DATA 0x00000002 +#define DENALI_PHY_192_DATA 0x51313152 +#define DENALI_PHY_193_DATA 0x80013130 +#define DENALI_PHY_194_DATA 0x02000080 +#define DENALI_PHY_195_DATA 0x00100001 +#define DENALI_PHY_196_DATA 0x0c064208 +#define DENALI_PHY_197_DATA 0x000f0c0f +#define DENALI_PHY_198_DATA 0x01000140 +#define DENALI_PHY_199_DATA 0x0000000c +#define DENALI_PHY_200_DATA 0x00000000 +#define DENALI_PHY_201_DATA 0x00000000 +#define DENALI_PHY_202_DATA 0x00000000 +#define DENALI_PHY_203_DATA 0x00000000 +#define DENALI_PHY_204_DATA 0x00000000 +#define DENALI_PHY_205_DATA 0x00000000 +#define DENALI_PHY_206_DATA 0x00000000 +#define DENALI_PHY_207_DATA 0x00000000 +#define DENALI_PHY_208_DATA 0x00000000 +#define DENALI_PHY_209_DATA 0x00000000 +#define DENALI_PHY_210_DATA 0x00000000 +#define DENALI_PHY_211_DATA 0x00000000 +#define DENALI_PHY_212_DATA 0x00000000 +#define DENALI_PHY_213_DATA 0x00000000 +#define DENALI_PHY_214_DATA 0x00000000 +#define DENALI_PHY_215_DATA 0x00000000 +#define DENALI_PHY_216_DATA 0x00000000 +#define DENALI_PHY_217_DATA 0x00000000 +#define DENALI_PHY_218_DATA 0x00000000 +#define DENALI_PHY_219_DATA 0x00000000 +#define DENALI_PHY_220_DATA 0x00000000 +#define DENALI_PHY_221_DATA 0x00000000 +#define DENALI_PHY_222_DATA 0x00000000 +#define DENALI_PHY_223_DATA 0x00000000 +#define DENALI_PHY_224_DATA 0x00000000 +#define DENALI_PHY_225_DATA 0x00000000 +#define DENALI_PHY_226_DATA 0x00000000 +#define DENALI_PHY_227_DATA 0x00000000 +#define DENALI_PHY_228_DATA 0x00000000 +#define DENALI_PHY_229_DATA 0x00000000 +#define DENALI_PHY_230_DATA 0x00000000 +#define DENALI_PHY_231_DATA 0x00000000 +#define DENALI_PHY_232_DATA 0x00000000 +#define DENALI_PHY_233_DATA 0x00000000 +#define DENALI_PHY_234_DATA 0x00000000 +#define DENALI_PHY_235_DATA 0x00000000 +#define DENALI_PHY_236_DATA 0x00000000 +#define DENALI_PHY_237_DATA 0x00000000 +#define DENALI_PHY_238_DATA 0x00000000 +#define DENALI_PHY_239_DATA 0x00000000 +#define DENALI_PHY_240_DATA 0x00000000 +#define DENALI_PHY_241_DATA 0x00000000 +#define DENALI_PHY_242_DATA 0x00000000 +#define DENALI_PHY_243_DATA 0x00000000 +#define DENALI_PHY_244_DATA 0x00000000 +#define DENALI_PHY_245_DATA 0x00000000 +#define DENALI_PHY_246_DATA 0x00000000 +#define DENALI_PHY_247_DATA 0x00000000 +#define DENALI_PHY_248_DATA 0x00000000 +#define DENALI_PHY_249_DATA 0x00000000 +#define DENALI_PHY_250_DATA 0x00000000 +#define DENALI_PHY_251_DATA 0x00000000 +#define DENALI_PHY_252_DATA 0x00000000 +#define DENALI_PHY_253_DATA 0x00000000 +#define DENALI_PHY_254_DATA 0x00000000 +#define DENALI_PHY_255_DATA 0x00000000 +#define DENALI_PHY_256_DATA 0x46052371 +#define DENALI_PHY_257_DATA 0x0004c008 +#define DENALI_PHY_258_DATA 0x000000da +#define DENALI_PHY_259_DATA 0x00000000 +#define DENALI_PHY_260_DATA 0x00000000 +#define DENALI_PHY_261_DATA 0x00010000 +#define DENALI_PHY_262_DATA 0x01DDDD90 +#define DENALI_PHY_263_DATA 0x01DDDD90 +#define DENALI_PHY_264_DATA 0x01030000 +#define DENALI_PHY_265_DATA 0x01000000 +#define DENALI_PHY_266_DATA 0x00c00000 +#define DENALI_PHY_267_DATA 0x00000007 +#define DENALI_PHY_268_DATA 0x00000000 +#define DENALI_PHY_269_DATA 0x00000000 +#define DENALI_PHY_270_DATA 0x04000408 +#define DENALI_PHY_271_DATA 0x00000408 +#define DENALI_PHY_272_DATA 0x00e4e400 +#define DENALI_PHY_273_DATA 0x00000000 +#define DENALI_PHY_274_DATA 0x00000000 +#define DENALI_PHY_275_DATA 0x00000000 +#define DENALI_PHY_276_DATA 0x00000000 +#define DENALI_PHY_277_DATA 0x00000000 +#define DENALI_PHY_278_DATA 0x00000000 +#define DENALI_PHY_279_DATA 0x00000000 +#define DENALI_PHY_280_DATA 0x00000000 +#define DENALI_PHY_281_DATA 0x00000000 +#define DENALI_PHY_282_DATA 0x00000000 +#define DENALI_PHY_283_DATA 0x00000000 +#define DENALI_PHY_284_DATA 0x00000000 +#define DENALI_PHY_285_DATA 0x00000000 +#define DENALI_PHY_286_DATA 0x00000000 +#define DENALI_PHY_287_DATA 0x00000000 +#define DENALI_PHY_288_DATA 0x00000000 +#define DENALI_PHY_289_DATA 0x00200000 +#define DENALI_PHY_290_DATA 0x00000000 +#define DENALI_PHY_291_DATA 0x00000000 +#define DENALI_PHY_292_DATA 0x00000000 +#define DENALI_PHY_293_DATA 0x00000000 +#define DENALI_PHY_294_DATA 0x00000000 +#define DENALI_PHY_295_DATA 0x00000000 +#define DENALI_PHY_296_DATA 0x02800280 +#define DENALI_PHY_297_DATA 0x02800280 +#define DENALI_PHY_298_DATA 0x02800280 +#define DENALI_PHY_299_DATA 0x02800280 +#define DENALI_PHY_300_DATA 0x00000280 +#define DENALI_PHY_301_DATA 0x00000000 +#define DENALI_PHY_302_DATA 0x00000000 +#define DENALI_PHY_303_DATA 0x00000000 +#define DENALI_PHY_304_DATA 0x00000000 +#define DENALI_PHY_305_DATA 0x00000000 +#define DENALI_PHY_306_DATA 0x00800080 +#define DENALI_PHY_307_DATA 0x00800080 +#define DENALI_PHY_308_DATA 0x00800080 +#define DENALI_PHY_309_DATA 0x00800080 +#define DENALI_PHY_310_DATA 0x00800080 +#define DENALI_PHY_311_DATA 0x00800080 +#define DENALI_PHY_312_DATA 0x00800080 +#define DENALI_PHY_313_DATA 0x00800080 +#define DENALI_PHY_314_DATA 0x00800080 +#define DENALI_PHY_315_DATA 0x000100da +#define DENALI_PHY_316_DATA 0x00000200 +#define DENALI_PHY_317_DATA 0x00000000 +#define DENALI_PHY_318_DATA 0x00000000 +#define DENALI_PHY_319_DATA 0x00000002 +#define DENALI_PHY_320_DATA 0x51313152 +#define DENALI_PHY_321_DATA 0x80013130 +#define DENALI_PHY_322_DATA 0x02000080 +#define DENALI_PHY_323_DATA 0x00100001 +#define DENALI_PHY_324_DATA 0x0c064208 +#define DENALI_PHY_325_DATA 0x000f0c0f +#define DENALI_PHY_326_DATA 0x01000140 +#define DENALI_PHY_327_DATA 0x0000000c +#define DENALI_PHY_328_DATA 0x00000000 +#define DENALI_PHY_329_DATA 0x00000000 +#define DENALI_PHY_330_DATA 0x00000000 +#define DENALI_PHY_331_DATA 0x00000000 +#define DENALI_PHY_332_DATA 0x00000000 +#define DENALI_PHY_333_DATA 0x00000000 +#define DENALI_PHY_334_DATA 0x00000000 +#define DENALI_PHY_335_DATA 0x00000000 +#define DENALI_PHY_336_DATA 0x00000000 +#define DENALI_PHY_337_DATA 0x00000000 +#define DENALI_PHY_338_DATA 0x00000000 +#define DENALI_PHY_339_DATA 0x00000000 +#define DENALI_PHY_340_DATA 0x00000000 +#define DENALI_PHY_341_DATA 0x00000000 +#define DENALI_PHY_342_DATA 0x00000000 +#define DENALI_PHY_343_DATA 0x00000000 +#define DENALI_PHY_344_DATA 0x00000000 +#define DENALI_PHY_345_DATA 0x00000000 +#define DENALI_PHY_346_DATA 0x00000000 +#define DENALI_PHY_347_DATA 0x00000000 +#define DENALI_PHY_348_DATA 0x00000000 +#define DENALI_PHY_349_DATA 0x00000000 +#define DENALI_PHY_350_DATA 0x00000000 +#define DENALI_PHY_351_DATA 0x00000000 +#define DENALI_PHY_352_DATA 0x00000000 +#define DENALI_PHY_353_DATA 0x00000000 +#define DENALI_PHY_354_DATA 0x00000000 +#define DENALI_PHY_355_DATA 0x00000000 +#define DENALI_PHY_356_DATA 0x00000000 +#define DENALI_PHY_357_DATA 0x00000000 +#define DENALI_PHY_358_DATA 0x00000000 +#define DENALI_PHY_359_DATA 0x00000000 +#define DENALI_PHY_360_DATA 0x00000000 +#define DENALI_PHY_361_DATA 0x00000000 +#define DENALI_PHY_362_DATA 0x00000000 +#define DENALI_PHY_363_DATA 0x00000000 +#define DENALI_PHY_364_DATA 0x00000000 +#define DENALI_PHY_365_DATA 0x00000000 +#define DENALI_PHY_366_DATA 0x00000000 +#define DENALI_PHY_367_DATA 0x00000000 +#define DENALI_PHY_368_DATA 0x00000000 +#define DENALI_PHY_369_DATA 0x00000000 +#define DENALI_PHY_370_DATA 0x00000000 +#define DENALI_PHY_371_DATA 0x00000000 +#define DENALI_PHY_372_DATA 0x00000000 +#define DENALI_PHY_373_DATA 0x00000000 +#define DENALI_PHY_374_DATA 0x00000000 +#define DENALI_PHY_375_DATA 0x00000000 +#define DENALI_PHY_376_DATA 0x00000000 +#define DENALI_PHY_377_DATA 0x00000000 +#define DENALI_PHY_378_DATA 0x00000000 +#define DENALI_PHY_379_DATA 0x00000000 +#define DENALI_PHY_380_DATA 0x00000000 +#define DENALI_PHY_381_DATA 0x00000000 +#define DENALI_PHY_382_DATA 0x00000000 +#define DENALI_PHY_383_DATA 0x00000000 +#define DENALI_PHY_384_DATA 0x37654120 +#define DENALI_PHY_385_DATA 0x0004c008 +#define DENALI_PHY_386_DATA 0x000000da +#define DENALI_PHY_387_DATA 0x00000000 +#define DENALI_PHY_388_DATA 0x00000000 +#define DENALI_PHY_389_DATA 0x00010000 +#define DENALI_PHY_390_DATA 0x01DDDD90 +#define DENALI_PHY_391_DATA 0x01DDDD90 +#define DENALI_PHY_392_DATA 0x01030000 +#define DENALI_PHY_393_DATA 0x01000000 +#define DENALI_PHY_394_DATA 0x00c00000 +#define DENALI_PHY_395_DATA 0x00000007 +#define DENALI_PHY_396_DATA 0x00000000 +#define DENALI_PHY_397_DATA 0x00000000 +#define DENALI_PHY_398_DATA 0x04000408 +#define DENALI_PHY_399_DATA 0x00000408 +#define DENALI_PHY_400_DATA 0x00e4e400 +#define DENALI_PHY_401_DATA 0x00000000 +#define DENALI_PHY_402_DATA 0x00000000 +#define DENALI_PHY_403_DATA 0x00000000 +#define DENALI_PHY_404_DATA 0x00000000 +#define DENALI_PHY_405_DATA 0x00000000 +#define DENALI_PHY_406_DATA 0x00000000 +#define DENALI_PHY_407_DATA 0x00000000 +#define DENALI_PHY_408_DATA 0x00000000 +#define DENALI_PHY_409_DATA 0x00000000 +#define DENALI_PHY_410_DATA 0x00000000 +#define DENALI_PHY_411_DATA 0x00000000 +#define DENALI_PHY_412_DATA 0x00000000 +#define DENALI_PHY_413_DATA 0x00000000 +#define DENALI_PHY_414_DATA 0x00000000 +#define DENALI_PHY_415_DATA 0x00000000 +#define DENALI_PHY_416_DATA 0x00000000 +#define DENALI_PHY_417_DATA 0x00200000 +#define DENALI_PHY_418_DATA 0x00000000 +#define DENALI_PHY_419_DATA 0x00000000 +#define DENALI_PHY_420_DATA 0x00000000 +#define DENALI_PHY_421_DATA 0x00000000 +#define DENALI_PHY_422_DATA 0x00000000 +#define DENALI_PHY_423_DATA 0x00000000 +#define DENALI_PHY_424_DATA 0x02800280 +#define DENALI_PHY_425_DATA 0x02800280 +#define DENALI_PHY_426_DATA 0x02800280 +#define DENALI_PHY_427_DATA 0x02800280 +#define DENALI_PHY_428_DATA 0x00000280 +#define DENALI_PHY_429_DATA 0x00000000 +#define DENALI_PHY_430_DATA 0x00000000 +#define DENALI_PHY_431_DATA 0x00000000 +#define DENALI_PHY_432_DATA 0x00000000 +#define DENALI_PHY_433_DATA 0x00000000 +#define DENALI_PHY_434_DATA 0x00800080 +#define DENALI_PHY_435_DATA 0x00800080 +#define DENALI_PHY_436_DATA 0x00800080 +#define DENALI_PHY_437_DATA 0x00800080 +#define DENALI_PHY_438_DATA 0x00800080 +#define DENALI_PHY_439_DATA 0x00800080 +#define DENALI_PHY_440_DATA 0x00800080 +#define DENALI_PHY_441_DATA 0x00800080 +#define DENALI_PHY_442_DATA 0x00800080 +#define DENALI_PHY_443_DATA 0x000100da +#define DENALI_PHY_444_DATA 0x00000200 +#define DENALI_PHY_445_DATA 0x00000000 +#define DENALI_PHY_446_DATA 0x00000000 +#define DENALI_PHY_447_DATA 0x00000002 +#define DENALI_PHY_448_DATA 0x51313152 +#define DENALI_PHY_449_DATA 0x80013130 +#define DENALI_PHY_450_DATA 0x02000080 +#define DENALI_PHY_451_DATA 0x00100001 +#define DENALI_PHY_452_DATA 0x0c064208 +#define DENALI_PHY_453_DATA 0x000f0c0f +#define DENALI_PHY_454_DATA 0x01000140 +#define DENALI_PHY_455_DATA 0x0000000c +#define DENALI_PHY_456_DATA 0x00000000 +#define DENALI_PHY_457_DATA 0x00000000 +#define DENALI_PHY_458_DATA 0x00000000 +#define DENALI_PHY_459_DATA 0x00000000 +#define DENALI_PHY_460_DATA 0x00000000 +#define DENALI_PHY_461_DATA 0x00000000 +#define DENALI_PHY_462_DATA 0x00000000 +#define DENALI_PHY_463_DATA 0x00000000 +#define DENALI_PHY_464_DATA 0x00000000 +#define DENALI_PHY_465_DATA 0x00000000 +#define DENALI_PHY_466_DATA 0x00000000 +#define DENALI_PHY_467_DATA 0x00000000 +#define DENALI_PHY_468_DATA 0x00000000 +#define DENALI_PHY_469_DATA 0x00000000 +#define DENALI_PHY_470_DATA 0x00000000 +#define DENALI_PHY_471_DATA 0x00000000 +#define DENALI_PHY_472_DATA 0x00000000 +#define DENALI_PHY_473_DATA 0x00000000 +#define DENALI_PHY_474_DATA 0x00000000 +#define DENALI_PHY_475_DATA 0x00000000 +#define DENALI_PHY_476_DATA 0x00000000 +#define DENALI_PHY_477_DATA 0x00000000 +#define DENALI_PHY_478_DATA 0x00000000 +#define DENALI_PHY_479_DATA 0x00000000 +#define DENALI_PHY_480_DATA 0x00000000 +#define DENALI_PHY_481_DATA 0x00000000 +#define DENALI_PHY_482_DATA 0x00000000 +#define DENALI_PHY_483_DATA 0x00000000 +#define DENALI_PHY_484_DATA 0x00000000 +#define DENALI_PHY_485_DATA 0x00000000 +#define DENALI_PHY_486_DATA 0x00000000 +#define DENALI_PHY_487_DATA 0x00000000 +#define DENALI_PHY_488_DATA 0x00000000 +#define DENALI_PHY_489_DATA 0x00000000 +#define DENALI_PHY_490_DATA 0x00000000 +#define DENALI_PHY_491_DATA 0x00000000 +#define DENALI_PHY_492_DATA 0x00000000 +#define DENALI_PHY_493_DATA 0x00000000 +#define DENALI_PHY_494_DATA 0x00000000 +#define DENALI_PHY_495_DATA 0x00000000 +#define DENALI_PHY_496_DATA 0x00000000 +#define DENALI_PHY_497_DATA 0x00000000 +#define DENALI_PHY_498_DATA 0x00000000 +#define DENALI_PHY_499_DATA 0x00000000 +#define DENALI_PHY_500_DATA 0x00000000 +#define DENALI_PHY_501_DATA 0x00000000 +#define DENALI_PHY_502_DATA 0x00000000 +#define DENALI_PHY_503_DATA 0x00000000 +#define DENALI_PHY_504_DATA 0x00000000 +#define DENALI_PHY_505_DATA 0x00000000 +#define DENALI_PHY_506_DATA 0x00000000 +#define DENALI_PHY_507_DATA 0x00000000 +#define DENALI_PHY_508_DATA 0x00000000 +#define DENALI_PHY_509_DATA 0x00000000 +#define DENALI_PHY_510_DATA 0x00000000 +#define DENALI_PHY_511_DATA 0x00000000 +#define DENALI_PHY_512_DATA 0x24316750 +#define DENALI_PHY_513_DATA 0x0004c008 +#define DENALI_PHY_514_DATA 0x000000da +#define DENALI_PHY_515_DATA 0x00000000 +#define DENALI_PHY_516_DATA 0x00000000 +#define DENALI_PHY_517_DATA 0x00010000 +#define DENALI_PHY_518_DATA 0x01DDDD90 +#define DENALI_PHY_519_DATA 0x01DDDD90 +#define DENALI_PHY_520_DATA 0x01030000 +#define DENALI_PHY_521_DATA 0x01000000 +#define DENALI_PHY_522_DATA 0x00c00000 +#define DENALI_PHY_523_DATA 0x00000007 +#define DENALI_PHY_524_DATA 0x00000000 +#define DENALI_PHY_525_DATA 0x00000000 +#define DENALI_PHY_526_DATA 0x04000408 +#define DENALI_PHY_527_DATA 0x00000408 +#define DENALI_PHY_528_DATA 0x00e4e400 +#define DENALI_PHY_529_DATA 0x00000000 +#define DENALI_PHY_530_DATA 0x00000000 +#define DENALI_PHY_531_DATA 0x00000000 +#define DENALI_PHY_532_DATA 0x00000000 +#define DENALI_PHY_533_DATA 0x00000000 +#define DENALI_PHY_534_DATA 0x00000000 +#define DENALI_PHY_535_DATA 0x00000000 +#define DENALI_PHY_536_DATA 0x00000000 +#define DENALI_PHY_537_DATA 0x00000000 +#define DENALI_PHY_538_DATA 0x00000000 +#define DENALI_PHY_539_DATA 0x00000000 +#define DENALI_PHY_540_DATA 0x00000000 +#define DENALI_PHY_541_DATA 0x00000000 +#define DENALI_PHY_542_DATA 0x00000000 +#define DENALI_PHY_543_DATA 0x00000000 +#define DENALI_PHY_544_DATA 0x00000000 +#define DENALI_PHY_545_DATA 0x00200000 +#define DENALI_PHY_546_DATA 0x00000000 +#define DENALI_PHY_547_DATA 0x00000000 +#define DENALI_PHY_548_DATA 0x00000000 +#define DENALI_PHY_549_DATA 0x00000000 +#define DENALI_PHY_550_DATA 0x00000000 +#define DENALI_PHY_551_DATA 0x00000000 +#define DENALI_PHY_552_DATA 0x02800280 +#define DENALI_PHY_553_DATA 0x02800280 +#define DENALI_PHY_554_DATA 0x02800280 +#define DENALI_PHY_555_DATA 0x02800280 +#define DENALI_PHY_556_DATA 0x00000280 +#define DENALI_PHY_557_DATA 0x00000000 +#define DENALI_PHY_558_DATA 0x00000000 +#define DENALI_PHY_559_DATA 0x00000000 +#define DENALI_PHY_560_DATA 0x00000000 +#define DENALI_PHY_561_DATA 0x00000000 +#define DENALI_PHY_562_DATA 0x00800080 +#define DENALI_PHY_563_DATA 0x00800080 +#define DENALI_PHY_564_DATA 0x00800080 +#define DENALI_PHY_565_DATA 0x00800080 +#define DENALI_PHY_566_DATA 0x00800080 +#define DENALI_PHY_567_DATA 0x00800080 +#define DENALI_PHY_568_DATA 0x00800080 +#define DENALI_PHY_569_DATA 0x00800080 +#define DENALI_PHY_570_DATA 0x00800080 +#define DENALI_PHY_571_DATA 0x000100da +#define DENALI_PHY_572_DATA 0x00000200 +#define DENALI_PHY_573_DATA 0x00000000 +#define DENALI_PHY_574_DATA 0x00000000 +#define DENALI_PHY_575_DATA 0x00000002 +#define DENALI_PHY_576_DATA 0x51313152 +#define DENALI_PHY_577_DATA 0x80013130 +#define DENALI_PHY_578_DATA 0x02000080 +#define DENALI_PHY_579_DATA 0x00100001 +#define DENALI_PHY_580_DATA 0x0c064208 +#define DENALI_PHY_581_DATA 0x000f0c0f +#define DENALI_PHY_582_DATA 0x01000140 +#define DENALI_PHY_583_DATA 0x0000000c +#define DENALI_PHY_584_DATA 0x00000000 +#define DENALI_PHY_585_DATA 0x00000000 +#define DENALI_PHY_586_DATA 0x00000000 +#define DENALI_PHY_587_DATA 0x00000000 +#define DENALI_PHY_588_DATA 0x00000000 +#define DENALI_PHY_589_DATA 0x00000000 +#define DENALI_PHY_590_DATA 0x00000000 +#define DENALI_PHY_591_DATA 0x00000000 +#define DENALI_PHY_592_DATA 0x00000000 +#define DENALI_PHY_593_DATA 0x00000000 +#define DENALI_PHY_594_DATA 0x00000000 +#define DENALI_PHY_595_DATA 0x00000000 +#define DENALI_PHY_596_DATA 0x00000000 +#define DENALI_PHY_597_DATA 0x00000000 +#define DENALI_PHY_598_DATA 0x00000000 +#define DENALI_PHY_599_DATA 0x00000000 +#define DENALI_PHY_600_DATA 0x00000000 +#define DENALI_PHY_601_DATA 0x00000000 +#define DENALI_PHY_602_DATA 0x00000000 +#define DENALI_PHY_603_DATA 0x00000000 +#define DENALI_PHY_604_DATA 0x00000000 +#define DENALI_PHY_605_DATA 0x00000000 +#define DENALI_PHY_606_DATA 0x00000000 +#define DENALI_PHY_607_DATA 0x00000000 +#define DENALI_PHY_608_DATA 0x00000000 +#define DENALI_PHY_609_DATA 0x00000000 +#define DENALI_PHY_610_DATA 0x00000000 +#define DENALI_PHY_611_DATA 0x00000000 +#define DENALI_PHY_612_DATA 0x00000000 +#define DENALI_PHY_613_DATA 0x00000000 +#define DENALI_PHY_614_DATA 0x00000000 +#define DENALI_PHY_615_DATA 0x00000000 +#define DENALI_PHY_616_DATA 0x00000000 +#define DENALI_PHY_617_DATA 0x00000000 +#define DENALI_PHY_618_DATA 0x00000000 +#define DENALI_PHY_619_DATA 0x00000000 +#define DENALI_PHY_620_DATA 0x00000000 +#define DENALI_PHY_621_DATA 0x00000000 +#define DENALI_PHY_622_DATA 0x00000000 +#define DENALI_PHY_623_DATA 0x00000000 +#define DENALI_PHY_624_DATA 0x00000000 +#define DENALI_PHY_625_DATA 0x00000000 +#define DENALI_PHY_626_DATA 0x00000000 +#define DENALI_PHY_627_DATA 0x00000000 +#define DENALI_PHY_628_DATA 0x00000000 +#define DENALI_PHY_629_DATA 0x00000000 +#define DENALI_PHY_630_DATA 0x00000000 +#define DENALI_PHY_631_DATA 0x00000000 +#define DENALI_PHY_632_DATA 0x00000000 +#define DENALI_PHY_633_DATA 0x00000000 +#define DENALI_PHY_634_DATA 0x00000000 +#define DENALI_PHY_635_DATA 0x00000000 +#define DENALI_PHY_636_DATA 0x00000000 +#define DENALI_PHY_637_DATA 0x00000000 +#define DENALI_PHY_638_DATA 0x00000000 +#define DENALI_PHY_639_DATA 0x00000000 +#define DENALI_PHY_640_DATA 0x35174620 +#define DENALI_PHY_641_DATA 0x0004c008 +#define DENALI_PHY_642_DATA 0x000000da +#define DENALI_PHY_643_DATA 0x00000000 +#define DENALI_PHY_644_DATA 0x00000000 +#define DENALI_PHY_645_DATA 0x00010000 +#define DENALI_PHY_646_DATA 0x01DDDD90 +#define DENALI_PHY_647_DATA 0x01DDDD90 +#define DENALI_PHY_648_DATA 0x01030000 +#define DENALI_PHY_649_DATA 0x01000000 +#define DENALI_PHY_650_DATA 0x00c00000 +#define DENALI_PHY_651_DATA 0x00000007 +#define DENALI_PHY_652_DATA 0x00000000 +#define DENALI_PHY_653_DATA 0x00000000 +#define DENALI_PHY_654_DATA 0x04000408 +#define DENALI_PHY_655_DATA 0x00000408 +#define DENALI_PHY_656_DATA 0x00e4e400 +#define DENALI_PHY_657_DATA 0x00000000 +#define DENALI_PHY_658_DATA 0x00000000 +#define DENALI_PHY_659_DATA 0x00000000 +#define DENALI_PHY_660_DATA 0x00000000 +#define DENALI_PHY_661_DATA 0x00000000 +#define DENALI_PHY_662_DATA 0x00000000 +#define DENALI_PHY_663_DATA 0x00000000 +#define DENALI_PHY_664_DATA 0x00000000 +#define DENALI_PHY_665_DATA 0x00000000 +#define DENALI_PHY_666_DATA 0x00000000 +#define DENALI_PHY_667_DATA 0x00000000 +#define DENALI_PHY_668_DATA 0x00000000 +#define DENALI_PHY_669_DATA 0x00000000 +#define DENALI_PHY_670_DATA 0x00000000 +#define DENALI_PHY_671_DATA 0x00000000 +#define DENALI_PHY_672_DATA 0x00000000 +#define DENALI_PHY_673_DATA 0x00200000 +#define DENALI_PHY_674_DATA 0x00000000 +#define DENALI_PHY_675_DATA 0x00000000 +#define DENALI_PHY_676_DATA 0x00000000 +#define DENALI_PHY_677_DATA 0x00000000 +#define DENALI_PHY_678_DATA 0x00000000 +#define DENALI_PHY_679_DATA 0x00000000 +#define DENALI_PHY_680_DATA 0x02800280 +#define DENALI_PHY_681_DATA 0x02800280 +#define DENALI_PHY_682_DATA 0x02800280 +#define DENALI_PHY_683_DATA 0x02800280 +#define DENALI_PHY_684_DATA 0x00000280 +#define DENALI_PHY_685_DATA 0x00000000 +#define DENALI_PHY_686_DATA 0x00000000 +#define DENALI_PHY_687_DATA 0x00000000 +#define DENALI_PHY_688_DATA 0x00000000 +#define DENALI_PHY_689_DATA 0x00000000 +#define DENALI_PHY_690_DATA 0x00800080 +#define DENALI_PHY_691_DATA 0x00800080 +#define DENALI_PHY_692_DATA 0x00800080 +#define DENALI_PHY_693_DATA 0x00800080 +#define DENALI_PHY_694_DATA 0x00800080 +#define DENALI_PHY_695_DATA 0x00800080 +#define DENALI_PHY_696_DATA 0x00800080 +#define DENALI_PHY_697_DATA 0x00800080 +#define DENALI_PHY_698_DATA 0x00800080 +#define DENALI_PHY_699_DATA 0x000100da +#define DENALI_PHY_700_DATA 0x00000200 +#define DENALI_PHY_701_DATA 0x00000000 +#define DENALI_PHY_702_DATA 0x00000000 +#define DENALI_PHY_703_DATA 0x00000002 +#define DENALI_PHY_704_DATA 0x51313152 +#define DENALI_PHY_705_DATA 0x80013130 +#define DENALI_PHY_706_DATA 0x02000080 +#define DENALI_PHY_707_DATA 0x00100001 +#define DENALI_PHY_708_DATA 0x0c064208 +#define DENALI_PHY_709_DATA 0x000f0c0f +#define DENALI_PHY_710_DATA 0x01000140 +#define DENALI_PHY_711_DATA 0x0000000c +#define DENALI_PHY_712_DATA 0x00000000 +#define DENALI_PHY_713_DATA 0x00000000 +#define DENALI_PHY_714_DATA 0x00000000 +#define DENALI_PHY_715_DATA 0x00000000 +#define DENALI_PHY_716_DATA 0x00000000 +#define DENALI_PHY_717_DATA 0x00000000 +#define DENALI_PHY_718_DATA 0x00000000 +#define DENALI_PHY_719_DATA 0x00000000 +#define DENALI_PHY_720_DATA 0x00000000 +#define DENALI_PHY_721_DATA 0x00000000 +#define DENALI_PHY_722_DATA 0x00000000 +#define DENALI_PHY_723_DATA 0x00000000 +#define DENALI_PHY_724_DATA 0x00000000 +#define DENALI_PHY_725_DATA 0x00000000 +#define DENALI_PHY_726_DATA 0x00000000 +#define DENALI_PHY_727_DATA 0x00000000 +#define DENALI_PHY_728_DATA 0x00000000 +#define DENALI_PHY_729_DATA 0x00000000 +#define DENALI_PHY_730_DATA 0x00000000 +#define DENALI_PHY_731_DATA 0x00000000 +#define DENALI_PHY_732_DATA 0x00000000 +#define DENALI_PHY_733_DATA 0x00000000 +#define DENALI_PHY_734_DATA 0x00000000 +#define DENALI_PHY_735_DATA 0x00000000 +#define DENALI_PHY_736_DATA 0x00000000 +#define DENALI_PHY_737_DATA 0x00000000 +#define DENALI_PHY_738_DATA 0x00000000 +#define DENALI_PHY_739_DATA 0x00000000 +#define DENALI_PHY_740_DATA 0x00000000 +#define DENALI_PHY_741_DATA 0x00000000 +#define DENALI_PHY_742_DATA 0x00000000 +#define DENALI_PHY_743_DATA 0x00000000 +#define DENALI_PHY_744_DATA 0x00000000 +#define DENALI_PHY_745_DATA 0x00000000 +#define DENALI_PHY_746_DATA 0x00000000 +#define DENALI_PHY_747_DATA 0x00000000 +#define DENALI_PHY_748_DATA 0x00000000 +#define DENALI_PHY_749_DATA 0x00000000 +#define DENALI_PHY_750_DATA 0x00000000 +#define DENALI_PHY_751_DATA 0x00000000 +#define DENALI_PHY_752_DATA 0x00000000 +#define DENALI_PHY_753_DATA 0x00000000 +#define DENALI_PHY_754_DATA 0x00000000 +#define DENALI_PHY_755_DATA 0x00000000 +#define DENALI_PHY_756_DATA 0x00000000 +#define DENALI_PHY_757_DATA 0x00000000 +#define DENALI_PHY_758_DATA 0x00000000 +#define DENALI_PHY_759_DATA 0x00000000 +#define DENALI_PHY_760_DATA 0x00000000 +#define DENALI_PHY_761_DATA 0x00000000 +#define DENALI_PHY_762_DATA 0x00000000 +#define DENALI_PHY_763_DATA 0x00000000 +#define DENALI_PHY_764_DATA 0x00000000 +#define DENALI_PHY_765_DATA 0x00000000 +#define DENALI_PHY_766_DATA 0x00000000 +#define DENALI_PHY_767_DATA 0x00000000 +#define DENALI_PHY_768_DATA 0x15203476 +#define DENALI_PHY_769_DATA 0x0004c008 +#define DENALI_PHY_770_DATA 0x000000da +#define DENALI_PHY_771_DATA 0x00000000 +#define DENALI_PHY_772_DATA 0x00000000 +#define DENALI_PHY_773_DATA 0x00010000 +#define DENALI_PHY_774_DATA 0x01DDDD90 +#define DENALI_PHY_775_DATA 0x01DDDD90 +#define DENALI_PHY_776_DATA 0x01030000 +#define DENALI_PHY_777_DATA 0x01000000 +#define DENALI_PHY_778_DATA 0x00c00000 +#define DENALI_PHY_779_DATA 0x00000007 +#define DENALI_PHY_780_DATA 0x00000000 +#define DENALI_PHY_781_DATA 0x00000000 +#define DENALI_PHY_782_DATA 0x04000408 +#define DENALI_PHY_783_DATA 0x00000408 +#define DENALI_PHY_784_DATA 0x00e4e400 +#define DENALI_PHY_785_DATA 0x00000000 +#define DENALI_PHY_786_DATA 0x00000000 +#define DENALI_PHY_787_DATA 0x00000000 +#define DENALI_PHY_788_DATA 0x00000000 +#define DENALI_PHY_789_DATA 0x00000000 +#define DENALI_PHY_790_DATA 0x00000000 +#define DENALI_PHY_791_DATA 0x00000000 +#define DENALI_PHY_792_DATA 0x00000000 +#define DENALI_PHY_793_DATA 0x00000000 +#define DENALI_PHY_794_DATA 0x00000000 +#define DENALI_PHY_795_DATA 0x00000000 +#define DENALI_PHY_796_DATA 0x00000000 +#define DENALI_PHY_797_DATA 0x00000000 +#define DENALI_PHY_798_DATA 0x00000000 +#define DENALI_PHY_799_DATA 0x00000000 +#define DENALI_PHY_800_DATA 0x00000000 +#define DENALI_PHY_801_DATA 0x00200000 +#define DENALI_PHY_802_DATA 0x00000000 +#define DENALI_PHY_803_DATA 0x00000000 +#define DENALI_PHY_804_DATA 0x00000000 +#define DENALI_PHY_805_DATA 0x00000000 +#define DENALI_PHY_806_DATA 0x00000000 +#define DENALI_PHY_807_DATA 0x00000000 +#define DENALI_PHY_808_DATA 0x02800280 +#define DENALI_PHY_809_DATA 0x02800280 +#define DENALI_PHY_810_DATA 0x02800280 +#define DENALI_PHY_811_DATA 0x02800280 +#define DENALI_PHY_812_DATA 0x00000280 +#define DENALI_PHY_813_DATA 0x00000000 +#define DENALI_PHY_814_DATA 0x00000000 +#define DENALI_PHY_815_DATA 0x00000000 +#define DENALI_PHY_816_DATA 0x00000000 +#define DENALI_PHY_817_DATA 0x00000000 +#define DENALI_PHY_818_DATA 0x00800080 +#define DENALI_PHY_819_DATA 0x00800080 +#define DENALI_PHY_820_DATA 0x00800080 +#define DENALI_PHY_821_DATA 0x00800080 +#define DENALI_PHY_822_DATA 0x00800080 +#define DENALI_PHY_823_DATA 0x00800080 +#define DENALI_PHY_824_DATA 0x00800080 +#define DENALI_PHY_825_DATA 0x00800080 +#define DENALI_PHY_826_DATA 0x00800080 +#define DENALI_PHY_827_DATA 0x000100da +#define DENALI_PHY_828_DATA 0x00000200 +#define DENALI_PHY_829_DATA 0x00000000 +#define DENALI_PHY_830_DATA 0x00000000 +#define DENALI_PHY_831_DATA 0x00000002 +#define DENALI_PHY_832_DATA 0x51313152 +#define DENALI_PHY_833_DATA 0x80013130 +#define DENALI_PHY_834_DATA 0x02000080 +#define DENALI_PHY_835_DATA 0x00100001 +#define DENALI_PHY_836_DATA 0x0c064208 +#define DENALI_PHY_837_DATA 0x000f0c0f +#define DENALI_PHY_838_DATA 0x01000140 +#define DENALI_PHY_839_DATA 0x0000000c +#define DENALI_PHY_840_DATA 0x00000000 +#define DENALI_PHY_841_DATA 0x00000000 +#define DENALI_PHY_842_DATA 0x00000000 +#define DENALI_PHY_843_DATA 0x00000000 +#define DENALI_PHY_844_DATA 0x00000000 +#define DENALI_PHY_845_DATA 0x00000000 +#define DENALI_PHY_846_DATA 0x00000000 +#define DENALI_PHY_847_DATA 0x00000000 +#define DENALI_PHY_848_DATA 0x00000000 +#define DENALI_PHY_849_DATA 0x00000000 +#define DENALI_PHY_850_DATA 0x00000000 +#define DENALI_PHY_851_DATA 0x00000000 +#define DENALI_PHY_852_DATA 0x00000000 +#define DENALI_PHY_853_DATA 0x00000000 +#define DENALI_PHY_854_DATA 0x00000000 +#define DENALI_PHY_855_DATA 0x00000000 +#define DENALI_PHY_856_DATA 0x00000000 +#define DENALI_PHY_857_DATA 0x00000000 +#define DENALI_PHY_858_DATA 0x00000000 +#define DENALI_PHY_859_DATA 0x00000000 +#define DENALI_PHY_860_DATA 0x00000000 +#define DENALI_PHY_861_DATA 0x00000000 +#define DENALI_PHY_862_DATA 0x00000000 +#define DENALI_PHY_863_DATA 0x00000000 +#define DENALI_PHY_864_DATA 0x00000000 +#define DENALI_PHY_865_DATA 0x00000000 +#define DENALI_PHY_866_DATA 0x00000000 +#define DENALI_PHY_867_DATA 0x00000000 +#define DENALI_PHY_868_DATA 0x00000000 +#define DENALI_PHY_869_DATA 0x00000000 +#define DENALI_PHY_870_DATA 0x00000000 +#define DENALI_PHY_871_DATA 0x00000000 +#define DENALI_PHY_872_DATA 0x00000000 +#define DENALI_PHY_873_DATA 0x00000000 +#define DENALI_PHY_874_DATA 0x00000000 +#define DENALI_PHY_875_DATA 0x00000000 +#define DENALI_PHY_876_DATA 0x00000000 +#define DENALI_PHY_877_DATA 0x00000000 +#define DENALI_PHY_878_DATA 0x00000000 +#define DENALI_PHY_879_DATA 0x00000000 +#define DENALI_PHY_880_DATA 0x00000000 +#define DENALI_PHY_881_DATA 0x00000000 +#define DENALI_PHY_882_DATA 0x00000000 +#define DENALI_PHY_883_DATA 0x00000000 +#define DENALI_PHY_884_DATA 0x00000000 +#define DENALI_PHY_885_DATA 0x00000000 +#define DENALI_PHY_886_DATA 0x00000000 +#define DENALI_PHY_887_DATA 0x00000000 +#define DENALI_PHY_888_DATA 0x00000000 +#define DENALI_PHY_889_DATA 0x00000000 +#define DENALI_PHY_890_DATA 0x00000000 +#define DENALI_PHY_891_DATA 0x00000000 +#define DENALI_PHY_892_DATA 0x00000000 +#define DENALI_PHY_893_DATA 0x00000000 +#define DENALI_PHY_894_DATA 0x00000000 +#define DENALI_PHY_895_DATA 0x00000000 +#define DENALI_PHY_896_DATA 0x41753206 +#define DENALI_PHY_897_DATA 0x0004c008 +#define DENALI_PHY_898_DATA 0x000000da +#define DENALI_PHY_899_DATA 0x00000000 +#define DENALI_PHY_900_DATA 0x00000000 +#define DENALI_PHY_901_DATA 0x00010000 +#define DENALI_PHY_902_DATA 0x01DDDD90 +#define DENALI_PHY_903_DATA 0x01DDDD90 +#define DENALI_PHY_904_DATA 0x01030000 +#define DENALI_PHY_905_DATA 0x01000000 +#define DENALI_PHY_906_DATA 0x00c00000 +#define DENALI_PHY_907_DATA 0x00000007 +#define DENALI_PHY_908_DATA 0x00000000 +#define DENALI_PHY_909_DATA 0x00000000 +#define DENALI_PHY_910_DATA 0x04000408 +#define DENALI_PHY_911_DATA 0x00000408 +#define DENALI_PHY_912_DATA 0x00e4e400 +#define DENALI_PHY_913_DATA 0x00000000 +#define DENALI_PHY_914_DATA 0x00000000 +#define DENALI_PHY_915_DATA 0x00000000 +#define DENALI_PHY_916_DATA 0x00000000 +#define DENALI_PHY_917_DATA 0x00000000 +#define DENALI_PHY_918_DATA 0x00000000 +#define DENALI_PHY_919_DATA 0x00000000 +#define DENALI_PHY_920_DATA 0x00000000 +#define DENALI_PHY_921_DATA 0x00000000 +#define DENALI_PHY_922_DATA 0x00000000 +#define DENALI_PHY_923_DATA 0x00000000 +#define DENALI_PHY_924_DATA 0x00000000 +#define DENALI_PHY_925_DATA 0x00000000 +#define DENALI_PHY_926_DATA 0x00000000 +#define DENALI_PHY_927_DATA 0x00000000 +#define DENALI_PHY_928_DATA 0x00000000 +#define DENALI_PHY_929_DATA 0x00200000 +#define DENALI_PHY_930_DATA 0x00000000 +#define DENALI_PHY_931_DATA 0x00000000 +#define DENALI_PHY_932_DATA 0x00000000 +#define DENALI_PHY_933_DATA 0x00000000 +#define DENALI_PHY_934_DATA 0x00000000 +#define DENALI_PHY_935_DATA 0x00000000 +#define DENALI_PHY_936_DATA 0x02800280 +#define DENALI_PHY_937_DATA 0x02800280 +#define DENALI_PHY_938_DATA 0x02800280 +#define DENALI_PHY_939_DATA 0x02800280 +#define DENALI_PHY_940_DATA 0x00000280 +#define DENALI_PHY_941_DATA 0x00000000 +#define DENALI_PHY_942_DATA 0x00000000 +#define DENALI_PHY_943_DATA 0x00000000 +#define DENALI_PHY_944_DATA 0x00000000 +#define DENALI_PHY_945_DATA 0x00000000 +#define DENALI_PHY_946_DATA 0x00800080 +#define DENALI_PHY_947_DATA 0x00800080 +#define DENALI_PHY_948_DATA 0x00800080 +#define DENALI_PHY_949_DATA 0x00800080 +#define DENALI_PHY_950_DATA 0x00800080 +#define DENALI_PHY_951_DATA 0x00800080 +#define DENALI_PHY_952_DATA 0x00800080 +#define DENALI_PHY_953_DATA 0x00800080 +#define DENALI_PHY_954_DATA 0x00800080 +#define DENALI_PHY_955_DATA 0x000100da +#define DENALI_PHY_956_DATA 0x00000200 +#define DENALI_PHY_957_DATA 0x00000000 +#define DENALI_PHY_958_DATA 0x00000000 +#define DENALI_PHY_959_DATA 0x00000002 +#define DENALI_PHY_960_DATA 0x51313152 +#define DENALI_PHY_961_DATA 0x80013130 +#define DENALI_PHY_962_DATA 0x02000080 +#define DENALI_PHY_963_DATA 0x00100001 +#define DENALI_PHY_964_DATA 0x0c064208 +#define DENALI_PHY_965_DATA 0x000f0c0f +#define DENALI_PHY_966_DATA 0x01000140 +#define DENALI_PHY_967_DATA 0x0000000c +#define DENALI_PHY_968_DATA 0x00000000 +#define DENALI_PHY_969_DATA 0x00000000 +#define DENALI_PHY_970_DATA 0x00000000 +#define DENALI_PHY_971_DATA 0x00000000 +#define DENALI_PHY_972_DATA 0x00000000 +#define DENALI_PHY_973_DATA 0x00000000 +#define DENALI_PHY_974_DATA 0x00000000 +#define DENALI_PHY_975_DATA 0x00000000 +#define DENALI_PHY_976_DATA 0x00000000 +#define DENALI_PHY_977_DATA 0x00000000 +#define DENALI_PHY_978_DATA 0x00000000 +#define DENALI_PHY_979_DATA 0x00000000 +#define DENALI_PHY_980_DATA 0x00000000 +#define DENALI_PHY_981_DATA 0x00000000 +#define DENALI_PHY_982_DATA 0x00000000 +#define DENALI_PHY_983_DATA 0x00000000 +#define DENALI_PHY_984_DATA 0x00000000 +#define DENALI_PHY_985_DATA 0x00000000 +#define DENALI_PHY_986_DATA 0x00000000 +#define DENALI_PHY_987_DATA 0x00000000 +#define DENALI_PHY_988_DATA 0x00000000 +#define DENALI_PHY_989_DATA 0x00000000 +#define DENALI_PHY_990_DATA 0x00000000 +#define DENALI_PHY_991_DATA 0x00000000 +#define DENALI_PHY_992_DATA 0x00000000 +#define DENALI_PHY_993_DATA 0x00000000 +#define DENALI_PHY_994_DATA 0x00000000 +#define DENALI_PHY_995_DATA 0x00000000 +#define DENALI_PHY_996_DATA 0x00000000 +#define DENALI_PHY_997_DATA 0x00000000 +#define DENALI_PHY_998_DATA 0x00000000 +#define DENALI_PHY_999_DATA 0x00000000 +#define DENALI_PHY_1000_DATA 0x00000000 +#define DENALI_PHY_1001_DATA 0x00000000 +#define DENALI_PHY_1002_DATA 0x00000000 +#define DENALI_PHY_1003_DATA 0x00000000 +#define DENALI_PHY_1004_DATA 0x00000000 +#define DENALI_PHY_1005_DATA 0x00000000 +#define DENALI_PHY_1006_DATA 0x00000000 +#define DENALI_PHY_1007_DATA 0x00000000 +#define DENALI_PHY_1008_DATA 0x00000000 +#define DENALI_PHY_1009_DATA 0x00000000 +#define DENALI_PHY_1010_DATA 0x00000000 +#define DENALI_PHY_1011_DATA 0x00000000 +#define DENALI_PHY_1012_DATA 0x00000000 +#define DENALI_PHY_1013_DATA 0x00000000 +#define DENALI_PHY_1014_DATA 0x00000000 +#define DENALI_PHY_1015_DATA 0x00000000 +#define DENALI_PHY_1016_DATA 0x00000000 +#define DENALI_PHY_1017_DATA 0x00000000 +#define DENALI_PHY_1018_DATA 0x00000000 +#define DENALI_PHY_1019_DATA 0x00000000 +#define DENALI_PHY_1020_DATA 0x00000000 +#define DENALI_PHY_1021_DATA 0x00000000 +#define DENALI_PHY_1022_DATA 0x00000000 +#define DENALI_PHY_1023_DATA 0x00000000 +#define DENALI_PHY_1024_DATA 0x36025174 +#define DENALI_PHY_1025_DATA 0x0004c008 +#define DENALI_PHY_1026_DATA 0x000000da +#define DENALI_PHY_1027_DATA 0x00000000 +#define DENALI_PHY_1028_DATA 0x00000000 +#define DENALI_PHY_1029_DATA 0x00010000 +#define DENALI_PHY_1030_DATA 0x01DDDD90 +#define DENALI_PHY_1031_DATA 0x01DDDD90 +#define DENALI_PHY_1032_DATA 0x01030000 +#define DENALI_PHY_1033_DATA 0x01000000 +#define DENALI_PHY_1034_DATA 0x00c00000 +#define DENALI_PHY_1035_DATA 0x00000007 +#define DENALI_PHY_1036_DATA 0x00000000 +#define DENALI_PHY_1037_DATA 0x00000000 +#define DENALI_PHY_1038_DATA 0x04000408 +#define DENALI_PHY_1039_DATA 0x00000408 +#define DENALI_PHY_1040_DATA 0x00e4e400 +#define DENALI_PHY_1041_DATA 0x00000000 +#define DENALI_PHY_1042_DATA 0x00000000 +#define DENALI_PHY_1043_DATA 0x00000000 +#define DENALI_PHY_1044_DATA 0x00000000 +#define DENALI_PHY_1045_DATA 0x00000000 +#define DENALI_PHY_1046_DATA 0x00000000 +#define DENALI_PHY_1047_DATA 0x00000000 +#define DENALI_PHY_1048_DATA 0x00000000 +#define DENALI_PHY_1049_DATA 0x00000000 +#define DENALI_PHY_1050_DATA 0x00000000 +#define DENALI_PHY_1051_DATA 0x00000000 +#define DENALI_PHY_1052_DATA 0x00000000 +#define DENALI_PHY_1053_DATA 0x00000000 +#define DENALI_PHY_1054_DATA 0x00000000 +#define DENALI_PHY_1055_DATA 0x00000000 +#define DENALI_PHY_1056_DATA 0x00000000 +#define DENALI_PHY_1057_DATA 0x00200000 +#define DENALI_PHY_1058_DATA 0x00000000 +#define DENALI_PHY_1059_DATA 0x00000000 +#define DENALI_PHY_1060_DATA 0x00000000 +#define DENALI_PHY_1061_DATA 0x00000000 +#define DENALI_PHY_1062_DATA 0x00000000 +#define DENALI_PHY_1063_DATA 0x00000000 +#define DENALI_PHY_1064_DATA 0x02800280 +#define DENALI_PHY_1065_DATA 0x02800280 +#define DENALI_PHY_1066_DATA 0x02800280 +#define DENALI_PHY_1067_DATA 0x02800280 +#define DENALI_PHY_1068_DATA 0x00000280 +#define DENALI_PHY_1069_DATA 0x00000000 +#define DENALI_PHY_1070_DATA 0x00000000 +#define DENALI_PHY_1071_DATA 0x00000000 +#define DENALI_PHY_1072_DATA 0x00000000 +#define DENALI_PHY_1073_DATA 0x00000000 +#define DENALI_PHY_1074_DATA 0x00800080 +#define DENALI_PHY_1075_DATA 0x00800080 +#define DENALI_PHY_1076_DATA 0x00800080 +#define DENALI_PHY_1077_DATA 0x00800080 +#define DENALI_PHY_1078_DATA 0x00800080 +#define DENALI_PHY_1079_DATA 0x00800080 +#define DENALI_PHY_1080_DATA 0x00800080 +#define DENALI_PHY_1081_DATA 0x00800080 +#define DENALI_PHY_1082_DATA 0x00800080 +#define DENALI_PHY_1083_DATA 0x000100da +#define DENALI_PHY_1084_DATA 0x00000200 +#define DENALI_PHY_1085_DATA 0x00000000 +#define DENALI_PHY_1086_DATA 0x00000000 +#define DENALI_PHY_1087_DATA 0x00000002 +#define DENALI_PHY_1088_DATA 0x51313152 +#define DENALI_PHY_1089_DATA 0x80013130 +#define DENALI_PHY_1090_DATA 0x02000080 +#define DENALI_PHY_1091_DATA 0x00100001 +#define DENALI_PHY_1092_DATA 0x0c064208 +#define DENALI_PHY_1093_DATA 0x000f0c0f +#define DENALI_PHY_1094_DATA 0x01000140 +#define DENALI_PHY_1095_DATA 0x0000000c +#define DENALI_PHY_1096_DATA 0x00000000 +#define DENALI_PHY_1097_DATA 0x00000000 +#define DENALI_PHY_1098_DATA 0x00000000 +#define DENALI_PHY_1099_DATA 0x00000000 +#define DENALI_PHY_1100_DATA 0x00000000 +#define DENALI_PHY_1101_DATA 0x00000000 +#define DENALI_PHY_1102_DATA 0x00000000 +#define DENALI_PHY_1103_DATA 0x00000000 +#define DENALI_PHY_1104_DATA 0x00000000 +#define DENALI_PHY_1105_DATA 0x00000000 +#define DENALI_PHY_1106_DATA 0x00000000 +#define DENALI_PHY_1107_DATA 0x00000000 +#define DENALI_PHY_1108_DATA 0x00000000 +#define DENALI_PHY_1109_DATA 0x00000000 +#define DENALI_PHY_1110_DATA 0x00000000 +#define DENALI_PHY_1111_DATA 0x00000000 +#define DENALI_PHY_1112_DATA 0x00000000 +#define DENALI_PHY_1113_DATA 0x00000000 +#define DENALI_PHY_1114_DATA 0x00000000 +#define DENALI_PHY_1115_DATA 0x00000000 +#define DENALI_PHY_1116_DATA 0x00000000 +#define DENALI_PHY_1117_DATA 0x00000000 +#define DENALI_PHY_1118_DATA 0x00000000 +#define DENALI_PHY_1119_DATA 0x00000000 +#define DENALI_PHY_1120_DATA 0x00000000 +#define DENALI_PHY_1121_DATA 0x00000000 +#define DENALI_PHY_1122_DATA 0x00000000 +#define DENALI_PHY_1123_DATA 0x00000000 +#define DENALI_PHY_1124_DATA 0x00000000 +#define DENALI_PHY_1125_DATA 0x00000000 +#define DENALI_PHY_1126_DATA 0x00000000 +#define DENALI_PHY_1127_DATA 0x00000000 +#define DENALI_PHY_1128_DATA 0x00000000 +#define DENALI_PHY_1129_DATA 0x00000000 +#define DENALI_PHY_1130_DATA 0x00000000 +#define DENALI_PHY_1131_DATA 0x00000000 +#define DENALI_PHY_1132_DATA 0x00000000 +#define DENALI_PHY_1133_DATA 0x00000000 +#define DENALI_PHY_1134_DATA 0x00000000 +#define DENALI_PHY_1135_DATA 0x00000000 +#define DENALI_PHY_1136_DATA 0x00000000 +#define DENALI_PHY_1137_DATA 0x00000000 +#define DENALI_PHY_1138_DATA 0x00000000 +#define DENALI_PHY_1139_DATA 0x00000000 +#define DENALI_PHY_1140_DATA 0x00000000 +#define DENALI_PHY_1141_DATA 0x00000000 +#define DENALI_PHY_1142_DATA 0x00000000 +#define DENALI_PHY_1143_DATA 0x00000000 +#define DENALI_PHY_1144_DATA 0x00000000 +#define DENALI_PHY_1145_DATA 0x00000000 +#define DENALI_PHY_1146_DATA 0x00000000 +#define DENALI_PHY_1147_DATA 0x00000000 +#define DENALI_PHY_1148_DATA 0x00000000 +#define DENALI_PHY_1149_DATA 0x00000000 +#define DENALI_PHY_1150_DATA 0x00000000 +#define DENALI_PHY_1151_DATA 0x00000000 +#define DENALI_PHY_1152_DATA 0x00000000 +#define DENALI_PHY_1153_DATA 0x00000000 +#define DENALI_PHY_1154_DATA 0x00050000 +#define DENALI_PHY_1155_DATA 0x00000000 +#define DENALI_PHY_1156_DATA 0x00000000 +#define DENALI_PHY_1157_DATA 0x00000000 +#define DENALI_PHY_1158_DATA 0x00000100 +#define DENALI_PHY_1159_DATA 0x00000000 +#define DENALI_PHY_1160_DATA 0x00000000 +#define DENALI_PHY_1161_DATA 0x00506401 +#define DENALI_PHY_1162_DATA 0x01221102 +#define DENALI_PHY_1163_DATA 0x00000122 +#define DENALI_PHY_1164_DATA 0x00000000 +#define DENALI_PHY_1165_DATA 0x000B1F00 +#define DENALI_PHY_1166_DATA 0x0B1F0B1F +#define DENALI_PHY_1167_DATA 0x0B1F0B1B +#define DENALI_PHY_1168_DATA 0x0B1F0B1F +#define DENALI_PHY_1169_DATA 0x0B1F0B1F +#define DENALI_PHY_1170_DATA 0x00000B00 +#define DENALI_PHY_1171_DATA 0x42080010 +#define DENALI_PHY_1172_DATA 0x01000100 +#define DENALI_PHY_1173_DATA 0x01000100 +#define DENALI_PHY_1174_DATA 0x01000100 +#define DENALI_PHY_1175_DATA 0x01000100 +#define DENALI_PHY_1176_DATA 0x00000000 +#define DENALI_PHY_1177_DATA 0x00000000 +#define DENALI_PHY_1178_DATA 0x00000000 +#define DENALI_PHY_1179_DATA 0x00000000 +#define DENALI_PHY_1180_DATA 0x00000000 +#define DENALI_PHY_1181_DATA 0x00000803 +#define DENALI_PHY_1182_DATA 0x223FFF00 +#define DENALI_PHY_1183_DATA 0x000008FF +#define DENALI_PHY_1184_DATA 0x0000057F +#define DENALI_PHY_1185_DATA 0x0000057F +#define DENALI_PHY_1186_DATA 0x00037FFF +#define DENALI_PHY_1187_DATA 0x00037FFF +#define DENALI_PHY_1188_DATA 0x00004410 +#define DENALI_PHY_1189_DATA 0x00004410 +#define DENALI_PHY_1190_DATA 0x00004410 +#define DENALI_PHY_1191_DATA 0x00004410 +#define DENALI_PHY_1192_DATA 0x00004410 +#define DENALI_PHY_1193_DATA 0x00037FFF +#define DENALI_PHY_1194_DATA 0x00037FFF +#define DENALI_PHY_1195_DATA 0x00000000 +#define DENALI_PHY_1196_DATA 0x00000000 +#define DENALI_PHY_1197_DATA 0x00000000 +#define DENALI_PHY_1198_DATA 0x04000000 +#define DENALI_PHY_1199_DATA 0x00000000 +#define DENALI_PHY_1200_DATA 0x00000000 +#define DENALI_PHY_1201_DATA 0x00000108 +#define DENALI_PHY_1202_DATA 0x00000000 +#define DENALI_PHY_1203_DATA 0x00000000 +#define DENALI_PHY_1204_DATA 0x00000000 +#define DENALI_PHY_1205_DATA 0x00000001 +#define DENALI_PHY_1206_DATA 0x00000000 +#define DENALI_PHY_1207_DATA 0x00000000 +#define DENALI_PHY_1208_DATA 0x00000000 +#define DENALI_PHY_1209_DATA 0x00000000 +#define DENALI_PHY_1210_DATA 0x00000000 +#define DENALI_PHY_1211_DATA 0x00000000 +#define DENALI_PHY_1212_DATA 0x00020100 +#define DENALI_PHY_1213_DATA 0x00000000 +#define DENALI_PHY_1214_DATA 0x00000000 -- To view, visit https://review.coreboot.org/28594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716 Gerrit-Change-Number: 28594 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

1 0

Change in coreboot[master]: arch/riscv: provide a monotonic timer
by build bot (Jenkins) (Code Review) 13 Sep '18

13 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27434 ) Change subject: arch/riscv: provide a monotonic timer ...................................................................... Patch Set 12: (2 comments) https://review.coreboot.org/#/c/27434/12/src/arch/riscv/include/arch/io.h File src/arch/riscv/include/arch/io.h: https://review.coreboot.org/#/c/27434/12/src/arch/riscv/include/arch/io.h@34 PS12, Line 34: static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr) line over 80 characters https://review.coreboot.org/#/c/27434/12/src/arch/riscv/include/arch/io.h@54 PS12, Line 54: static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value) line over 80 characters -- To view, visit https://review.coreboot.org/27434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Gerrit-Change-Number: 27434 Gerrit-PatchSet: 12 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Sep 2018 16:13:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/sifive/fu540: create ram_resource with actual memory size
by Philipp Hug (Code Review) 13 Sep '18

13 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28592 to look at the new patch set (#3). Change subject: soc/sifive/fu540: create ram_resource with actual memory size ...................................................................... soc/sifive/fu540: create ram_resource with actual memory size Change-Id: If6af6f679e24e56c79b995de0970d4e6f455e40a Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- A src/soc/sifive/fu540/soc.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/28592/3 -- To view, visit https://review.coreboot.org/28592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If6af6f679e24e56c79b995de0970d4e6f455e40a Gerrit-Change-Number: 28592 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/sifive/fu540: create ram_resource with actual memory size
by Philipp Hug (Code Review) 13 Sep '18

13 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28592 to look at the new patch set (#2). Change subject: soc/sifive/fu540: create ram_resource with actual memory size ...................................................................... soc/sifive/fu540: create ram_resource with actual memory size Change-Id: If6af6f679e24e56c79b995de0970d4e6f455e40a Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- A src/soc/sifive/fu540/soc.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/28592/2 -- To view, visit https://review.coreboot.org/28592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If6af6f679e24e56c79b995de0970d4e6f455e40a Gerrit-Change-Number: 28592 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payloads/external: Add yabits payload
by Martin Roth (Code Review) 13 Sep '18

13 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28590 ) Change subject: payloads/external: Add yabits payload ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/28590/4/payloads/external/Yabits/Makefile File payloads/external/Yabits/Makefile: https://review.coreboot.org/#/c/28590/4/payloads/external/Yabits/Makefile@61 PS4, Line 61: XGCC=$(XGCCPATH) Need to do this another way. -- To view, visit https://review.coreboot.org/28590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899 Gerrit-Change-Number: 28590 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Sep 2018 16:00:22 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/intel/fsp2_0: Hook up IntelFSP repo
by Patrick Georgi (Code Review) 13 Sep '18

13 Sep '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/28593 Change subject: drivers/intel/fsp2_0: Hook up IntelFSP repo ...................................................................... drivers/intel/fsp2_0: Hook up IntelFSP repo With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. So far, this commit covers Apollolake, but as you can see there, it's easy enough to support the other SoCs. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc D src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h 7 files changed, 34 insertions(+), 2,489 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/28593/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4c4dfb2..f904fa9 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -66,21 +66,32 @@ string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_USE_REPO + bool "Use the IntelFSP based binaries" + depends on ADD_FSP_BINARIES + help + When selecting this option, the SoC's Makefile must generate the + fsp-? binaries from the fsp.FD and also set FSP_HEADER_PATH and + FSP_FD_PATH correctly. + config FSP_T_FILE string "Intel FSP-T (temp ram init) binary path and filename" depends on FSP_CAR + default "$(obj)/Fsp_T.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-M binary for this platform. config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES + default "$(obj)/Fsp_M.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-M binary for this platform. config FSP_S_FILE string "Intel FSP-S (silicon init) binary path and filename" depends on ADD_FSP_BINARIES + default "$(obj)/Fsp_S.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-S binary for this platform. diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d5709ad..0094253 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -64,4 +64,17 @@ $(CONFIG_FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) $(CONFIG_FSP_S_CBFS)-type := fsp +ifeq ($(CONFIG_FSP_USE_REPO),y) +$(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) + 3rdparty/fsp/tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" + +$(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd + true + +$(obj)/Fsp_T.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd + true + +CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) +endif + endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4dcecf5..b2903d1 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -201,6 +201,16 @@ help The base address (in CAR) where verstage should be linked +config FSP_HEADER_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/ApolloLakeFspBinPkg/FspBin/Fsp.fd" + config FSP_M_ADDR hex default 0xfef40000 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 08a5037..b224318 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -102,8 +102,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include ifeq ($(CONFIG_SOC_INTEL_GLK),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk -else -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake endif # Since FSP-M runs in CAR we need to relocate it to a specific address diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h deleted file mode 100644 index 5f4cb66..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h deleted file mode 100644 index 3cfbd71..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h +++ /dev/null @@ -1,850 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - - -#define MAX_CHANNELS_NUM 4 -#define MAX_DIMMS_NUM 1 - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DRR3 is 18 bytes - but DRR4 is 20 bytes as per JEDEC Spec, so - reserving 20 bytes **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT8 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT16 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Debug Serial Port Base address - Debug serial port base address. This option will be used only when the 'Serial Port - Debug Device' option is set to 'External Device'. 0x00000000(Default). -**/ - UINT32 SerialDebugPortAddress; - -/** Offset 0x0044 - Debug Serial Port Type - 16550 compatible debug serial port resource type. NONE means no serial port support. - 0x02:MMIO(Default). - 0:NONE, 1:I/O, 2:MMIO -**/ - UINT8 SerialDebugPortType; - -/** Offset 0x0045 - Serial Port Debug Device - Select active serial port device for debug. For SOC UART devices,'Debug Serial Port - Base' options will be ignored. 0x02:SOC UART2(Default). - 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device -**/ - UINT8 SerialDebugPortDevice; - -/** Offset 0x0046 - Debug Serial Port Stride Size - Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). - 0:1, 2:4 -**/ - UINT8 SerialDebugPortStrideSize; - -/** Offset 0x0047 - Memory Fast Boot - Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0048 - Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video - Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 Igd; - -/** Offset 0x0049 - DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal - Graphics Device. 0x02:64 MB(Default). - 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 - MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, - 0x0F:480 MB, 0x10:512 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x004A - Aperture Size - Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), - 0x2:256 MB, 0x3:512 MB. - 0x1:128 MB, 0x2:256 MB, 0x3:512 MB -**/ - UINT8 IgdApertureSize; - -/** Offset 0x004B - GTT Size - Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 - MB(Default). - 0x1:2 MB, 0x2:4 MB, 0x3:8 MB -**/ - UINT8 GttSize; - -/** Offset 0x004C - Primary Display - Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), - 0x2:IGD, 0x3:PCI - 0x0:AUTO, 0x2:IGD, 0x3:PCI -**/ - UINT8 PrimaryVideoAdaptor; - -/** Offset 0x004D - Package - NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default); - 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored - (DDR3L); Refer to the IAFW spec for specific details about each CA mapping. - 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank - 1 Mirrored (DDR3L) -**/ - UINT8 Package; - -/** Offset 0x004E - Profile - Profile list. 0x19(Default). - 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, - 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, - 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, - 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, - 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, - 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, - 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, - 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, - 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, - 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, - 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, - 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 -**/ - UINT8 Profile; - -/** Offset 0x004F - MemoryDown - Memory Down. 0x0(Default). - 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 -**/ - UINT8 MemoryDown; - -/** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB. - 0x1:1KB, 0x2:2KB -**/ - UINT8 DDR3LPageSize; - -/** Offset 0x0051 - DDR3LASR - NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment - in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported. - 0x0:Not Supported, 0x1:Supported -**/ - UINT8 DDR3LASR; - -/** Offset 0x0052 - ScramblerSupport - Scrambler Support - Enable or disable the memory scrambler. Data scrambling is - provided as a means to increase signal integrity/reduce RFI generated by the DRAM - interface. This is achieved by randomizing seed that encodes/decodes memory data - so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support, - 01: Enable Scrambler Support - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x0053 - InterleavedMode - This field is ignored if one of the PnP channel configurations is used. If the memory - configuration is different, then the field is used directly to populate. 0x00:Disable(Default), - 0x02:Enable. - 0x0:Disable, 0x2:Enable -**/ - UINT8 InterleavedMode; - -/** Offset 0x0054 - ChannelHashMask - ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be - modified. These inputs are not used for configurations where an optimized ChannelHashMask - has been provided by the PnP validation teams. 0x00(Default). -**/ - UINT16 ChannelHashMask; - -/** Offset 0x0056 - SliceHashMask - ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be - modified. These inputs are not used for configurations where an optimized ChannelHashMask - has been provided by the PnP validation teams. 0x00(Default). -**/ - UINT16 SliceHashMask; - -/** Offset 0x0058 - ChannelsSlicesEnable - ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration - is calculated internally based on the enabled channel configuration. 0x00:Disable(Default), - 0x01:Enable. - $EN_DIS -**/ - UINT8 ChannelsSlicesEnable; - -/** Offset 0x0059 - MinRefRate2xEnable - Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), - 0x01:Enable. - $EN_DIS -**/ - UINT8 MinRefRate2xEnable; - -/** Offset 0x005A - DualRankSupportEnable - Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 DualRankSupportEnable; - -/** Offset 0x005B - RmtMode - Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled). - 0x0:Disabled, 0x3:Enabled -**/ - UINT8 RmtMode; - -/** Offset 0x005C - MemorySizeLimit - Memory Size Limit: This value is used to restrict the total amount of memory and - the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, - 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) -**/ - UINT16 MemorySizeLimit; - -/** Offset 0x005E - LowMemoryMaxValue - Low Memory Max Value: This value is used to restrict the amount of memory below - 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 - = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). -**/ - UINT16 LowMemoryMaxValue; - -/** Offset 0x0060 - HighMemoryMaxValue - High Memory Max Value: This value is used to restrict the amount of memory above - 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, - 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). -**/ - UINT16 HighMemoryMaxValue; - -/** Offset 0x0062 - DisableFastBoot - 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled; - Full re-train of memory on every boot. - $EN_DIS -**/ - UINT8 DisableFastBoot; - -/** Offset 0x0063 - DIMM0SPDAddress - DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). -**/ - UINT8 DIMM0SPDAddress; - -/** Offset 0x0064 - DIMM1SPDAddress - DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). -**/ - UINT8 DIMM1SPDAddress; - -/** Offset 0x0065 - Ch0_RankEnable - NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. - NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank - 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be - set to 1 to enable use of this rank. -**/ - UINT8 Ch0_RankEnable; - -/** Offset 0x0066 - Ch0_DeviceWidth - NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel - (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 - and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 - device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch0_DeviceWidth; - -/** Offset 0x0067 - Ch0_DramDensity - NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device - density per rank (per Chip Select). The simplest way of identifying the density - per rank is to divide the total SoC memory channel density by the number of ranks. - For DDR3L: Must specify the DRAM device density per DRAM device. For example, an - 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, - a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch0_DramDensity; - -/** Offset 0x0068 - Ch0_Option - BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: - 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] - Bank Address Hashing Enable. See Address Mapping section for full description: - 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 - CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board - designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 - CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register - specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) -**/ - UINT8 Ch0_Option; - -/** Offset 0x0069 - Ch0_OdtConfig - [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination - during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 - OHMS or so roughly. Purpose: Save power on these technologies which burn power - directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. - a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, - 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The - customer needs to choose this based on their actual board strapping (how they tie - the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW - ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, - which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS - signals). Purpose: To improve signal integrity and provide a much more optimized - CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), - 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: - 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 - Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care -**/ - UINT8 Ch0_OdtConfig; - -/** Offset 0x006A - Ch0_TristateClk1 - Not used -**/ - UINT8 Ch0_TristateClk1; - -/** Offset 0x006B - Ch0_Mode2N - DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command - mode that provides more setup and hold time for DRAM commands on the DRAM command - bus. This is useful for platforms with unusual CMD bus routing or marginal signal - integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and - Control training), 1 - Force 2N Mode - 0x0:Auto, 0x1:Force 2N CMD Timing Mode -**/ - UINT8 Ch0_Mode2N; - -/** Offset 0x006C - Ch0_OdtLevels - Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to - SoC, 1 - ODT held high -**/ - UINT8 Ch0_OdtLevels; - -/** Offset 0x006D - Ch1_RankEnable - NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. - NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank - 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be - set to 1 to enable use of this rank. -**/ - UINT8 Ch1_RankEnable; - -/** Offset 0x006E - Ch1_DeviceWidth - NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel - (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 - and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 - device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch1_DeviceWidth; - -/** Offset 0x006F - Ch1_DramDensity - NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device - density per rank (per Chip Select). The simplest way of identifying the density - per rank is to divide the total SoC memory channel density by the number of ranks. - For DDR3L: Must specify the DRAM device density per DRAM device. For example, an - 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, - a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch1_DramDensity; - -/** Offset 0x0070 - Ch1_Option - BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: - 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] - Bank Address Hashing Enable. See Address Mapping section for full description: - 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 - CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board - designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 - CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register - specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) -**/ - UINT8 Ch1_Option; - -/** Offset 0x0071 - Ch1_OdtConfig - BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; - LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, - 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: - X = Don't Care -**/ - UINT8 Ch1_OdtConfig; - -/** Offset 0x0072 - Ch1_TristateClk1 - Not used -**/ - UINT8 Ch1_TristateClk1; - -/** Offset 0x0073 - Ch1_Mode2N - DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command - mode that provides more setup and hold time for DRAM commands on the DRAM command - bus. This is useful for platforms with unusual CMD bus routing or marginal signal - integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and - Control training), 1 - Force 2N Mode - 0x0:Auto, 0x1:Force 2N CMD Timing Mode -**/ - UINT8 Ch1_Mode2N; - -/** Offset 0x0074 - Ch1_OdtLevels - DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW - (default), 1 - ODT_AB_HIGH_HIGH -**/ - UINT8 Ch1_OdtLevels; - -/** Offset 0x0075 - Ch2_RankEnable - NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. - NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank - 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be - set to 1 to enable use of this rank. -**/ - UINT8 Ch2_RankEnable; - -/** Offset 0x0076 - Ch2_DeviceWidth - NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel - (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 - and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 - device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch2_DeviceWidth; - -/** Offset 0x0077 - Ch2_DramDensity - NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device - density per rank (per Chip Select). The simplest way of identifying the density - per rank is to divide the total SoC memory channel density by the number of ranks. - For DDR3L: Must specify the DRAM device density per DRAM device. For example, an - 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, - a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch2_DramDensity; - -/** Offset 0x0078 - Ch2_Option - BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: - 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] - Bank Address Hashing Enable. See Address Mapping section for full description: - 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 - CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board - designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 - CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register - specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) -**/ - UINT8 Ch2_Option; - -/** Offset 0x0079 - Ch2_OdtConfig - BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; - LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, - 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: - X = Don't Care -**/ - UINT8 Ch2_OdtConfig; - -/** Offset 0x007A - Ch2_TristateClk1 - Not used -**/ - UINT8 Ch2_TristateClk1; - -/** Offset 0x007B - Ch2_Mode2N - DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command - mode that provides more setup and hold time for DRAM commands on the DRAM command - bus. This is useful for platforms with unusual CMD bus routing or marginal signal - integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and - Control training), 1 - Force 2N Mode - 0x0:Auto, 0x1:Force 2N CMD Timing Mode -**/ - UINT8 Ch2_Mode2N; - -/** Offset 0x007C - Ch2_OdtLevels - DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW - (default), 1 - ODT_AB_HIGH_HIGH -**/ - UINT8 Ch2_OdtLevels; - -/** Offset 0x007D - Ch3_RankEnable - NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. - NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank - 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be - set to 1 to enable use of this rank. -**/ - UINT8 Ch3_RankEnable; - -/** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel - (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 - and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 - device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch3_DeviceWidth; - -/** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device - density per rank (per Chip Select). The simplest way of identifying the density - per rank is to divide the total SoC memory channel density by the number of ranks. - For DDR3L: Must specify the DRAM device density per DRAM device. For example, an - 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, - a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch3_DramDensity; - -/** Offset 0x0080 - Ch3_Option - BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: - 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] - Bank Address Hashing Enable. See Address Mapping section for full description: - 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 - CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board - designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 - CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register - specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) -**/ - UINT8 Ch3_Option; - -/** Offset 0x0081 - Ch3_OdtConfig - BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; - LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, - 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: - X = Don't Care -**/ - UINT8 Ch3_OdtConfig; - -/** Offset 0x0082 - Ch3_TristateClk1 - Not used -**/ - UINT8 Ch3_TristateClk1; - -/** Offset 0x0083 - Ch3_Mode2N - DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command - mode that provides more setup and hold time for DRAM commands on the DRAM command - bus. This is useful for platforms with unusual CMD bus routing or marginal signal - integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and - Control training), 1 - Force 2N Mode - 0x0:Auto, 0x1:Force 2N CMD Timing Mode -**/ - UINT8 Ch3_Mode2N; - -/** Offset 0x0084 - Ch3_OdtLevels - DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW - (default), 1 - ODT_AB_HIGH_HIGH -**/ - UINT8 Ch3_OdtLevels; - -/** Offset 0x0085 - RmtCheckRun - Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM - MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK -**/ - UINT8 RmtCheckRun; - -/** Offset 0x0086 - RmtMarginCheckScaleHighThreshold - Percentage used to determine the margin tolerances over the failing margin. -**/ - UINT16 RmtMarginCheckScaleHighThreshold; - -/** Offset 0x0088 - Ch0_Bit_swizzling - Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently - asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes - on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes - need to follow the DQ byte lane they correspond too. So for example if you have - DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair. - Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that - specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion - can arrise from the fact that the indexes to the array do not necessarily map 1:1 - to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value - of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates - a 2 physical channels need to be stuffed and operated together. Are the CHx_A and - CHx_B physical channels operated in tandem or completely separate? If separate, - why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting - up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you - have 2 channels in order to power gate one PHY, those two channel populated must - be on one PHY instance. So yes all channels are independent of each other, but - there are some restrictions on how they need to be populated. Q: How is it that - an LPDDR4 device is identified as having a x16 width when all 32-bits are used - at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4 - DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel - the CS of the two devices in the same die are connected together to make a single - rank of one x32 channel (SDP). The second die in the DDP package makes the second rank. -**/ - UINT8 Ch0_Bit_swizzling[32]; - -/** Offset 0x00A8 - Ch1_Bit_swizzling - Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch1_Bit_swizzling[32]; - -/** Offset 0x00C8 - Ch2_Bit_swizzling - Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch2_Bit_swizzling[32]; - -/** Offset 0x00E8 - Ch3_Bit_swizzling - Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch3_Bit_swizzling[32]; - -/** Offset 0x0108 - MsgLevelMask - 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages. -**/ - UINT32 MsgLevelMask; - -/** Offset 0x010C -**/ - UINT8 UnusedUpdSpace0[4]; - -/** Offset 0x0110 - PreMem GPIO Pin Number for each table - Number of Pins in each PreMem GPIO Table. 0(Default). -**/ - UINT8 PreMemGpioTablePinNum[4]; - -/** Offset 0x0114 - PreMem GPIO Table Pointer - Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). -**/ - UINT32 PreMemGpioTablePtr; - -/** Offset 0x0118 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 - Number of Entries in PreMem GPIO Table. 0(Default). -**/ - UINT8 PreMemGpioTableEntryNum; - -/** Offset 0x0119 - Enhance the port 8xh decoding - Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnhancePort8xhDecoding; - -/** Offset 0x011A - SPD Data Write - Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 SpdWriteEnable; - -/** Offset 0x011B - MRC Training Data Saving - Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 MrcDataSaving; - -/** Offset 0x011C - OEM File Loading Address - Determine the memory base address to load a specified file from CSE file system - after memory is available. -**/ - UINT32 OemLoadingBase; - -/** Offset 0x0120 - OEM File Name to Load - Specify a file name to load from CSE file system after memory is available. Empty - indicates no file needs to be loaded. -**/ - UINT8 OemFileName[16]; - -/** Offset 0x0130 -**/ - VOID* MrcBootDataPtr; - -/** Offset 0x0134 - eMMC Trace Length - Select eMMC trace length to load OEM file from when loading OEM file name is specified. - 0x0:Long(Default), 0x1:Short. - 0x0:Long, 0x1:Short -**/ - UINT8 eMMCTraceLen; - -/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB - Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of - CSE. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 SkipCseRbp; - -/** Offset 0x0136 - Npk Enable - Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default). - 0:Disable, 1:Enable, 2:Debugger, 3:Auto -**/ - UINT8 NpkEn; - -/** Offset 0x0137 - FW Trace Enable - Enable/Disable FW Trace. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 FwTraceEn; - -/** Offset 0x0138 - FW Trace Destination - FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, - 4-NPK_TRACE_TO_PTI(Default). -**/ - UINT8 FwTraceDestination; - -/** Offset 0x0139 - NPK Recovery Dump - Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 RecoverDump; - -/** Offset 0x013A - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - UINT8 Msc0Wrap; - -/** Offset 0x013B - Memory Region 1 Buffer WrapAround - Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - UINT8 Msc1Wrap; - -/** Offset 0x013C - Memory Region 0 Buffer Size - Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, - 6-512MB, 7-1GB. -**/ - UINT32 Msc0Size; - -/** Offset 0x0140 - Memory Region 1 Buffer Size - Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, - 6-512MB, 7-1GB. -**/ - UINT32 Msc1Size; - -/** Offset 0x0144 - PTI Mode - PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. -**/ - UINT8 PtiMode; - -/** Offset 0x0145 - PTI Training - PTI Training. 0-off(Default), 1-6=1-6. -**/ - UINT8 PtiTraining; - -/** Offset 0x0146 - PTI Speed - PTI Speed. 0-full, 1-half, 2-quarter(Default). -**/ - UINT8 PtiSpeed; - -/** Offset 0x0147 - Punit Message Level - Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. -**/ - UINT8 PunitMlvl; - -/** Offset 0x0148 - PMC Message Level - PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. -**/ - UINT8 PmcMlvl; - -/** Offset 0x0149 - SW Trace Enable - Enable/Disable SW Trace. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SwTraceEn; - -/** Offset 0x014A - Periodic Retraining Disable - Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic - Retraining for debug purposes. Periodic Retraining should be enabled in production. - Periodic retraining allows the platform to operate reliably over a larger voltage - and temperature range. This field has no effect for DDR3L and LPDDR3 memory type - configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic - Retraining (debug configuration only) - 0x0:Enabled, 0x1:Disabled -**/ - UINT8 PeriodicRetrainingDisable; - -/** Offset 0x014B - Enable Reset System - Enable FSP to trigger reset instead of returning reset request. 0x00: Return the - Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside - FSP instead of returning from the API. - 0x0:Disabled, 0x1:Eabled -**/ - UINT8 EnableResetSystem; - -/** Offset 0x014C - Enable HECI2 in S3 resume path - Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ; - 0x01: Enable HECI2 in S3 resume path.(Default) - 0x0:Disabled, 0x1:Eabled -**/ - UINT8 EnableS3Heci2; - -/** Offset 0x014D -**/ - UINT8 UnusedUpdSpace1[3]; - -/** Offset 0x0150 -**/ - VOID* VariableNvsBufferPtr; - -/** Offset 0x0154 -**/ - UINT8 ReservedFspmUpd[12]; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0160 -**/ - UINT8 UnusedUpdSpace2[158]; - -/** Offset 0x01FE -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h deleted file mode 100644 index 82a224d..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h +++ /dev/null @@ -1,1589 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - ActiveProcessorCores - Number of active cores. 0:Disable(Default), 1:Enable. -**/ - UINT8 ActiveProcessorCores; - -/** Offset 0x0021 - Disable Core1 - Disable/Enable Core1. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore1; - -/** Offset 0x0022 - Disable Core2 - Disable/Enable Core2. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore2; - -/** Offset 0x0023 - Disable Core3 - Disable/Enable Core3. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore3; - -/** Offset 0x0024 - VMX Enable - Enable or Disable VMX. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x0025 - Memory region allocation for Processor Trace - Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to - 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) -**/ - UINT8 ProcTraceMemSize; - -/** Offset 0x0026 - Enable Processor Trace - Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 ProcTraceEnable; - -/** Offset 0x0027 - Eist - Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0028 - Boot PState - Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. -**/ - UINT8 BootPState; - -/** Offset 0x0029 - CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableCx; - -/** Offset 0x002A - Enhanced C-states - Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x002B - Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x002C - Max Pkg Cstate - Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, - 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x002D - C-State auto-demotion - C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 - Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion - to C1 and C3. -**/ - UINT8 CStateAutoDemotion; - -/** Offset 0x002E - C-State un-demotion - C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, - 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. -**/ - UINT8 CStateUnDemotion; - -/** Offset 0x002F - Max Core C-State - Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). -**/ - UINT8 MaxCoreCState; - -/** Offset 0x0030 - Package C-State Demotion - Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0031 - Package C-State Un-demotion - Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0032 - Turbo Mode - Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0033 - SC HDA Verb Table Entry Number - Number of Entries in Verb Table. 0(Default). -**/ - UINT8 HdaVerbTableEntryNum; - -/** Offset 0x0034 - SC HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. 0x00000000(Default). -**/ - UINT32 HdaVerbTablePtr; - -/** Offset 0x0038 - Enable/Disable P2SB device hidden. - Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 P2sbUnhide; - -/** Offset 0x0039 - IPU Enable/Disable - Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IpuEn; - -/** Offset 0x003A - IMGU ACPI mode selection - 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. - 0:Disable, 1:IGFX Child device, 2:ACPI device -**/ - UINT8 IpuAcpiMode; - -/** Offset 0x003B - Enable ForceWake - Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 ForceWake; - -/** Offset 0x003C - GttMmAdr - GttMmAdr structure for initialization. 0xBF000000(Default). -**/ - UINT32 GttMmAdr; - -/** Offset 0x0040 - GmAdr - GmAdr structure for initialization. 0xA0000000(Default). -**/ - UINT32 GmAdr; - -/** Offset 0x0044 - Enable PavpLock - Enable/disable PavpLock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PavpLock; - -/** Offset 0x0045 - Enable GraphicsFreqModify - Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsFreqModify; - -/** Offset 0x0046 - Enable GraphicsFreqReq - Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsFreqReq; - -/** Offset 0x0047 - Enable GraphicsVideoFreq - Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsVideoFreq; - -/** Offset 0x0048 - Enable PmLock - Enable/disable PmLock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PmLock; - -/** Offset 0x0049 - Enable DopClockGating - Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DopClockGating; - -/** Offset 0x004A - Enable UnsolicitedAttackOverride - Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UnsolicitedAttackOverride; - -/** Offset 0x004B - Enable WOPCMSupport - Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 WOPCMSupport; - -/** Offset 0x004C - Enable WOPCMSize - Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 WOPCMSize; - -/** Offset 0x004D - Enable PowerGating - Enable/disable PowerGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PowerGating; - -/** Offset 0x004E - Enable UnitLevelClockGating - Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UnitLevelClockGating; - -/** Offset 0x004F - Enable FastBoot - Enable/disable FastBoot. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 FastBoot; - -/** Offset 0x0050 - Enable DynSR - Enable/disable DynSR. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DynSR; - -/** Offset 0x0051 - Enable SaIpuEnable - Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x0052 - GT PM Support - Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x0053 - RC6(Render Standby) - Enable/Disable render standby support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableRenderStandby; - -/** Offset 0x0054 - BMP Logo Data Size - BMP logo data buffer size. 0x00000000(Default). -**/ - UINT32 LogoSize; - -/** Offset 0x0058 - BMP Logo Data Pointer - BMP logo data pointer to a BMP format buffer. 0x00000000(Default). -**/ - UINT32 LogoPtr; - -/** Offset 0x005C - Graphics Configuration Data Pointer - Graphics configuration data used for initialization. 0x00000000(Default). -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x0060 - PAVP Enable - Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0061 - PAVP PR3 - Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PavpPr3; - -/** Offset 0x0062 - CdClock Frequency selection - 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). - 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz -**/ - UINT8 CdClock; - -/** Offset 0x0063 - Enable/Disable PeiGraphicsPeimInit - Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0064 - Write Protection Support - Enable/disable Write Protection. 0:Disable, 1:Enable(Default). -**/ - UINT8 WriteProtectionEnable[5]; - -/** Offset 0x0069 - Read Protection Support - Enable/disable Read Protection. 0:Disable, 1:Enable(Default). -**/ - UINT8 ReadProtectionEnable[5]; - -/** Offset 0x006E - Protected Range Limitation - The address of the upper limit of protection, 0x0FFFh(Default). -**/ - UINT16 ProtectedRangeLimit[5]; - -/** Offset 0x0078 - Protected Range Base - The base address of the upper limit of protection. 0x0000(Default). -**/ - UINT16 ProtectedRangeBase[5]; - -/** Offset 0x0082 - Enable SC Gaussian Mixture Models - Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Gmm; - -/** Offset 0x0083 - GMM Clock Gating - PGCB Clock Trunk - Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingPgcbClkTrunk; - -/** Offset 0x0084 - GMM Clock Gating - Sideband - Enable/disable Sideband. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSb; - -/** Offset 0x0085 - GMM Clock Gating - Sideband - Enable/disable Sideband. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSbClkTrunk; - -/** Offset 0x0086 - GMM Clock Gating - Sideband Clock Partition - Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSbClkPartition; - -/** Offset 0x0087 - GMM Clock Gating - Core - Enable/disable Core. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingCore; - -/** Offset 0x0088 - GMM Clock Gating - DMA - Enable/disable DMA. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingDma; - -/** Offset 0x0089 - GMM Clock Gating - Register Access - Enable/disable Register Access. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingRegAccess; - -/** Offset 0x008A - GMM Clock Gating - Host - Enable/disable Host. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingHost; - -/** Offset 0x008B - GMM Clock Gating - Partition - Enable/disable Partition. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingPartition; - -/** Offset 0x008C - Clock Gating - Trunk - Enable/disable Trunk. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingTrunk; - -/** Offset 0x008D - HD Audio Support - Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 HdaEnable; - -/** Offset 0x008E - HD Audio DSP Support - Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DspEnable; - -/** Offset 0x008F - Azalia wake-on-ring - Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 Pme; - -/** Offset 0x0090 - HD-Audio I/O Buffer Ownership - Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default) - 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and - I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers -**/ - UINT8 HdAudioIoBufferOwnership; - -/** Offset 0x0091 - HD-Audio I/O Buffer Voltage - HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. - 0: 3.3V, 1: 1.8V -**/ - UINT8 HdAudioIoBufferVoltage; - -/** Offset 0x0092 - HD-Audio Virtual Channel Type - HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. - 0: VC0, 1: VC1 -**/ - UINT8 HdAudioVcType; - -/** Offset 0x0093 - HD-Audio Link Frequency - HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, - 4:96MHz, 5:Invalid. - 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid -**/ - UINT8 HdAudioLinkFrequency; - -/** Offset 0x0094 - HD-Audio iDisp-Link Frequency - HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, - 4:96MHz, 5:Invalid. - 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid -**/ - UINT8 HdAudioIDispLinkFrequency; - -/** Offset 0x0095 - HD-Audio iDisp-Link T-Mode - HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. - 0: 2T, 1: 1T -**/ - UINT8 HdAudioIDispLinkTmode; - -/** Offset 0x0096 - HD-Audio Disp DMIC - HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. - 0: Disable, 1: 2ch array, 2: 4ch array -**/ - UINT8 DspEndpointDmic; - -/** Offset 0x0097 - HD-Audio Bluetooth - Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DspEndpointBluetooth; - -/** Offset 0x0098 - HD-Audio I2S SHK - Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DspEndpointI2sSkp; - -/** Offset 0x0099 - HD-Audio I2S HP - Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DspEndpointI2sHp; - -/** Offset 0x009A - HD-Audio Controller Power Gating - Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. - $EN_DIS -**/ - UINT8 AudioCtlPwrGate; - -/** Offset 0x009B - HD-Audio ADSP Power Gating - Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. - $EN_DIS -**/ - UINT8 AudioDspPwrGate; - -/** Offset 0x009C - HD-Audio CSME Memory Transfers - Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. - 0: VC0, 1: VC2 -**/ - UINT8 Mmt; - -/** Offset 0x009D - HD-Audio Host Memory Transfers - Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. - 0: VC0, 1: VC2 -**/ - UINT8 Hmt; - -/** Offset 0x009E - HD-Audio Power Gating - Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HDAudioPwrGate; - -/** Offset 0x009F - HD-Audio Clock Gatingn - Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HDAudioClkGate; - -/** Offset 0x00A0 - Bitmask of DSP Feature - Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation -**/ - UINT32 DspFeatureMask; - -/** Offset 0x00A4 - Bitmask of supported DSP Post-Processing Modules - Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation -**/ - UINT32 DspPpModuleMask; - -/** Offset 0x00A8 - HD-Audio BIOS Configuration Lock Down - Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. - This option is deprecated - $EN_DIS -**/ - UINT8 BiosCfgLockDown; - -/** Offset 0x00A9 - Enable High Precision Timer - Enable/Disable Hpet. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Hpet; - -/** Offset 0x00AA - Hpet Valid BDF Value - Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HpetBdfValid; - -/** Offset 0x00AB - Bus Number of Hpet - Completer ID of Bus Number of Hpet. Default = 0xFA(Default). -**/ - UINT8 HpetBusNumber; - -/** Offset 0x00AC - Device Number of Hpet - Completer ID of Device Number of Hpet. 0x1F(Default). -**/ - UINT8 HpetDeviceNumber; - -/** Offset 0x00AD - Function Number of Hpet - Completer ID of Function Number of Hpet. 0x00(Default). -**/ - UINT8 HpetFunctionNumber; - -/** Offset 0x00AE - IoApic Valid BDF Value - Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 IoApicBdfValid; - -/** Offset 0x00AF - Bus Number of IoApic - Completer ID of Bus Number of IoApic. 0xFA(Default). -**/ - UINT8 IoApicBusNumber; - -/** Offset 0x00B0 - Device Number of IoApic - Completer ID of Device Number of IoApic. 0x0F(Default). -**/ - UINT8 IoApicDeviceNumber; - -/** Offset 0x00B1 - Function Number of IoApic - Completer ID of Function Number of IoApic. 0x00(Default). -**/ - UINT8 IoApicFunctionNumber; - -/** Offset 0x00B2 - IOAPIC Entry 24-119 - Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IoApicEntry24_119; - -/** Offset 0x00B3 - IO APIC ID - This member determines IOAPIC ID. 0x01(Default). -**/ - UINT8 IoApicId; - -/** Offset 0x00B4 - IoApic Range - Define address bits 19:12 for the IOxAPIC range. 0x00(Default). -**/ - UINT8 IoApicRangeSelect; - -/** Offset 0x00B5 - ISH Controller - Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IshEnable; - -/** Offset 0x00B6 - BIOS Interface Lock Down - Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control - Register. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 BiosInterface; - -/** Offset 0x00B7 - Bios LockDown Enable - Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 BiosLock; - -/** Offset 0x00B8 - SPI EISS Status - Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SpiEiss; - -/** Offset 0x00B9 - BiosLock SWSMI Number - This member describes the SwSmi value for Bios Lock. 0xA9(Default). -**/ - UINT8 BiosLockSwSmiNumber; - -/** Offset 0x00BA - LPSS IOSF PMCTL S0ix Enable - Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 LPSS_S0ixEnable; - -/** Offset 0x00BB -**/ - UINT8 UnusedUpdSpace0[1]; - -/** Offset 0x00BC - LPSS I2C Clock Gating Configuration - Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 I2cClkGateCfg[8]; - -/** Offset 0x00C4 - PSS HSUART Clock Gating Configuration - Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 HsuartClkGateCfg[4]; - -/** Offset 0x00C8 - LPSS SPI Clock Gating Configuration - Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 SpiClkGateCfg[3]; - -/** Offset 0x00CB - I2C Device 0 - Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c0Enable; - -/** Offset 0x00CC - I2C Device 1 - Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c1Enable; - -/** Offset 0x00CD - I2C Device 2 - Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c2Enable; - -/** Offset 0x00CE - I2C Device 3 - Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c3Enable; - -/** Offset 0x00CF - I2C Device 4 - Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c4Enable; - -/** Offset 0x00D0 - I2C Device 5 - Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c5Enable; - -/** Offset 0x00D1 - I2C Device 6 - Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c6Enable; - -/** Offset 0x00D2 - I2C Device 7 - Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c7Enable; - -/** Offset 0x00D3 - UART Device 0 - Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart0Enable; - -/** Offset 0x00D4 - UART Device 1 - Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart1Enable; - -/** Offset 0x00D5 - UART Device 2 - Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart2Enable; - -/** Offset 0x00D6 - UART Device 3 - Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart3Enable; - -/** Offset 0x00D7 - SPI UART Device 0 - Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi0Enable; - -/** Offset 0x00D8 - SPI UART Device 1 - Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi1Enable; - -/** Offset 0x00D9 - SPI UART Device 2 - Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi2Enable; - -/** Offset 0x00DA - OS Debug Feature - Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. - $EN_DIS -**/ - UINT8 OsDbgEnable; - -/** Offset 0x00DB - DCI Feature - Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. - $EN_DIS -**/ - UINT8 DciEn; - -/** Offset 0x00DC - UART Debug Base Address - UART Debug Base Address. 0x00000000(Default). -**/ - UINT32 Uart2KernelDebugBaseAddress; - -/** Offset 0x00E0 - Enable PCIE Clock Gating - Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). - 0:Enable, 1:Disable -**/ - UINT8 PcieClockGatingDisabled; - -/** Offset 0x00E1 - Enable PCIE Root Port 8xh Decode - Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PcieRootPort8xhDecode; - -/** Offset 0x00E2 - PCIE 8xh Decode Port Index - PCIE 8xh Decode Port Index. 0x00(Default). -**/ - UINT8 Pcie8xhDecodePortIndex; - -/** Offset 0x00E3 - Enable PCIE Root Port Peer Memory Write - Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PcieRootPortPeerMemoryWriteEnable; - -/** Offset 0x00E4 - PCIE SWSMI Number - This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). -**/ - UINT8 PcieAspmSwSmiNumber; - -/** Offset 0x00E5 -**/ - UINT8 UnusedUpdSpace1[1]; - -/** Offset 0x00E6 - PCI Express Root Port - Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRootPortEn[6]; - -/** Offset 0x00EC - Hide PCIE Root Port Configuration Space - Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpHide[6]; - -/** Offset 0x00F2 - PCIE Root Port Slot Implement - Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpSlotImplemented[6]; - -/** Offset 0x00F8 - Hot Plug - PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpHotPlug[6]; - -/** Offset 0x00FE - PCIE PM SCI - Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpPmSci[6]; - -/** Offset 0x0104 - PCIE Root Port Extended Sync - Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpExtSync[6]; - -/** Offset 0x010A - Transmitter Half Swing - Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpTransmitterHalfSwing[6]; - -/** Offset 0x0110 - ACS - Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpAcsEnabled[6]; - -/** Offset 0x0116 - Clock Request Support - Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpClkReqSupported[6]; - -/** Offset 0x011C - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, - 0x01, 0x02, 0x03. -**/ - UINT8 PcieRpClkReqNumber[6]; - -/** Offset 0x0122 - CLKREQ# Detection - Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. -**/ - UINT8 PcieRpClkReqDetect[6]; - -/** Offset 0x0128 - Advanced Error Reporting - Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. -**/ - UINT8 AdvancedErrorReporting[6]; - -/** Offset 0x012E - PME Interrupt - Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. -**/ - UINT8 PmeInterrupt[6]; - -/** Offset 0x0134 - URR - PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 UnsupportedRequestReport[6]; - -/** Offset 0x013A - FER - PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 FatalErrorReport[6]; - -/** Offset 0x0140 - NFER - PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 NoFatalErrorReport[6]; - -/** Offset 0x0146 - CER - PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 CorrectableErrorReport[6]; - -/** Offset 0x014C - SEFE - Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnFatalError[6]; - -/** Offset 0x0152 - SENFE - Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnNonFatalError[6]; - -/** Offset 0x0158 - SECE - Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnCorrectableError[6]; - -/** Offset 0x015E - PCIe Speed - Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. -**/ - UINT8 PcieRpSpeed[6]; - -/** Offset 0x0164 - Physical Slot Number - Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. -**/ - UINT8 PhysicalSlotNumber[6]; - -/** Offset 0x016A - CTO - Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpCompletionTimeout[6]; - -/** Offset 0x0170 - PTM Support - Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. -**/ - UINT8 PtmEnable[6]; - -/** Offset 0x0176 - ASPM - PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, - 4:Auto(Default). -**/ - UINT8 PcieRpAspm[6]; - -/** Offset 0x017C - L1 Substates - PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). -**/ - UINT8 PcieRpL1Substates[6]; - -/** Offset 0x0182 - PCH PCIe LTR - PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpLtrEnable[6]; - -/** Offset 0x0188 - PCIE LTR Lock - PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpLtrConfigLock[6]; - -/** Offset 0x018E - PME_B0_S5 Disable bit - PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PmeB0S5Dis; - -/** Offset 0x018F - PCI Clock Run - This member describes whether or not the PCI ClockRun feature of SC should be enabled. - 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PciClockRun; - -/** Offset 0x0190 - Enable/Disable Timer 8254 Clock Setting - Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 Timer8254ClkSetting; - -/** Offset 0x0191 - Chipset SATA - Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports - the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableSata; - -/** Offset 0x0192 - SATA Mode Selection - Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0193 - Aggressive LPM Support - Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0194 - SATA Power Optimization - Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0195 - eSATA Speed Limit - Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 eSATASpeedLimit; - -/** Offset 0x0196 - SATA Speed Limit - SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). - 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) -**/ - UINT8 SpeedLimit; - -/** Offset 0x0197 -**/ - UINT8 UnusedUpdSpace2[1]; - -/** Offset 0x0198 - SATA Port - Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). -**/ - UINT8 SataPortsEnable[2]; - -/** Offset 0x019A - SATA Port DevSlp - Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsDevSlp[2]; - -/** Offset 0x019C - SATA Port HotPlug - Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsHotPlug[2]; - -/** Offset 0x019E - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\n - Note:Requires hardware support. 0:Disable, 1:Enable(Default). -**/ - UINT8 SataPortsInterlockSw[2]; - -/** Offset 0x01A0 - External SATA Ports - Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsExternal[2]; - -/** Offset 0x01A2 - Spin Up Device - Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsSpinUp[2]; - -/** Offset 0x01A4 - SATA Solid State - Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard - Disk Drive(Default), 1:Solid State Drive. -**/ - UINT8 SataPortsSolidStateDrive[2]; - -/** Offset 0x01A6 - DITO Configuration - Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsEnableDitoConfig[2]; - -/** Offset 0x01A8 - DM Value - DM Value. 0:Minimum, 0x0F:Maximum(Default). -**/ - UINT8 SataPortsDmVal[2]; - -/** Offset 0x01AA -**/ - UINT8 UnusedUpdSpace3[2]; - -/** Offset 0x01AC - DITO Value - DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). -**/ - UINT16 SataPortsDitoVal[2]; - -/** Offset 0x01B0 - Subsystem Vendor ID - Subsystem Vendor ID. 0x8086(Default). -**/ - UINT16 SubSystemVendorId; - -/** Offset 0x01B2 - Subsystem ID - Subsystem ID. 0x7270(Default). -**/ - UINT16 SubSystemId; - -/** Offset 0x01B4 - CRIDSettings - PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. -**/ - UINT8 CRIDSettings; - -/** Offset 0x01B5 - ResetSelect - ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. -**/ - UINT8 ResetSelect; - -/** Offset 0x01B6 - SD Card Support (D27:F0) - Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SdcardEnabled; - -/** Offset 0x01B7 - SeMMC Support (D28:F0) - Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 eMMCEnabled; - -/** Offset 0x01B8 - eMMC Max Speed - Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. - 0:HS400, 1: HS200, 2:DDR50 -**/ - UINT8 eMMCHostMaxSpeed; - -/** Offset 0x01B9 - UFS Support (D29:F0) - Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 UfsEnabled; - -/** Offset 0x01BA - SDIO Support (D30:F0) - Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SdioEnabled; - -/** Offset 0x01BB - GPP Lock Feature - Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GppLock; - -/** Offset 0x01BC - Serial IRQ - Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SirqEnable; - -/** Offset 0x01BD - Serial IRQ Mode - Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. - $EN_DIS -**/ - UINT8 SirqMode; - -/** Offset 0x01BE - Start Frame Pulse Width - Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. - 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk -**/ - UINT8 StartFramePulse; - -/** Offset 0x01BF - Enable SMBus - Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x01C0 - SMBus ARP Support - Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ArpEnable; - -/** Offset 0x01C1 -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x01C2 - SMBus Table Elements - The number of elements in the Reserved SMBus Address Table. 0x0080(Default). -**/ - UINT16 NumRsvdSmbusAddresses; - -/** Offset 0x01C4 - Reserved SMBus Address Table - Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). -**/ - UINT8 RsvdSmbusAddressTable[128]; - -/** Offset 0x0244 - XHCI Disable Compliance Mode - Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance - Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. - $EN_DIS -**/ - UINT8 DisableComplianceMode; - -/** Offset 0x0245 - USB Per-Port Control - Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UsbPerPortCtl; - -/** Offset 0x0246 - xHCI Mode - Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Usb30Mode; - -/** Offset 0x0247 -**/ - UINT8 UnusedUpdSpace5[1]; - -/** Offset 0x0248 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. 0x01(Default). -**/ - UINT8 PortUsb20Enable[8]; - -/** Offset 0x0250 - USB20 Over Current Pin - Over Current Pin number of USB 2.0 Port. 0x00(Default). -**/ - UINT8 PortUs20bOverCurrentPin[8]; - -/** Offset 0x0258 - XDCI Support - Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. - 0:Disable, 1:PCI_Mode, 2:ACPI_mode -**/ - UINT8 UsbOtg; - -/** Offset 0x0259 - Enable XHCI HSIC Support - Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HsicSupportEnable; - -/** Offset 0x025A - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. 0x01(Default). -**/ - UINT8 PortUsb30Enable[6]; - -/** Offset 0x0260 - USB20 Over Current Pin - Over Current Pin number of USB 3.0 Port. 0x01(Default). -**/ - UINT8 PortUs30bOverCurrentPin[6]; - -/** Offset 0x0266 - Enable XHCI SSIC Support - Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for - port1. 0x00(Default). -**/ - UINT8 SsicPortEnable[2]; - -/** Offset 0x0268 - SSIC Dlane PowerGating - Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT16 DlanePwrGating; - -/** Offset 0x026A - VT-d - Enable/Disable VT-d. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 VtdEnable; - -/** Offset 0x026B - SMI Lock bit - Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, - 1:Enable(Default). - $EN_DIS -**/ - UINT8 LockDownGlobalSmi; - -/** Offset 0x026C - HDAudio Delay Timer - The delay timer after Azalia reset. 0x012C(Default). -**/ - UINT16 ResetWaitTimer; - -/** Offset 0x026E - RTC Lock Bits - Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 RtcLock; - -/** Offset 0x026F - SATA Test Mode Selection - Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0270 - XHCI SSIC RATE - Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. -**/ - UINT8 SsicRate[2]; - -/** Offset 0x0272 - SMBus Dynamic Power Gating - Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT16 DynamicPowerGating; - -/** Offset 0x0274 - Max Snoop Latency - Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). -**/ - UINT16 PcieRpLtrMaxSnoopLatency[6]; - -/** Offset 0x0280 - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \n - Disabled:Disable override.\n - Manual:Manually enter override values.\n - Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[6]; - -/** Offset 0x0286 -**/ - UINT8 UnusedUpdSpace6[2]; - -/** Offset 0x0288 - Snoop Latency Value - LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[6]; - -/** Offset 0x0294 - Snoop Latency Multiplier - LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, - 4:1048576ns, 5:33554432ns. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[6]; - -/** Offset 0x029A - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize(Default), 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x029B - DCI Auto Detect - Enable/disable DCI AUTO mode. Enabled(Default). - $EN_DIS -**/ - UINT8 DciAutoDetect; - -/** Offset 0x029C - Max Non-Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). -**/ - UINT16 PcieRpLtrMaxNonSnoopLatency[6]; - -/** Offset 0x02A8 - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \n - Disabled:Disable override.\n - Manual:Manually enter override values.\n - Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[6]; - -/** Offset 0x02AE - Halt and Lock TCO Timer - Halt and Lock the TCO Timer (Watchdog). - 0:No, 1:Yes (default) -**/ - UINT8 TcoTimerHaltLock; - -/** Offset 0x02AF - Power Button Override Period - specifies how long will PMC wait before initiating a global reset. 000b-4s(default), - 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) - 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s -**/ - UINT8 PwrBtnOverridePeriod; - -/** Offset 0x02B0 - Non Snoop Latency Value - LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[6]; - -/** Offset 0x02BC - Non Snoop Latency Multiplier - LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), - 3:32768ns, 4:1048576ns, 5:33554432ns. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6]; - -/** Offset 0x02C2 - PCIE Root Port Slot Power Limit Scale - Specifies scale used for slot power limit value. 0x00(Default). -**/ - UINT8 PcieRpSlotPowerLimitScale[6]; - -/** Offset 0x02C8 - PCIE Root Port Slot Power Limit Value - Specifies upper limit on power supplie by slot. 0x00(Default). -**/ - UINT8 PcieRpSlotPowerLimitValue[6]; - -/** Offset 0x02CE - Power Button Native Mode Disable - Disable power button native mode, when 1, this will result in the PMC logic constantly - seeing the power button as de-asserted. 0 (default)) - $EN_DIS -**/ - UINT8 DisableNativePowerButton; - -/** Offset 0x02CF - Power Button Debounce Mode - Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) - $EN_DIS -**/ - UINT8 PowerButterDebounceMode; - -/** Offset 0x02D0 - SDIO_TX_CMD_DLL_CNTL - SDIO_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 SdioTxCmdCntl; - -/** Offset 0x02D4 - SDIO_TX_DATA_DLL_CNTL1 - SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). -**/ - UINT32 SdioTxDataCntl1; - -/** Offset 0x02D8 - SDIO_TX_DATA_DLL_CNTL2 - SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). -**/ - UINT32 SdioTxDataCntl2; - -/** Offset 0x02DC - SDIO_RX_CMD_DATA_DLL_CNTL1 - SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). -**/ - UINT32 SdioRxCmdDataCntl1; - -/** Offset 0x02E0 - SDIO_RX_CMD_DATA_DLL_CNTL2 - SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). -**/ - UINT32 SdioRxCmdDataCntl2; - -/** Offset 0x02E4 - SDCARD_TX_CMD_DLL_CNTL - SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 SdcardTxCmdCntl; - -/** Offset 0x02E8 - SDCARD_TX_DATA_DLL_CNTL1 - SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). -**/ - UINT32 SdcardTxDataCntl1; - -/** Offset 0x02EC - SDCARD_TX_DATA_DLL_CNTL2 - SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). -**/ - UINT32 SdcardTxDataCntl2; - -/** Offset 0x02F0 - SDCARD_RX_CMD_DATA_DLL_CNTL1 - SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). -**/ - UINT32 SdcardRxCmdDataCntl1; - -/** Offset 0x02F4 - SDCARD_RX_STROBE_DLL_CNTL - SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). -**/ - UINT32 SdcardRxStrobeCntl; - -/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL2 - SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). -**/ - UINT32 SdcardRxCmdDataCntl2; - -/** Offset 0x02FC - EMMC_TX_CMD_DLL_CNTL - EMMC_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 EmmcTxCmdCntl; - -/** Offset 0x0300 - EMMC_TX_DATA_DLL_CNTL1 - EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). -**/ - UINT32 EmmcTxDataCntl1; - -/** Offset 0x0304 - EMMC_TX_DATA_DLL_CNTL2 - EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). -**/ - UINT32 EmmcTxDataCntl2; - -/** Offset 0x0308 - EMMC_RX_CMD_DATA_DLL_CNTL1 - EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). -**/ - UINT32 EmmcRxCmdDataCntl1; - -/** Offset 0x030C - EMMC_RX_STROBE_DLL_CNTL - EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). -**/ - UINT32 EmmcRxStrobeCntl; - -/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL2 - EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). -**/ - UINT32 EmmcRxCmdDataCntl2; - -/** Offset 0x0314 - EMMC_MASTER_DLL_CNTL - EMMC_MASTER_DLL_CNTL. 0x001(Default). -**/ - UINT32 EmmcMasterSwCntl; - -/** Offset 0x0318 - PCIe Selectable De-emphasis - When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis - for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpSelectableDeemphasis[6]; - -/** Offset 0x031E - Monitor Mwait Enable - Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux - based OS, this should be Disabled. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x031F - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 HdAudioDspUaaCompliance; - -/** Offset 0x0320 - IRQ Interrupt Polarity Control - Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low -**/ - UINT32 IPC[4]; - -/** Offset 0x0330 - Disable ModPHY dynamic power gate - Disable ModPHY dynamic power gate for the specific SATA port. -**/ - UINT8 SataPortsDisableDynamicPg[2]; - -/** Offset 0x0332 - Init CPU during S3 resume - 0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume. - $EN_DIS -**/ - UINT8 InitS3Cpu; - -/** Offset 0x0333 - Skip P-unit Initialization - When this is skipped, boot loader must initialize P-unit before SilicionInit API. - 0: Initialize(Default), 1: Skip - $EN_DIS -**/ - UINT8 SkipPunitInit; - -/** Offset 0x0334 -**/ - UINT8 UnusedUpdSpace7[4]; - -/** Offset 0x0338 - PerPort Half Bit Pre-emphasis - PerPort Half Bit Pre-emphasis. Value of register USB2_PER_PORT_PPX [14] -**/ - UINT8 PortUsb20PerPortTxPeHalf[8]; - -/** Offset 0x0340 - PerPort HS Pre-emphasis Bias - PerPort HS Pre-emphasis Bias. Value of register USB2_PER_PORT_PPX [13:11] -**/ - UINT8 PortUsb20PerPortPeTxiSet[8]; - -/** Offset 0x0348 - PerPort HS Transmitter Bias - PerPort HS Transmitter Bias. Value of register USB2_PER_PORT_PPX [10:8] -**/ - UINT8 PortUsb20PerPortTxiSet[8]; - -/** Offset 0x0350 - Select the skew direction for HS transition - Select the skew direction for HS transition. Value of register USB2_PER_PORT_2_PPX [25] -**/ - UINT8 PortUsb20HsSkewSel[8]; - -/** Offset 0x0358 - Per Port HS Transmitter Emphasis - Per Port HS Transmitter Emphasis. Value of register USB2_PER_PORT_2_PPX [24:23] -**/ - UINT8 PortUsb20IUsbTxEmphasisEn[8]; - -/** Offset 0x0360 - PerPort HS Receiver Bias - PerPort HS Receiver Bias. Value of register USB2_PER_PORT_2_PPX [19:17] -**/ - UINT8 PortUsb20PerPortRXISet[8]; - -/** Offset 0x0368 - Delay/skew's strength control for HS driver - Delay/skew's strength control for HS driver. Value of register USB2_PER_PORT_2_PPX [1:0] -**/ - UINT8 PortUsb20HsNpreDrvSel[8]; - -/** Offset 0x0370 -**/ - UINT8 ReservedFspsUpd[16]; -} FSP_S_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x0380 -**/ - UINT8 UnusedUpdSpace8[46]; - -/** Offset 0x03AE -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif -- To view, visit https://review.coreboot.org/28593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Gerrit-Change-Number: 28593 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: soc/sifive/fu540: create ram_resource with actual memory size
by build bot (Jenkins) (Code Review) 13 Sep '18

13 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28592 ) Change subject: soc/sifive/fu540: create ram_resource with actual memory size ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/28592/1/src/soc/sifive/fu540/soc.c File src/soc/sifive/fu540/soc.c: https://review.coreboot.org/#/c/28592/1/src/soc/sifive/fu540/soc.c@18 PS1, Line 18: ram_resource(dev, 0, (uintptr_t)_dram/KiB, code indent should use tabs where possible https://review.coreboot.org/#/c/28592/1/src/soc/sifive/fu540/soc.c@18 PS1, Line 18: ram_resource(dev, 0, (uintptr_t)_dram/KiB, please, no spaces at the start of a line https://review.coreboot.org/#/c/28592/1/src/soc/sifive/fu540/soc.c@19 PS1, Line 19: (sdram_max_addressable_mb() - fb_size)*KiB - code indent should use tabs where possible https://review.coreboot.org/#/c/28592/1/src/soc/sifive/fu540/soc.c@19 PS1, Line 19: (sdram_max_addressable_mb() - fb_size)*KiB - please, no spaces at the start of a line https://review.coreboot.org/#/c/28592/1/src/soc/sifive/fu540/soc.c@20 PS1, Line 20: (uintptr_t)_dram/KiB); code indent should use tabs where possible https://review.coreboot.org/#/c/28592/1/src/soc/sifive/fu540/soc.c@20 PS1, Line 20: (uintptr_t)_dram/KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If6af6f679e24e56c79b995de0970d4e6f455e40a Gerrit-Change-Number: 28592 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Sep 2018 14:15:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018