coreboot-gerrit September 2018

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by build bot (Jenkins) (Code Review) 14 Sep '18

14 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28606 ) Change subject: WIP: Port libpayload to riscv ...................................................................... Patch Set 1: (14 comments) https://review.coreboot.org/#/c/28606/1/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/28606/1/payloads/external/LinuxBoot/Makefil… PS1, Line 78: echo "BEFOR DEF" 'BEFOR' may be misspelled - perhaps 'BEFORE'? https://review.coreboot.org/#/c/28606/1/payloads/libpayload/arch/riscv/core… File payloads/libpayload/arch/riscv/coreboot.c: https://review.coreboot.org/#/c/28606/1/payloads/libpayload/arch/riscv/core… PS1, Line 42: switch(rec->tag) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/asm.h: https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 24: name: labels should not be indented https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 27: .size name, .-name space required before that '-' (ctx:VxV) https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/barrier.h: https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 57: #define mb() memory barrier without comment https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 58: #define rmb() memory barrier without comment https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 59: #define wmb() memory barrier without comment https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/cache.h: https://review.coreboot.org/#/c/28606/1/payloads/libpayload/include/riscv/a… PS1, Line 81: } void function return statements are not generally useful -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: comment Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 14:41:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28606 Change subject: WIP: Port libpayload to riscv ...................................................................... WIP: Port libpayload to riscv Work-in-progress port of libpayload to RISC-V Do not merge yet Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/barrier.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h M payloads/linuxcheck/Makefile 21 files changed, 779 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28606/1 diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 8acb542..c359a57 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -37,6 +37,12 @@ help AARCH64 kernel and initramfs +config LINUXBOOT_RISCV + bool "riscv" + depends on ARCH_RISCV + help + RISCV64 kernel and initramfs + endchoice config LINUXBOOT_ARCH @@ -44,6 +50,7 @@ default "amd64" if LINUXBOOT_X86_64 default "386" if LINUXBOOT_X86 default "arm64" if LINUXBOOT_ARM64 + default "riscv" if LINUXBOOT_RISCV choice prompt "Kernel version" diff --git a/payloads/external/LinuxBoot/Kconfig.name b/payloads/external/LinuxBoot/Kconfig.name index 18438c7..c59a8bc 100644 --- a/payloads/external/LinuxBoot/Kconfig.name +++ b/payloads/external/LinuxBoot/Kconfig.name @@ -14,7 +14,7 @@ config PAYLOAD_LINUXBOOT bool "LinuxBoot" - depends on ARCH_X86 || ARCH_ARM64 + depends on ARCH_X86 || ARCH_ARM64 || ARCH_RISCV help Select this option if you want to build a coreboot image with a LinuxBoot payload. If you don't know what this is diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index c051389..71b3ab2 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -29,6 +29,9 @@ else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) LINUXBOOT_COMPILE?=$(XGCCPATH)/aarch64-linux- ARCH?=arm64 +else ifeq ($(CONFIG_LINUXBOOT_ARCH),riscv) +LINUXBOOT_COMPILE?=$(XGCCPATH)/riscv64-elf- +ARCH?=riscv endif OBJCOPY:=$(LINUXBOOT_COMPILE)objcopy @@ -36,10 +39,11 @@ all: payload toolchain: - if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \ - echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \ - exit 1; \ - fi + echo $(LINUXBOOT_COMPILE) + #if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \ + #echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \ + #exit 1; \ + #fi $(kernel_dir)/.config: echo " WWW Download Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)" @@ -59,15 +63,21 @@ cp x86_64/defconfig $(kernel_dir)/.config else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) cp arm64/defconfig $(kernel_dir)/.config +else ifeq ($(CONFIG_LINUXBOOT_ARCH),riscv) + cp riscv/defconfig $(kernel_dir)/.config endif ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64)) $(kernel_dir)/arch/x86/boot/bzImage: config toolchain else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) $(kernel_dir)/vmlinux: config toolchain +else ifeq ($(CONFIG_LINUXBOOT_ARCH),riscv) +$(kernel_dir)/vmlinux: config toolchain endif echo " MAKE Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)" + echo "BEFOR DEF" $(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH) + echo "AFTER DEF" $(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH) ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64)) @@ -86,6 +96,9 @@ $(project_dir)/kernel-image: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb $(PWD)/$(CONFIG_PAYLOAD_USERSPACE) cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir) mkimage -f $(project_dir)/kernel_fdt_lzma.its $@ +else ifeq ($(CONFIG_LINUXBOOT_ARCH),riscv) +$(project_dir)/kernel-image: $(kernel_dir)/vmlinux + $(OBJCOPY) -O binary $< $@ endif ifeq ($(CONFIG_LINUXBOOT_UROOT),y) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 3cd8ba6..178945b 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -119,6 +119,11 @@ help Support the MIPS architecture +config ARCH_RISCV + bool "RISCV" + help + Support the RISCV architecture + endchoice config MULTIBOOT @@ -148,12 +153,13 @@ default 0x04000000 if ARCH_ARM default 0x80100000 if ARCH_ARM64 default 0x00000000 if ARCH_MIPS + default 0x81000000 if ARCH_RISCV default 0x00100000 if ARCH_X86 help This is the base address for the payload. If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS, - 0x04000000 on ARM or 0x80100000 on ARM64. + 0x04000000 on ARM or 0x80100000 on ARM64 or 0x81000000 on RISCV. endmenu @@ -450,4 +456,5 @@ source "arch/arm/Kconfig" source "arch/arm64/Kconfig" source "arch/mips/Kconfig" +source "arch/riscv/Kconfig" source "arch/x86/Kconfig" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 1a0acf1..e01115e 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -96,6 +96,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips +ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 ARCH-y := $(ARCHDIR-y) @@ -105,6 +106,7 @@ ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_RISCV) := riscv ARCH-$(CONFIG_LP_ARCH_MIPS) := mips # Three cases where we don't need fully populated $(obj) lists: diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 7787762..f204722 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -34,6 +34,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips +ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 DESTDIR ?= install @@ -83,6 +84,9 @@ $(obj)/libpayload.a: $(foreach class,$(libraries),$$($(class)-objs)) printf " AR $(subst $(CURDIR)/,,$(@))\n" + echo $(ARCH-y) + echo $(AR) + echo $(AR_riscv) $(AR) rc $@ $^ $(obj)/%.a: $$(%-objs) diff --git a/payloads/libpayload/arch/riscv/Kconfig b/payloads/libpayload/arch/riscv/Kconfig new file mode 100644 index 0000000..b747256 --- /dev/null +++ b/payloads/libpayload/arch/riscv/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the libpayload project. +## +## Copyright (c) 2012 Google Inc. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +if ARCH_RISCV + +config ARCH_SPECIFIC_OPTIONS # dummy + def_bool y + select LITTLE_ENDIAN + +endif diff --git a/payloads/libpayload/arch/riscv/Makefile.inc b/payloads/libpayload/arch/riscv/Makefile.inc new file mode 100644 index 0000000..4c5c78b --- /dev/null +++ b/payloads/libpayload/arch/riscv/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the libpayload project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +head.o-y += head.S + +libc-y += main.c coreboot.c diff --git a/payloads/libpayload/arch/riscv/coreboot.c b/payloads/libpayload/arch/riscv/coreboot.c new file mode 100644 index 0000000..a25c51a --- /dev/null +++ b/payloads/libpayload/arch/riscv/coreboot.c @@ -0,0 +1,57 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> +#include <coreboot_tables.h> + +/* This pointer gets set in head.S and is passed in from coreboot. */ +void *cb_header_ptr; + +/* == Architecture specific == */ + +int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) +{ + switch(rec->tag) { + default: + return 0; + } + return 1; +} + +int get_coreboot_info(struct sysinfo_t *info) +{ + return cb_parse_header(cb_header_ptr, 1, info); +} + +void *get_cb_header_ptr(void) +{ + return cb_header_ptr; +} diff --git a/payloads/libpayload/arch/riscv/head.S b/payloads/libpayload/arch/riscv/head.S new file mode 100644 index 0000000..c7f793f --- /dev/null +++ b/payloads/libpayload/arch/riscv/head.S @@ -0,0 +1,60 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + +/* + * Our entry point + */ +ENTRY(_entry) + + /* Save off the location of the coreboot tables */ + // TODO + + /* Setup exception stack */ + // TODO + + /* Setup new stack */ + // TODO + csrr a0, mhartid + la t0, _stack + li t1, 0xDEADBEEF + sd t1, 0(t0) + add sp, t0, 0 + + /* Let's rock. */ + tail start_main + +ENDPROC(_entry) + +.align 4 +1: +.quad cb_header_ptr +2: +.quad _stack diff --git a/payloads/libpayload/arch/riscv/libpayload.ldscript b/payloads/libpayload/arch/riscv/libpayload.ldscript new file mode 100644 index 0000000..149c121 --- /dev/null +++ b/payloads/libpayload/arch/riscv/libpayload.ldscript @@ -0,0 +1,88 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv","elf64-littleriscv") +OUTPUT_ARCH(riscv) + +ENTRY(_entry) + +SECTIONS +{ + . = CONFIG_LP_BASE_ADDRESS; + + //. = ALIGN(16); + _start = .; + + .text : { + *(.text._entry) + *(.text) + *(.text.*) + } + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + .data : { + *(.data) + *(.data.*) + } + + _edata = .; + + .bss : { + *(.sbss) + *(.sbss.*) + *(.bss) + *(.bss.*) + *(COMMON) + + /* Stack and heap */ + + . = ALIGN(16); + _heap = .; + . += CONFIG_LP_HEAP_SIZE; + . = ALIGN(16); + _eheap = .; + + _estack = .; + . += CONFIG_LP_STACK_SIZE; + . = ALIGN(16); + _stack = .; + } + + _end = .; + + /DISCARD/ : { + *(.comment) + *(.note*) + } +} diff --git a/payloads/libpayload/arch/riscv/main.c b/payloads/libpayload/arch/riscv/main.c new file mode 100644 index 0000000..4c288ac --- /dev/null +++ b/payloads/libpayload/arch/riscv/main.c @@ -0,0 +1,71 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +unsigned int main_argc; /**< The argc value to pass to main() */ + +/** The argv value to pass to main() */ +char *main_argv[MAX_ARGC_COUNT]; + +/** + * This is our C entry function - set up the system + * and jump into the payload entry point. + */ +void start_main(void); +void start_main(void) +{ + extern int main(int argc, char **argv); + + /* Gather system information. */ + lib_get_sysinfo(); + +#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT) + console_init(); +#endif + + //exception_init(); TODO + + /* + * Any other system init that has to happen before the + * user gets control goes here. + */ + + /* + * Go to the entry point. + * In the future we may care about the return value. + */ + + (void) main(main_argc, (main_argc != 0) ? main_argv : NULL); + + /* + * Returning here will go to the _leave function to return + * us to the original context. + */ +} diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index b3ef342..2faf113 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -86,6 +86,12 @@ _ARCHEXTRA="" _ARCH=mips fi +if [ "$CONFIG_LP_ARCH_RISCV" = "y" ]; then + _ARCHINCDIR=$_INCDIR/riscv + _ARCHLIBDIR=$_LIBDIR/riscv + _ARCHEXTRA="" + _ARCH=riscv +fi if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHINCDIR=$_INCDIR/x86 _ARCHLIBDIR=$_LIBDIR/x86 diff --git a/payloads/libpayload/configs/defconfig-riscv b/payloads/libpayload/configs/defconfig-riscv new file mode 100644 index 0000000..2ce2bc5 --- /dev/null +++ b/payloads/libpayload/configs/defconfig-riscv @@ -0,0 +1,3 @@ +CONFIG_LP_ARCH_RISCV=y +CONFIG_LP_TINYCURSES=n +CONFIG_LP_USB=n diff --git a/payloads/libpayload/include/riscv/arch/asm.h b/payloads/libpayload/include/riscv/arch/asm.h new file mode 100644 index 0000000..de44482 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/asm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + */ + +#ifndef __ARM64_ASM_H +#define __ARM64_ASM_H + +# define ARM64(x...) x +# define W(instr) instr + +#define ALIGN .align 2 + +#define ENDPROC(name) \ + .type name, %function; \ + END(name) + +#define ENTRY(name) \ + .section .text.name, "ax", %progbits; \ + .global name; \ + ALIGN; \ + name: + +#define END(name) \ + .size name, .-name + +#endif /* __ARM64_ASM_H */ diff --git a/payloads/libpayload/include/riscv/arch/barrier.h b/payloads/libpayload/include/riscv/arch/barrier.h new file mode 100644 index 0000000..0b55df6 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/barrier.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __ARCH_BARRIER_H_ +#define __ARCH_BARRIER_H__ + +#include <arch/cache.h> + +/* + * Description of different memory barriers introduced: + * + * Memory barrier(mb) - Guarantees that all memory accesses specified before the + * barrier will happen before all memory accesses specified after the barrier + * + * Read memory barrier (rmb) - Guarantees that all read memory accesses + * specified before the barrier will happen before all read memory accesses + * specified after the barrier + * + * Write memory barrier (wmb) - Guarantees that all write memory accesses + * specified before the barrier will happen before all write memory accesses + * specified after the barrier + */ + +#define mb() +#define rmb() +#define wmb() + +#endif /* __ARCH_BARRIER_H__ */ diff --git a/payloads/libpayload/include/riscv/arch/cache.h b/payloads/libpayload/include/riscv/arch/cache.h new file mode 100644 index 0000000..820bee9 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/cache.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.h: Cache maintenance API for RISCV + */ + +#ifndef RISCV_CACHE_H +#define RISCV_CACHE_H + +#include <stddef.h> +#include <stdint.h> + +/* + * Cache maintenance API + */ + +/* dcache clean and invalidate all (on current level given by CCSELR) */ +void dcache_clean_invalidate_all(void); + +/* dcache clean by virtual address to PoC */ +void dcache_clean_by_mva(void const *addr, size_t len); + +/* dcache clean and invalidate by virtual address to PoC */ +void dcache_clean_invalidate_by_mva(void const *addr, size_t len); + +/* dcache invalidate by virtual address to PoC */ +void dcache_invalidate_by_mva(void const *addr, size_t len); + +void dcache_clean_all(void); + +/* dcache invalidate all (on current level given by CCSELR) */ +void dcache_invalidate_all(void); + +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + +/* perform all icache/dcache maintenance needed after loading new code */ +void cache_sync_instructions(void); + +/* Ensure that loaded program segment is synced back from cache to PoC */ +void arch_program_segment_loaded(void const *addr, size_t len); + +/* tlb invalidate all */ +void tlb_invalidate_all(void); + +/* Invalidate all of the instruction cache for PE to PoU. */ +static inline void icache_invalidate_all(void) +{ + return; +} + +#endif /* RISCV_CACHE_H */ diff --git a/payloads/libpayload/include/riscv/arch/io.h b/payloads/libpayload/include/riscv/arch/io.h new file mode 100644 index 0000000..8413b61 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/io.h @@ -0,0 +1,106 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_IO_H +#define _ARCH_IO_H + +#include <stdint.h> +#include <arch/cache.h> +//#include <arch/lib_helpers.h> + +/* + * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 + * instead for future development. + * + * TODO: make the existing code use read8/16/32 and write8/16/32 then remove + * readb/w/l and writeb/w/l. + */ + +static inline uint8_t readb(volatile const void *_a) +{ + return *(volatile const uint8_t *)_a; +} + +static inline uint16_t readw(volatile const void *_a) +{ + return *(volatile const uint16_t *)_a; +} + +static inline uint32_t readl(volatile const void *_a) +{ + return *(volatile const uint32_t *)_a; +} + +static inline void writeb(uint8_t _v, volatile void *_a) +{ + *(volatile uint8_t *)_a = _v; +} + +static inline void writew(uint16_t _v, volatile void *_a) +{ + *(volatile uint16_t *)_a = _v; +} + +static inline void writel(uint32_t _v, volatile void *_a) +{ + *(volatile uint32_t *)_a = _v; +} + +static inline uint8_t read8(const void *addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline uint16_t read16(const void *addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline uint32_t read32(const void *addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void write8(void *addr, uint8_t val) +{ + *(volatile uint8_t *)addr = val; +} + +static inline void write16(void *addr, uint16_t val) +{ + *(volatile uint16_t *)addr = val; +} + +static inline void write32(void *addr, uint32_t val) +{ + *(volatile uint32_t *)addr = val; +} + +#endif diff --git a/payloads/libpayload/include/riscv/arch/types.h b/payloads/libpayload/include/riscv/arch/types.h new file mode 100644 index 0000000..1bd815b --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/types.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_TYPES_H +#define _ARCH_TYPES_H + +typedef unsigned char uint8_t; +typedef unsigned char u8; +typedef signed char int8_t; +typedef signed char s8; + +typedef unsigned short uint16_t; +typedef unsigned short u16; +typedef signed short int16_t; +typedef signed short s16; + +typedef unsigned int uint32_t; +typedef unsigned int u32; +typedef signed int int32_t; +typedef signed int s32; + +typedef unsigned long long uint64_t; +typedef unsigned long long u64; +typedef signed long long int64_t; +typedef signed long long s64; + +typedef long time_t; +typedef long suseconds_t; + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#endif diff --git a/payloads/libpayload/include/riscv/arch/virtual.h b/payloads/libpayload/include/riscv/arch/virtual.h new file mode 100644 index 0000000..328c3aa --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/virtual.h @@ -0,0 +1,41 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_VIRTUAL_H +#define _ARCH_VIRTUAL_H + +extern unsigned long virtual_offset; + +#define virt_to_phys(virt) ((unsigned long) (virt) + virtual_offset) +#define phys_to_virt(phys) ((void *) ((unsigned long) (phys) - virtual_offset)) + +#define virt_to_bus(addr) virt_to_phys(addr) +#define bus_to_virt(addr) phys_to_virt(addr) + +#endif diff --git a/payloads/linuxcheck/Makefile b/payloads/linuxcheck/Makefile index b967369..3299397 100644 --- a/payloads/linuxcheck/Makefile +++ b/payloads/linuxcheck/Makefile @@ -6,18 +6,23 @@ CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib ifeq ($(CONFIG_ARCH_X86),y) TARGETARCH = i386 +DEFCONFIG = defconfig +endif +ifeq ($(CONFIG_ARCH_RISCV),y) +TARGETARCH = riscv +DEFCONFIG = defconfig-riscv endif all: linuxcheck.elf $(LIBPAYLOAD_DIR): - $(MAKE) -C ../libpayload $(LPOPTS) defconfig + $(MAKE) -C ../libpayload $(LPOPTS) $(DEFCONFIG) $(MAKE) -C ../libpayload $(LPOPTS) $(MAKE) -C ../libpayload $(LPOPTS) install ifneq ($(strip $(wildcard libpayload)),) include $(XCOMPILE) -LPGCC = CC="$(GCC_CC_x86_32)" "$(LIBPAYLOAD_DIR)/bin/lpgcc" +LPGCC = CC="$(GCC_CC_riscv)" "$(LIBPAYLOAD_DIR)/bin/lpgcc" %.elf: %.c Makefile $(LPGCC) $(CFLAGS) -o $*.elf $*.c $(TARGETARCH).c else -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: newchange Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Enable common block PMC
by Philipp Deppenwiese (Code Review) 14 Sep '18

14 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/25426 ) Change subject: soc/intel/denverton_ns: Enable common block PMC ...................................................................... soc/intel/denverton_ns: Enable common block PMC Mainly update headers to build. Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove function configuring the global reset through PMC base. On denverton the global reset lock is not in PMC base but in the PCI registers so this code cannot be shared. Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/25426 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-by: Evandro Luiz Hauenstein <kingsumos(a)gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/skylake/Kconfig 11 files changed, 38 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Lijian Zhao: Looks good to me, but someone else must approve Evandro Luiz Hauenstein: Looks good to me, but someone else must approve diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4dcecf5..fbc81ce 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -61,6 +61,7 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE select PMC_INVALID_READ_AFTER_WRITE + select PMC_GLOBAL_RESET_ENABLE_LOCK select REG_SCRIPT select RTC select SMM_TSEG diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 3392728..256cf1b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -53,6 +53,7 @@ select SMM_TSEG select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT + select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 46f134e..2f08408 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -37,3 +37,11 @@ help Enable this for PMC devices where a read back of ACPI BAR and IO access bit does not return the previously written value. + +config PMC_GLOBAL_RESET_ENABLE_LOCK + bool + help + Enable this for PMC devices where the reset configuration + and lock register is located under PMC BASE at offset ETR. + Note that the reset register is still at 0xCF9 this only + controls the enable and lock feature. diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 339e674..52bfaec 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -419,6 +419,7 @@ return ps->prev_sleep_state; } +#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK) /* * If possible, lock 0xcf9. Once the register is locked, it can't be changed. * This lock is reset on cold boot, hard reset, soft reset and Sx. @@ -451,6 +452,7 @@ reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; write32((void *)etr, reg); } +#endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK int vboot_platform_is_resuming(void) { diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 4517065..e22b8ee 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -46,6 +46,8 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_PMC + select ACPI_INTEL_HARDWARE_SLEEP_VALUES # select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 07278c5..6a947ff 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -130,7 +130,7 @@ fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe0_blk = pmbase + GPE0_STS(GPE_STD); fadt->gpe1_blk = 0; /* Control Registers - Length */ diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 29b231f..a7548d4 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -29,6 +29,7 @@ /* Southbridge internal device IO BARs (Set to match FSP settings) */ #define DEFAULT_PMBASE 0x1800 #define DEFAULT_ACPI_BASE DEFAULT_PMBASE +#define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400 /* Southbridge internal device MEM BARs (Set to match FSP settings) */ diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 2dc8781..32d8a76 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -20,10 +20,9 @@ #include <arch/io.h> #include <soc/pmc.h> +#include <arch/acpi.h> -#define SLEEP_STATE_S0 0 -#define SLEEP_STATE_S3 3 -#define SLEEP_STATE_S5 5 +#define GPE_MAX 127 struct chipset_power_state { uint16_t pm1_sts; @@ -31,8 +30,8 @@ uint32_t pm1_cnt; uint16_t tco1_sts; uint16_t tco2_sts; - uint32_t gpe0_sts[4]; - uint32_t gpe0_en[4]; + uint32_t gpe0_sts[GPE0_REG_MAX]; + uint32_t gpe0_en[GPE0_REG_MAX]; uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; uint32_t gblrst_cause[2]; diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index edb5c55..4db3981 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -120,7 +120,10 @@ #define GPE_CTRL 0x40 #define SWGPE_CTRL (1 << 17) #define PM2_CNT 0x50 -#define GPE0_STS 0x80 +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x80 + (x * 4)) +#define GPE_STD 0 #define GPIO31_STS (1 << 31) #define GPIO30_STS (1 << 30) #define GPIO29_STS (1 << 29) @@ -166,7 +169,7 @@ #define IE_SCI_STS (1 << 3) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x90 +#define GPE0_EN(x) (0x90 + (x * 4)) #define GPIO31_EN (1 << 31) #define GPIO30_EN (1 << 30) #define GPIO29_EN (1 << 29) @@ -236,6 +239,12 @@ #define TCO2_CNT 0x0a #define TCO_TMR 0x12 +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x10 +#define GPIO_GPE_CFG 0x120 +#define GPE0_DWX_MASK 0x7 +#define GPE0_DW_SHIFT(x) (4 + 4*(x)) + /* I/O ports */ #define RST_CNT 0xcf9 #define FULL_RST (1 << 3) diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 78903bb..ccf0d95 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -189,17 +189,17 @@ void enable_gpe(uint32_t mask) { uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN)); + uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); gpe0_en |= mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN)); + outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); } void disable_gpe(uint32_t mask) { uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN)); + uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); gpe0_en &= ~mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN)); + outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); } void disable_all_gpe(void) { disable_gpe(~0); } @@ -207,8 +207,8 @@ static uint32_t reset_gpe_status(void) { uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS)); - outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS)); + uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); + outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); return gpe_sts; } diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9a5aae4..614c251 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -51,6 +51,7 @@ select SA_ENABLE_DPR select SMM_TSEG select SMP + select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK -- To view, visit https://review.coreboot.org/25426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Gerrit-Change-Number: 25426 Gerrit-PatchSet: 6 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Evandro Luiz Hauenstein <kingsumos(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com>

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Change in coreboot[master]: soc/intel/denverton_ns: Enable common block PMC
by Philipp Deppenwiese (Code Review) 14 Sep '18

14 Sep '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/25426 ) Change subject: soc/intel/denverton_ns: Enable common block PMC ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/25426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Gerrit-Change-Number: 25426 Gerrit-PatchSet: 5 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Evandro Luiz Hauenstein <kingsumos(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Fri, 14 Sep 2018 14:10:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree
by Angel Pons (Code Review) 14 Sep '18

14 Sep '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28595 ) Change subject: mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28595/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28595/1//COMMIT_MSG@7 PS1, Line 7: buildin built-in -- To view, visit https://review.coreboot.org/28595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca Gerrit-Change-Number: 28595 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 14:04:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: arch/riscv: Only execute on hart 0 for now
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28605 Change subject: arch/riscv: Only execute on hart 0 for now ...................................................................... arch/riscv: Only execute on hart 0 for now Only execute coreboot on hart 0 until synchronisation between hart's is ready. Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/bootblock.S 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28605/1 diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 81a4455..95e1923 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -24,6 +24,12 @@ .global _estack .globl _start _start: + csrr a0, mhartid + li a3, 0 + beq a0, a3, _hart_zero +_hart_loop: + j _hart_loop +_hart_zero: # The boot ROM may pass the following arguments to coreboot: # a0: the value of mhartid -- To view, visit https://review.coreboot.org/28605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658 Gerrit-Change-Number: 28605 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: soc/sifive/fu540: Initialize SDRAM
by build bot (Jenkins) (Code Review) 14 Sep '18

14 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28604 ) Change subject: soc/sifive/fu540: Initialize SDRAM ...................................................................... Patch Set 1: (161 comments) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h File src/soc/sifive/fu540/ux00ddr.h: https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@39 PS1, Line 39: static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) { line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@39 PS1, Line 39: static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@40 PS1, Line 40: unsigned int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41 PS1, Line 41: for (i=1152;i<=1214;i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41 PS1, Line 41: for (i=1152;i<=1214;i++) { suspect code indent for conditional statements (2, 4) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41 PS1, Line 41: for (i=1152;i<=1214;i++) { spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41 PS1, Line 41: for (i=1152;i<=1214;i++) { space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41 PS1, Line 41: for (i=1152;i<=1214;i++) { spaces required around that '<=' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41 PS1, Line 41: for (i=1152;i<=1214;i++) { space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@42 PS1, Line 42: uint32_t physet = physettings[i]; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@44 PS1, Line 44: } please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45 PS1, Line 45: for (i=0;i<=1151;i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45 PS1, Line 45: for (i=0;i<=1151;i++) { suspect code indent for conditional statements (2, 4) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45 PS1, Line 45: for (i=0;i<=1151;i++) { spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45 PS1, Line 45: for (i=0;i<=1151;i++) { space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45 PS1, Line 45: for (i=0;i<=1151;i++) { spaces required around that '<=' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45 PS1, Line 45: for (i=0;i<=1151;i++) { space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@46 PS1, Line 46: uint32_t physet = physettings[i]; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@48 PS1, Line 48: } please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@52 PS1, Line 52: static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) { line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@52 PS1, Line 52: static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@53 PS1, Line 53: volatile uint32_t *ddrctlreg = (volatile uint32_t *) ahbregaddr; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@54 PS1, Line 54: volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t)); line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@54 PS1, Line 54: volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@56 PS1, Line 56: unsigned int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57 PS1, Line 57: for (i=0;i<=264;i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57 PS1, Line 57: for (i=0;i<=264;i++) { suspect code indent for conditional statements (2, 4) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57 PS1, Line 57: for (i=0;i<=264;i++) { spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57 PS1, Line 57: for (i=0;i<=264;i++) { space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57 PS1, Line 57: for (i=0;i<=264;i++) { spaces required around that '<=' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57 PS1, Line 57: for (i=0;i<=264;i++) { space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@58 PS1, Line 58: uint32_t ctlset = ctlsettings[i]; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@60 PS1, Line 60: } please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@62 PS1, Line 62: phy_reset(ddrphyreg, physettings); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@65 PS1, Line 65: static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) { line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@65 PS1, Line 65: static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@67 PS1, Line 67: uint32_t regdata = _REG32(0<<2, ahbregaddr); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@68 PS1, Line 68: regdata |= 0x1; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@69 PS1, Line 69: _REG32(0<<2, ahbregaddr) = regdata; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@70 PS1, Line 70: // WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210 line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@71 PS1, Line 71: while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {} please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@71 PS1, Line 71: while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {} trailing statements should be on next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@71 PS1, Line 71: while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {} braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@74 PS1, Line 74: volatile uint64_t *filterreg = (volatile uint64_t *)filteraddr; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@75 PS1, Line 75: filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@79 PS1, Line 79: static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@82 PS1, Line 82: _REG32(136<<2, ahbregaddr) |= (1<<MC_INIT_COMPLETE_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@85 PS1, Line 85: static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@87 PS1, Line 87: // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured 'occured' may be misspelled - perhaps 'occurred'? https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@87 PS1, Line 87: // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@88 PS1, Line 88: // Bit [1] A memory access outside the defined PHYSICAL memory space has occured 'occured' may be misspelled - perhaps 'occurred'? https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@88 PS1, Line 88: // Bit [1] A memory access outside the defined PHYSICAL memory space has occured line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@89 PS1, Line 89: _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET)); line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@89 PS1, Line 89: _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@92 PS1, Line 92: static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) { line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@92 PS1, Line 92: static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@94 PS1, Line 94: // Bit [7] An error occured on the port command channel 'occured' may be misspelled - perhaps 'occurred'? https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@95 PS1, Line 95: _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@98 PS1, Line 98: static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) { line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@98 PS1, Line 98: static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@101 PS1, Line 101: _REG32(136<<2, ahbregaddr) |= (1<<LEVELING_OPERATION_COMPLETED_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@104 PS1, Line 104: static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) { line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@104 PS1, Line 104: static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@105 PS1, Line 105: _REG32(209<<2, ahbregaddr) = 0x0; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@106 PS1, Line 106: size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@107 PS1, Line 107: _REG32(210<<2, ahbregaddr) = ((uint32_t) end_addr_16Kblocks); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@108 PS1, Line 108: _REG32(212<<2, ahbregaddr) = 0x0; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@109 PS1, Line 109: _REG32(214<<2, ahbregaddr) = 0x0; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@110 PS1, Line 110: _REG32(216<<2, ahbregaddr) = 0x0; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@111 PS1, Line 111: _REG32(224<<2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@112 PS1, Line 112: _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@113 PS1, Line 113: _REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@114 PS1, Line 114: _REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@118 PS1, Line 118: static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@119 PS1, Line 119: _REG32(120<<2, ahbregaddr) |= (1<<DISABLE_RD_INTERLEAVE_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@122 PS1, Line 122: static inline void ux00ddr_disableoptimalrmodw(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@123 PS1, Line 123: _REG32(21<<2, ahbregaddr) &= (~(1<<OPTIMAL_RMODW_EN_OFFSET)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@126 PS1, Line 126: static inline void ux00ddr_enablewriteleveling(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@127 PS1, Line 127: _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET)); line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@127 PS1, Line 127: _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@130 PS1, Line 130: static inline void ux00ddr_enablereadleveling(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@131 PS1, Line 131: _REG32(181<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_MODE_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@132 PS1, Line 132: _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_EN_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@135 PS1, Line 135: static inline void ux00ddr_enablereadlevelinggate(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@136 PS1, Line 136: _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_GATE_EN_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@137 PS1, Line 137: _REG32(182<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_GATE_MODE_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@140 PS1, Line 140: static inline void ux00ddr_enablevreftraining(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@141 PS1, Line 141: _REG32(184<<2, ahbregaddr) |= (1<<VREF_EN_OFFSET); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@144 PS1, Line 144: static inline uint32_t ux00ddr_getdramclass(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@145 PS1, Line 145: return ((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@148 PS1, Line 148: static inline uint64_t ux00ddr_phy_fixup(size_t ahbregaddr) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@151 PS1, Line 151: size_t ddrphyreg = ahbregaddr + 0x2000; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@153 PS1, Line 153: uint64_t fails=0; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@153 PS1, Line 153: uint64_t fails=0; spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@154 PS1, Line 154: uint32_t slicebase = 0; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@155 PS1, Line 155: uint32_t dq = 0; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@158 PS1, Line 158: for (uint32_t slice = 0; slice < 8; slice++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@158 PS1, Line 158: for (uint32_t slice = 0; slice < 8; slice++) { suspect code indent for conditional statements (2, 4) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@159 PS1, Line 159: uint32_t regbase = slicebase + 34; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@160 PS1, Line 160: for (uint32_t reg = 0 ; reg < 4; reg++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@160 PS1, Line 160: for (uint32_t reg = 0 ; reg < 4; reg++) { suspect code indent for conditional statements (4, 6) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@161 PS1, Line 161: uint32_t updownreg = _REG32((regbase+reg)<<2, ddrphyreg); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@162 PS1, Line 162: for (uint32_t bit = 0; bit < 2; bit++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@163 PS1, Line 163: uint32_t phy_rx_cal_dqn_0_offset; code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@163 PS1, Line 163: uint32_t phy_rx_cal_dqn_0_offset; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165 PS1, Line 165: if (bit==0) { code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165 PS1, Line 165: if (bit==0) { please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165 PS1, Line 165: if (bit==0) { suspect code indent for conditional statements (8, 10) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165 PS1, Line 165: if (bit==0) { spaces required around that '==' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165 PS1, Line 165: if (bit==0) { braces {} are not necessary for any arm of this statement https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@166 PS1, Line 166: phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET; code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@166 PS1, Line 166: phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@167 PS1, Line 167: }else{ code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@167 PS1, Line 167: }else{ please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@167 PS1, Line 167: }else{ suspect code indent for conditional statements (8, 10) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@167 PS1, Line 167: }else{ space required after that close brace '}' https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@168 PS1, Line 168: phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET; code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@168 PS1, Line 168: phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@169 PS1, Line 169: } code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@169 PS1, Line 169: } please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@171 PS1, Line 171: uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F; code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@171 PS1, Line 171: uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@172 PS1, Line 172: uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F; code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@172 PS1, Line 172: uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@174 PS1, Line 174: uint8_t failc0 = ((down == 0) && (up == 0x3F)); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@174 PS1, Line 174: uint8_t failc0 = ((down == 0) && (up == 0x3F)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@175 PS1, Line 175: uint8_t failc1 = ((up == 0) && (down == 0x3F)); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@175 PS1, Line 175: uint8_t failc1 = ((up == 0) && (down == 0x3F)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@177 PS1, Line 177: // print error message on failure code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@178 PS1, Line 178: if (failc0 || failc1) { code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@178 PS1, Line 178: if (failc0 || failc1) { please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@178 PS1, Line 178: if (failc0 || failc1) { suspect code indent for conditional statements (8, 10) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@179 PS1, Line 179: //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n"); line over 80 characters https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@179 PS1, Line 179: //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n"); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@179 PS1, Line 179: //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n"); unnecessary whitespace before a quoted newline https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@180 PS1, Line 180: fails |= (1<<dq); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@180 PS1, Line 180: fails |= (1<<dq); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@181 PS1, Line 181: char slicelsc = '0'; code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@181 PS1, Line 181: char slicelsc = '0'; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@182 PS1, Line 182: char slicemsc = '0'; code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@182 PS1, Line 182: char slicemsc = '0'; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@183 PS1, Line 183: slicelsc += (dq % 10); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@183 PS1, Line 183: slicelsc += (dq % 10); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@184 PS1, Line 184: slicemsc += (dq / 10); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@184 PS1, Line 184: slicemsc += (dq / 10); please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@185 PS1, Line 185: //uart_puts((void*) UART0_CTRL_ADDR, "S "); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@186 PS1, Line 186: //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@187 PS1, Line 187: //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@188 PS1, Line 188: //if (failc0) uart_puts((void*) UART0_CTRL_ADDR, "U"); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@189 PS1, Line 189: //else uart_puts((void*) UART0_CTRL_ADDR, "D"); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@190 PS1, Line 190: //uart_puts((void*) UART0_CTRL_ADDR, "\n"); code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@191 PS1, Line 191: } code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@191 PS1, Line 191: } please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@192 PS1, Line 192: dq++; code indent should use tabs where possible https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@192 PS1, Line 192: dq++; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@193 PS1, Line 193: } please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@194 PS1, Line 194: } please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@195 PS1, Line 195: slicebase+=128; please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@195 PS1, Line 195: slicebase+=128; spaces required around that '+=' (ctx:VxV) https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@196 PS1, Line 196: } please, no spaces at the start of a line https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@197 PS1, Line 197: return (0); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc Gerrit-Change-Number: 28604 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 09:54:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/sifive/fu540: Initialize SDRAM
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28604 Change subject: soc/sifive/fu540: Initialize SDRAM ...................................................................... soc/sifive/fu540: Initialize SDRAM Based on SiFive bootloader code Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/include/soc/addressmap.h M src/soc/sifive/fu540/sdram.c A src/soc/sifive/fu540/ux00ddr.h 4 files changed, 242 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28604/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 9729f86..df4cf89 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -40,5 +40,7 @@ uart_init(CONFIG_UART_FOR_CONSOLE); #endif + sdram_init(); + run_ramstage(); } diff --git a/src/soc/sifive/fu540/include/soc/addressmap.h b/src/soc/sifive/fu540/include/soc/addressmap.h index 0de1423..21709b5 100644 --- a/src/soc/sifive/fu540/include/soc/addressmap.h +++ b/src/soc/sifive/fu540/include/soc/addressmap.h @@ -29,6 +29,7 @@ #define FU540_ETHMAC 0x10090000 #define FU540_ETHMGMT 0x100a0000 #define FU540_DDRCTRL 0x100b0000 +#define FU540_DDRBUSBLOCKER 0x100b8000 #define FU540_DDRMGMT 0x100c0000 #define FU540_QSPI0FLASH 0x20000000 #define FU540_QSPI1FLASH 0x30000000 diff --git a/src/soc/sifive/fu540/sdram.c b/src/soc/sifive/fu540/sdram.c index 1ad36da..6418b0d 100644 --- a/src/soc/sifive/fu540/sdram.c +++ b/src/soc/sifive/fu540/sdram.c @@ -14,10 +14,46 @@ */ #include <soc/sdram.h> +#include <soc/addressmap.h> + +#include "regconfig-phy.h" +#include "regconfig-ctl.h" +#include "ux00ddr.h" + +#define DENALI_PHY_DATA ddr_phy_settings +#define DENALI_CTL_DATA ddr_ctl_settings +#include "ddrregs.h" + +#define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL) +#define DDRCTLPLL_F 55 +#define DDRCTLPLL_Q 2 void sdram_init(void) { - // TODO: implement + ux00ddr_writeregmap(FU540_DDRCTRL, ddr_ctl_settings, ddr_phy_settings); + ux00ddr_disableaxireadinterleave(FU540_DDRCTRL); + + ux00ddr_disableoptimalrmodw(FU540_DDRCTRL); + + ux00ddr_enablewriteleveling(FU540_DDRCTRL); + ux00ddr_enablereadleveling(FU540_DDRCTRL); + ux00ddr_enablereadlevelinggate(FU540_DDRCTRL); + if (ux00ddr_getdramclass(FU540_DDRCTRL) == DRAM_CLASS_DDR4) + ux00ddr_enablevreftraining(FU540_DDRCTRL); + + //mask off interrupts for leveling completion + ux00ddr_mask_leveling_completed_interrupt(FU540_DDRCTRL); + + ux00ddr_mask_mc_init_complete_interrupt(FU540_DDRCTRL); + ux00ddr_mask_outofrange_interrupts(FU540_DDRCTRL); + ux00ddr_setuprangeprotection(FU540_DDRCTRL, DDR_SIZE); + ux00ddr_mask_port_command_error_interrupt(FU540_DDRCTRL); + + const uint64_t ddr_size = DDR_SIZE; + const uint64_t ddr_end = FU540_DRAM + ddr_size; + ux00ddr_start(FU540_DDRCTRL, FU540_DDRBUSBLOCKER, ddr_end); + + ux00ddr_phy_fixup(FU540_DDRCTRL); } size_t sdram_size_mb(void) diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h new file mode 100644 index 0000000..fc5e110 --- /dev/null +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -0,0 +1,202 @@ +/* Copyright (c) 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* See the file LICENSE for further information */ + +#ifndef _SIFIVE_UX00DDR_H +#define _SIFIVE_UX00DDR_H + +#ifndef __ASSEMBLER__ + +#include <stdint.h> +#include <stddef.h> + +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) + +#define DRAM_CLASS_OFFSET 8 +#define DRAM_CLASS_DDR4 0xA +#define OPTIMAL_RMODW_EN_OFFSET 0 +#define DISABLE_RD_INTERLEAVE_OFFSET 16 +#define OUT_OF_RANGE_OFFSET 1 +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2 +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7 +#define MC_INIT_COMPLETE_OFFSET 8 +#define LEVELING_OPERATION_COMPLETED_OFFSET 22 +#define DFI_PHY_WRLELV_MODE_OFFSET 24 +#define DFI_PHY_RDLVL_MODE_OFFSET 24 +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0 +#define VREF_EN_OFFSET 24 +#define PORT_ADDR_PROTECTION_EN_OFFSET 0 +#define AXI0_ADDRESS_RANGE_ENABLE 8 +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24 +#define RDLVL_EN_OFFSET 16 +#define RDLVL_GATE_EN_OFFSET 24 +#define WRLVL_EN_OFFSET 0 + +#define PHY_RX_CAL_DQ0_0_OFFSET 0 +#define PHY_RX_CAL_DQ1_0_OFFSET 16 + +static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) { + unsigned int i; + for (i=1152;i<=1214;i++) { + uint32_t physet = physettings[i]; + /*if (physet!=0)*/ ddrphyreg[i] = physet; + } + for (i=0;i<=1151;i++) { + uint32_t physet = physettings[i]; + /*if (physet!=0)*/ ddrphyreg[i] = physet; + } +} + + +static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) { + volatile uint32_t *ddrctlreg = (volatile uint32_t *) ahbregaddr; + volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t)); + + unsigned int i; + for (i=0;i<=264;i++) { + uint32_t ctlset = ctlsettings[i]; + /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset; + } + + phy_reset(ddrphyreg, physettings); +} + +static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) { + // START register at ddrctl register base offset 0 + uint32_t regdata = _REG32(0<<2, ahbregaddr); + regdata |= 0x1; + _REG32(0<<2, ahbregaddr) = regdata; + // WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210 + while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {} + + // Disable the BusBlocker in front of the controller AXI slave ports + volatile uint64_t *filterreg = (volatile uint64_t *)filteraddr; + filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2); + // ^^ RWX + TOR +} + +static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) { + // Mask off Bit 8 of Interrupt Status + // Bit [8] The MC initialization has been completed + _REG32(136<<2, ahbregaddr) |= (1<<MC_INIT_COMPLETE_OFFSET); +} + +static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) { + // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status + // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured + // Bit [1] A memory access outside the defined PHYSICAL memory space has occured + _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET)); +} + +static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) { + // Mask off Bit 7 of Interrupt Status + // Bit [7] An error occured on the port command channel + _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET); +} + +static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) { + // Mask off Bit 22 of Interrupt Status + // Bit [22] The leveling operation has completed + _REG32(136<<2, ahbregaddr) |= (1<<LEVELING_OPERATION_COMPLETED_OFFSET); +} + +static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) { + _REG32(209<<2, ahbregaddr) = 0x0; + size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1; + _REG32(210<<2, ahbregaddr) = ((uint32_t) end_addr_16Kblocks); + _REG32(212<<2, ahbregaddr) = 0x0; + _REG32(214<<2, ahbregaddr) = 0x0; + _REG32(216<<2, ahbregaddr) = 0x0; + _REG32(224<<2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET); + _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF; + _REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE); + _REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET); + +} + +static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) { + _REG32(120<<2, ahbregaddr) |= (1<<DISABLE_RD_INTERLEAVE_OFFSET); +} + +static inline void ux00ddr_disableoptimalrmodw(size_t ahbregaddr) { + _REG32(21<<2, ahbregaddr) &= (~(1<<OPTIMAL_RMODW_EN_OFFSET)); +} + +static inline void ux00ddr_enablewriteleveling(size_t ahbregaddr) { + _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET)); +} + +static inline void ux00ddr_enablereadleveling(size_t ahbregaddr) { + _REG32(181<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_MODE_OFFSET); + _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_EN_OFFSET); +} + +static inline void ux00ddr_enablereadlevelinggate(size_t ahbregaddr) { + _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_GATE_EN_OFFSET); + _REG32(182<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_GATE_MODE_OFFSET); +} + +static inline void ux00ddr_enablevreftraining(size_t ahbregaddr) { + _REG32(184<<2, ahbregaddr) |= (1<<VREF_EN_OFFSET); +} + +static inline uint32_t ux00ddr_getdramclass(size_t ahbregaddr) { + return ((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF); +} + +static inline uint64_t ux00ddr_phy_fixup(size_t ahbregaddr) { + // return bitmask of failed lanes + + size_t ddrphyreg = ahbregaddr + 0x2000; + + uint64_t fails=0; + uint32_t slicebase = 0; + uint32_t dq = 0; + + // check errata condition + for (uint32_t slice = 0; slice < 8; slice++) { + uint32_t regbase = slicebase + 34; + for (uint32_t reg = 0 ; reg < 4; reg++) { + uint32_t updownreg = _REG32((regbase+reg)<<2, ddrphyreg); + for (uint32_t bit = 0; bit < 2; bit++) { + uint32_t phy_rx_cal_dqn_0_offset; + + if (bit==0) { + phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET; + }else{ + phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET; + } + + uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F; + uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F; + + uint8_t failc0 = ((down == 0) && (up == 0x3F)); + uint8_t failc1 = ((up == 0) && (down == 0x3F)); + + // print error message on failure + if (failc0 || failc1) { + //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n"); + fails |= (1<<dq); + char slicelsc = '0'; + char slicemsc = '0'; + slicelsc += (dq % 10); + slicemsc += (dq / 10); + //uart_puts((void*) UART0_CTRL_ADDR, "S "); + //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc); + //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc); + //if (failc0) uart_puts((void*) UART0_CTRL_ADDR, "U"); + //else uart_puts((void*) UART0_CTRL_ADDR, "D"); + //uart_puts((void*) UART0_CTRL_ADDR, "\n"); + } + dq++; + } + } + slicebase+=128; + } + return (0); +} + +#endif + +#endif -- To view, visit https://review.coreboot.org/28604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc Gerrit-Change-Number: 28604 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by build bot (Jenkins) (Code Review) 14 Sep '18

14 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28602 ) Change subject: soc/sifive/fu540: Switch clock to 1GHz in romstage ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/28602/5/src/soc/sifive/fu540/clock.c File src/soc/sifive/fu540/clock.c: https://review.coreboot.org/#/c/28602/5/src/soc/sifive/fu540/clock.c@198 PS5, Line 198: write32((uint32_t *)(FU540_UART(i) + FU540_UART_REG_DIV), FU540_UART_DIV_VAL); line over 80 characters -- To view, visit https://review.coreboot.org/28602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Gerrit-Change-Number: 28602 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 09:31:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28602 to look at the new patch set (#5). Change subject: soc/sifive/fu540: Switch clock to 1GHz in romstage ...................................................................... soc/sifive/fu540: Switch clock to 1GHz in romstage Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/clock.c 3 files changed, 64 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28602/5 -- To view, visit https://review.coreboot.org/28602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Gerrit-Change-Number: 28602 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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