coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by build bot (Jenkins) (Code Review) 14 Sep '18

14 Sep '18

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Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28602 to look at the new patch set (#4). Change subject: soc/sifive/fu540: Switch clock to 1GHz in romstage ...................................................................... soc/sifive/fu540: Switch clock to 1GHz in romstage Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/clock.c 3 files changed, 64 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28602/4 -- To view, visit https://review.coreboot.org/28602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Gerrit-Change-Number: 28602 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by build bot (Jenkins) (Code Review) 14 Sep '18

14 Sep '18

1 0

Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28602 to look at the new patch set (#3). Change subject: soc/sifive/fu540: Switch clock to 1GHz in romstage ...................................................................... soc/sifive/fu540: Switch clock to 1GHz in romstage Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/clock.c 3 files changed, 65 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28602/3 -- To view, visit https://review.coreboot.org/28602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Gerrit-Change-Number: 28602 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by build bot (Jenkins) (Code Review) 14 Sep '18

14 Sep '18

1 0

Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Philipp Hug has uploaded a new patch set (#2). ( https://review.coreboot.org/28602 ) Change subject: soc/sifive/fu540: Switch clock to 1GHz in romstage ...................................................................... soc/sifive/fu540: Switch clock to 1GHz in romstage Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/clock.c 3 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28602/2 -- To view, visit https://review.coreboot.org/28602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Gerrit-Change-Number: 28602 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/riscv: add missing endian.h header to io.h
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Philipp Hug has uploaded a new patch set (#2). ( https://review.coreboot.org/28601 ) Change subject: arch/riscv: add missing endian.h header to io.h ...................................................................... arch/riscv: add missing endian.h header to io.h Make it uniform as other architectures also include it in io.h Change-Id: I62c2d909c703f01cdaabdaaba344f82b6746f094 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/include/arch/io.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/28601/2 -- To view, visit https://review.coreboot.org/28601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I62c2d909c703f01cdaabdaaba344f82b6746f094 Gerrit-Change-Number: 28601 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: nb/intel/haswell: Move MMCONF_BASE_ADDRESS to northbridge Kconfig
by Elyes HAOUAS (Code Review) 14 Sep '18

14 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28603 Change subject: nb/intel/haswell: Move MMCONF_BASE_ADDRESS to northbridge Kconfig ...................................................................... nb/intel/haswell: Move MMCONF_BASE_ADDRESS to northbridge Kconfig Change-Id: I44f27405fc8ccbe54c7d19b70327da866390a156 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/beltino/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/intel/baskingridge/Kconfig M src/northbridge/intel/haswell/Kconfig 4 files changed, 4 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/28603/1 diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index aaec9f7..2f51461 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -53,10 +53,6 @@ default "X86 TRICKY TEST 4487" if BOARD_GOOGLE_TRICKY default "X86 ZAKO TEST 8602" if BOARD_GOOGLE_ZAKO -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6891c0b..c56eb3d 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -61,10 +61,6 @@ default "variants/peppy/devicetree.cb" if BOARD_GOOGLE_PEPPY default "variants/wolf/devicetree.cb" if BOARD_GOOGLE_WOLF -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - config MAX_CPUS int default 8 diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 1fd07c2..2119d47de 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -25,10 +25,6 @@ string default "BASKING RIDGE" -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - config MAX_CPUS int default 16 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index f9c68f3..0362ffe 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -36,6 +36,10 @@ string default "8086,0166" +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + config CACHE_MRC_SIZE_KB int default 512 -- To view, visit https://review.coreboot.org/28603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I44f27405fc8ccbe54c7d19b70327da866390a156 Gerrit-Change-Number: 28603 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by build bot (Jenkins) (Code Review) 14 Sep '18

14 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28602 ) Change subject: soc/sifive/fu540: Switch clock to 1GHz in romstage ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/28602/1/src/soc/sifive/fu540/clock.c File src/soc/sifive/fu540/clock.c: https://review.coreboot.org/#/c/28602/1/src/soc/sifive/fu540/clock.c@209 PS1, Line 209: void static update_peripheral_clock_dividers(void) storage class 'static' should be located before type 'void' https://review.coreboot.org/#/c/28602/1/src/soc/sifive/fu540/clock.c@215 PS1, Line 215: for (size_t i = 0; i < FU540_UART_DEVICES; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28602/1/src/soc/sifive/fu540/clock.c@216 PS1, Line 216: write32((uint32_t *)(FU540_UART(i) + FU540_UART_REG_DIV), FU540_UART_DIV_VAL); line over 80 characters https://review.coreboot.org/#/c/28602/1/src/soc/sifive/fu540/clock.c@224 PS1, Line 224: * values as we can't put them in reset before changing frequency. code indent should use tabs where possible -- To view, visit https://review.coreboot.org/28602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Gerrit-Change-Number: 28602 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 08:33:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/sifive/fu540: Switch clock to 1GHz in romstage
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28602 Change subject: soc/sifive/fu540: Switch clock to 1GHz in romstage ...................................................................... soc/sifive/fu540: Switch clock to 1GHz in romstage Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/clock.c 3 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28602/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index ea6efb9..9729f86 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -13,8 +13,13 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> +#include <console/streams.h> +#include <console/uart.h> #include <program_loading.h> +#include <soc/clock.h> +#include <soc/sdram.h> void main(void) { @@ -22,5 +27,18 @@ /* TODO: Follow Section 6.3 (FSBL) of the FU540 manual */ + /* + * Flush console before changing clock/UART divisor to prevent garbage + * being printed. + */ + console_tx_flush(); + + clock_init(); + + // re-initialize UART + #if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + uart_init(CONFIG_UART_FOR_CONSOLE); + #endif + run_ramstage(); } diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index b991783..ed1836e 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += media.c romstage-y += sdram.c romstage-y += otp.c +romstage-y += clock.c ramstage-y += uart.c ramstage-y += clint.c @@ -29,6 +30,7 @@ ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c +ramstage-y += clock.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index a98a093..5fcf5bd 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -198,8 +198,33 @@ / (1ul << divq); } +#define FU540_UART_DEVICES 2 +#define FU540_UART_REG_DIV 0x18 +#define FU540_UART_DIV_VAL 4 + +#define FU540_SPI_DIV 0x00 +#define FU540_SPI_DIV_VAL 4 + + +void static update_peripheral_clock_dividers(void) +{ + write32((uint32_t *)(FU540_QSPI0 + FU540_SPI_DIV), FU540_SPI_DIV_VAL); + write32((uint32_t *)(FU540_QSPI1 + FU540_SPI_DIV), FU540_SPI_DIV_VAL); + write32((uint32_t *)(FU540_QSPI2 + FU540_SPI_DIV), FU540_SPI_DIV_VAL); + + for (size_t i = 0; i < FU540_UART_DEVICES; i++) { + write32((uint32_t *)(FU540_UART(i) + FU540_UART_REG_DIV), FU540_UART_DIV_VAL); + } +} + void clock_init(void) { + /* + * Update the peripheral clock dividers of UART, SPI and I2C to safe + * values as we can't put them in reset before changing frequency. + */ + update_peripheral_clock_dividers(); + init_coreclk(); // put DDR and ethernet in reset -- To view, visit https://review.coreboot.org/28602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Gerrit-Change-Number: 28602 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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coreboot-gerrit September 2018