coreboot-gerrit September 2018

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Change in coreboot[master]: arch/riscv: add missing endian.h header to io.h
by Philipp Hug (Code Review) 14 Sep '18

14 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28601 Change subject: arch/riscv: add missing endian.h header to io.h ...................................................................... arch/riscv: add missing endian.h header to io.h Change-Id: I62c2d909c703f01cdaabdaaba344f82b6746f094 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/include/arch/io.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/28601/1 diff --git a/src/arch/riscv/include/arch/io.h b/src/arch/riscv/include/arch/io.h index a19f4b5..fa52c5e 100644 --- a/src/arch/riscv/include/arch/io.h +++ b/src/arch/riscv/include/arch/io.h @@ -14,6 +14,7 @@ #ifndef _ASM_IO_H #define _ASM_IO_H +#include <endian.h> #include <stdint.h> static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr) -- To view, visit https://review.coreboot.org/28601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62c2d909c703f01cdaabdaaba344f82b6746f094 Gerrit-Change-Number: 28601 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Arthur Heymans (Code Review) 14 Sep '18

14 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28596 to look at the new patch set (#5). Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... mb/asrock/g41m_vs3_r2: Add mainboard The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Kconfig.name M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl M src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb 5 files changed, 197 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28596/5 -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Makefile.inc: Fix dependency tracking of fmap{_config.h, .desc}
by Patrick Georgi (Code Review) 14 Sep '18

14 Sep '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/28198 ) Change subject: Makefile.inc: Fix dependency tracking of fmap{_config.h,.desc} ...................................................................... Patch Set 2: > Patch Set 2: > > The code looks quite strange and in fact, these are false dependencies. If you e.g. `touch fmap.fmap`, `make` will call `true` in an attempt to update `fmap_config.h`, every time without real success. > > If you have a recipe like the one for `fmap.fmap` that builds a number of targets, then the right thing to do is to define multiple targets in the rule: https://www.gnu.org/software/make/manual/html_node/Multiple-Targets.html > > Feel free to update the fix :) well, don't touch fmap.fmap then :) The problem with multiple targets in make is that it's just a shorthand: a b c: d foo means that it call foo to generate a, call foo to generate b, and call foo to generate c. in a parallelized build, it will even call them in parallel, which means you have three processes trying to write to the same three files at the same time - which might or might not work out well (nevermind the additional build load) -- To view, visit https://review.coreboot.org/28198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic7ecb88cf7df7f2488defd47ea02255fc10a67e9 Gerrit-Change-Number: 28198 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 14 Sep 2018 05:55:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Makefile.inc: Fix dependency tracking of fmap{_config.h, .desc}
by Alex Thiessen (Code Review) 14 Sep '18

14 Sep '18

Alex Thiessen has posted comments on this change. ( https://review.coreboot.org/28198 ) Change subject: Makefile.inc: Fix dependency tracking of fmap{_config.h,.desc} ...................................................................... Patch Set 2: The code looks quite strange and in fact, these are false dependencies. If you e.g. `touch fmap.fmap`, `make` will call `true` in an attempt to update `fmap_config.h`, every time without real success. If you have a recipe like the one for `fmap.fmap` that builds a number of targets, then the right thing to do is to define multiple targets in the rule: https://www.gnu.org/software/make/manual/html_node/Multiple-Targets.html Feel free to update the fix :) -- To view, visit https://review.coreboot.org/28198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic7ecb88cf7df7f2488defd47ea02255fc10a67e9 Gerrit-Change-Number: 28198 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 14 Sep 2018 00:09:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Arthur Heymans (Code Review) 13 Sep '18

13 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28596 to look at the new patch set (#4). Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... mb/asrock/g41m_vs3_r2: Add mainboard The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Kconfig.name M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl M src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb 5 files changed, 196 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28596/4 -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Arthur Heymans (Code Review) 13 Sep '18

13 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28596 to look at the new patch set (#3). Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... mb/asrock/g41m_vs3_r2: Add mainboard The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Kconfig.name M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl M src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb 5 files changed, 196 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28596/3 -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/kahlee/variants/careena/devicetree.cb: Set STAPM values
by Richard Spiegel (Code Review) 13 Sep '18

13 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28597 Change subject: mb/google/kahlee/variants/careena/devicetree.cb: Set STAPM values ...................................................................... mb/google/kahlee/variants/careena/devicetree.cb: Set STAPM values AMD has tested careena, and for the time being is recommending a scalar of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM configuration code, set the desired values. BUG=b:111561217 TEST=none, code was tested with grunt. Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/28597/1 diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 513bd4e..ef24b45 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -20,6 +20,9 @@ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" + register "stapm_percent" = "68" + register "stapm_time" = "2500" + register "stapm_power" = "7800" # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ -- To view, visit https://review.coreboot.org/28597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e Gerrit-Change-Number: 28597 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Arthur Heymans (Code Review) 13 Sep '18

13 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28596 to look at the new patch set (#2). Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... mb/asrock/g41m_vs3_r2: Add mainboard The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Kconfig.name M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl M src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb 5 files changed, 196 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28596/2 -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Arthur Heymans (Code Review) 13 Sep '18

13 Sep '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28596 Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... mb/asrock/g41m_vs3_r2: Add mainboard The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with native graphic init - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Kconfig.name M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl M src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb 5 files changed, 196 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28596/1 diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index ad2fe22..e2ad83b 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -14,7 +14,7 @@ # GNU General Public License for more details. # -if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS +if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_VS3_R2_0 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -24,7 +24,7 @@ select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0 select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS \ - || BOARD_ASROCK_G41M_GS + || BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_VS3_R2_0 select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select PCIEXP_ASPM @@ -46,12 +46,14 @@ default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0 default "G41C-GS" if BOARD_ASROCK_G41C_GS default "G41M-GS" if BOARD_ASROCK_G41M_GS + default "G41M-VS3 R2.0" if BOARD_ASROCK_G41M_VS3_R2_0 config DEVICETREE string default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0 default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS + default "variants/g41m-vs3-r2/devicetree.cb" if BOARD_ASROCK_G41M_VS3_R2_0 config MAX_CPUS int diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name index 329a3e2..e10558c 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig.name +++ b/src/mainboard/asrock/g41c-gs/Kconfig.name @@ -6,3 +6,6 @@ config BOARD_ASROCK_G41M_GS bool "G41M-GS" + +config BOARD_ASROCK_G41M_VS3_R2_0 + bool "G41M-VS3 R2.0" diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl index bb8745e..21cec96 100644 --- a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl @@ -18,6 +18,9 @@ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 */ +#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) + || IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS) + || IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) If (PICM) { Return (Package() { /* PCI1 SLOT 1 */ @@ -51,3 +54,38 @@ /* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */ }) } +#else /* BOARD_ASROCK_G41M_VS3_R2_0 */ +If (PICM) { + Return (Package() { + /* PCI1 SLOT 1 */ + Package() { 0x0000ffff, 0, 0, 0x11}, + Package() { 0x0000ffff, 1, 0, 0x12}, + Package() { 0x0000ffff, 2, 0, 0x13}, + Package() { 0x0000ffff, 3, 0, 0x10}, + + /* PCI1 SLOT 2 */ + Package() { 0x0002ffff, 0, 0, 0x17}, + Package() { 0x0002ffff, 1, 0, 0x14}, + Package() { 0x0002ffff, 2, 0, 0x15}, + Package() { 0x0002ffff, 3, 0, 0x16}, + + /* device not in lspci but in vendor DSDT */ + /* Package() { 0x0008ffff, 0, 0, 0x14}, */ + }) +} Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + /* device not in lspci but in vendor DSDT */ + /* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */ + }) +} +#endif \ No newline at end of file diff --git a/src/mainboard/asrock/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/gpio.c index b6ccbad..3508950 100644 --- a/src/mainboard/asrock/g41c-gs/gpio.c +++ b/src/mainboard/asrock/g41c-gs/gpio.c @@ -40,8 +40,13 @@ .gpio0 = GPIO_DIR_INPUT, .gpio6 = GPIO_DIR_INPUT, .gpio7 = GPIO_DIR_INPUT, +#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0) + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_OUTPUT, +#else .gpio8 = GPIO_DIR_INPUT, .gpio9 = GPIO_DIR_INPUT, +#endif .gpio10 = GPIO_DIR_OUTPUT, .gpio12 = GPIO_DIR_INPUT, .gpio13 = GPIO_DIR_INPUT, @@ -67,6 +72,10 @@ #if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) static const struct pch_gpio_set1 pch_gpio_set1_level = { +#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0) + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, +#endif .gpio10 = GPIO_LEVEL_LOW, .gpio15 = GPIO_LEVEL_LOW, .gpio16 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb new file mode 100644 index 0000000..2b0da8f --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1849 0x2e30 + end + device pci 1.0 on end # PEG + + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1849 0x2e32 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + + register "ide_enable_primary" = "0x1" + register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant + register "gpe0_en" = "0x440" + + device pci 1b.0 on # Audio + subsystemid 0x1849 0x3662 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 (ethernet) + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on # USB + subsystemid 0x1849 0x27c8 + end + device pci 1d.1 on # USB + subsystemid 0x1849 0x27c9 + end + device pci 1d.2 on # USB + subsystemid 0x1849 0x27ca + end + device pci 1d.3 on # USB + subsystemid 0x1849 0x27cb + end + device pci 1d.7 on # USB + subsystemid 0x1849 0x27cc + end + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # ISA bridge + subsystemid 0x1849 0x27b8 + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + irq 0x28 = 0x70 + irq 0x2c = 0xd2 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2 + device pnp 2e.5 on # Keyboard & MOUSE + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 0x0C + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 off end # GPIO6 + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 on # GPIO4 + irq 0xf4 = 0xb3 + end + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # Power dram during s3 + end + device pnp 2e.b on # HWM, front pannel LED + io 0x60 = 0x290 + irq 0x70 = 0 + end + device pnp 2e.c off end # PECI, SST + end + end + device pci 1f.1 on # PATA/IDE + subsystemid 0x1849 0x27df + end + device pci 1f.2 on # SATA + subsystemid 0x1849 0x27c0 + end + device pci 1f.3 on # SMbus + subsystemid 0x1849 0x27da + chip drivers/i2c/ck505 # W83115RG-965 + # set SATA to fixed 100Mhz refclk + register "mask" = "{ 0x02 }" + register "regs" = "{ 0x02 }" + device i2c 69 on end + end + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree
by Arthur Heymans (Code Review) 13 Sep '18

13 Sep '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28595 Change subject: mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree ...................................................................... mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/28595/1 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index f58fae7..dba3a69 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -62,6 +62,8 @@ device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end @@ -78,6 +80,8 @@ subsystemid 0x1849 0x27cc end device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # ISA bridge subsystemid 0x1849 0x27b8 chip superio/nuvoton/nct6776 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 36335c8..f12a50b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -57,6 +57,8 @@ device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end @@ -73,6 +75,8 @@ subsystemid 0x1849 0x27cc end device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # ISA bridge subsystemid 0x1849 0x27b8 chip superio/winbond/w83627dhg -- To view, visit https://review.coreboot.org/28595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca Gerrit-Change-Number: 28595 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit September 2018