coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

1 participants
886 discussions

Change in coreboot[master]: device/ddr3: Prevent overflow when adding SMBUS Table 17 entries
by Felix Held (Code Review) 14 Sep '18

14 Sep '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/28588 ) Change subject: device/ddr3: Prevent overflow when adding SMBUS Table 17 entries ...................................................................... device/ddr3: Prevent overflow when adding SMBUS Table 17 entries Change-Id: If84c6849011106b2a50e504b79cda9cd6a3a9cc3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/28588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/dram/ddr3.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 63ca964..f27fdcb 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -559,6 +559,12 @@ memset(mem_info, 0, sizeof(*mem_info)); } + if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) { + printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n", + __func__); + return CB_ERR; + } + dimm = &mem_info->dimm[mem_info->dimm_cnt]; if (info->size_mb) { dimm->ddr_type = MEMORY_TYPE_DDR3; -- To view, visit https://review.coreboot.org/28588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If84c6849011106b2a50e504b79cda9cd6a3a9cc3 Gerrit-Change-Number: 28588 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR
by Richard Spiegel (Code Review) 14 Sep '18

14 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28608 ) Change subject: amd/stoneyridge: Sync PSP base to MSR ...................................................................... Patch Set 1: > Patch Set 1: > > I still don't see how this can have anything to do with the TPM that would be reported by coreboot. Grunt uses a discrete TPM and not the fTPM in the PSP. > > I hadn't tried S3. However, I get a GPF on resume during mp_init when the MSR is rewritten. It's easy enough to skip it on a resume, but I'd like some direction from AMD instead of flailing like this. Could it be that the S3 failure was actually GPF? Could it be that the MSR is preserved through S3, thus causing GPF when written again? -- To view, visit https://review.coreboot.org/28608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Gerrit-Change-Number: 28608 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 20:14:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree
by Felix Held (Code Review) 14 Sep '18

14 Sep '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28595 ) Change subject: mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca Gerrit-Change-Number: 28595 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 20:09:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/intel/coffeelake_rvp: GPIO support for whiskey board
by Lijian Zhao (Code Review) 14 Sep '18

14 Sep '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/28367 ) Change subject: mb/intel/coffeelake_rvp: GPIO support for whiskey board ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28367/2/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/28367/2/src/mainboard/intel/coffeelake_rvp/… PS2, Line 266: #if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) : PAD_CFG_GPO(GPP_H22, 1, PLTRST), : #endif > With this GPP_H22 gets programmed 2 times for WHISKEYLAKE_RVP, keep #if and #else ? Done -- To view, visit https://review.coreboot.org/28367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Gerrit-Change-Number: 28367 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 19:30:52 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/intel/coffeelake_rvp: GPIO support for whiskey board
by Lijian Zhao (Code Review) 14 Sep '18

14 Sep '18

Hello Pratikkumar V Prajapati, Subrata Banik, Bora Guvendik, build bot (Jenkins), Hannah Williams, Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28367 to look at the new patch set (#3). Change subject: mb/intel/coffeelake_rvp: GPIO support for whiskey board ...................................................................... mb/intel/coffeelake_rvp: GPIO support for whiskey board Add gpio programming difference for whiskeylake rvp platform. BUG=N/A TEST=N/A Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28367/3 -- To view, visit https://review.coreboot.org/28367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Gerrit-Change-Number: 28367 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR
by Marshall Dawson (Code Review) 14 Sep '18

14 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28608 ) Change subject: amd/stoneyridge: Sync PSP base to MSR ...................................................................... Patch Set 1: I still don't see how this can have anything to do with the TPM that would be reported by coreboot. Grunt uses a discrete TPM and not the fTPM in the PSP. I hadn't tried S3. However, I get a GPF on resume during mp_init when the MSR is rewritten. It's easy enough to skip it on a resume, but I'd like some direction from AMD instead of flailing like this. -- To view, visit https://review.coreboot.org/28608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Gerrit-Change-Number: 28608 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 17:38:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR
by Richard Spiegel (Code Review) 14 Sep '18

14 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28608 ) Change subject: amd/stoneyridge: Sync PSP base to MSR ...................................................................... Patch Set 1: Have you tested it through S3 suspend/resume? The code looks right from what I investigated, but I was having problems accessing TPM on the resume path (and it would not resume at all). -- To view, visit https://review.coreboot.org/28608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Gerrit-Change-Number: 28608 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 16:54:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR
by Marshall Dawson (Code Review) 14 Sep '18

14 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28608 Change subject: amd/stoneyridge: Sync PSP base to MSR ...................................................................... amd/stoneyridge: Sync PSP base to MSR According to AMD, there exists an undocumented MSR which must be written with the PSP's base address. Read the value from the PSP's config space and sync each core's copy of the MSR to match. BUG=b:76167350 TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/cpu.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/28608/1 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 43ee6a0..8e2703d 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -121,6 +121,15 @@ { check_mca(); setup_lapic(); + + /* Per AMD, sync an undocumented MSR with the PSP base address */ + msr_t psp_msr; + uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ + psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); + psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + psp_msr.hi = 0; + psp_msr.lo = psp_bar; + wrmsr(0xc00110a2, psp_msr); } static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/28608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Gerrit-Change-Number: 28608 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706
by Richard Spiegel (Code Review) 14 Sep '18

14 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28607 Change subject: arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706 ...................................................................... arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706 There are 8 possible BERT context errors, with table ctx_names being a table to print their names. Thus the table is supposed to have 8 elements, and indeed it has 8 lines... but some lines are missing commas, and when compiling it becomes a 5 element table. Add the commas at the appropriate places. BUG=b:115719190 TEST=none. Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/arch/x86/acpi_bert_storage.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/28607/1 diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 82ecc5f..961faa6 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -311,9 +311,9 @@ "MSR Registers", "32-bit Mode Execution", "64-bit Mode Execution", - "FXSAVE" - "32-bit Mode Debug" - "64-bit Mode Debug" + "FXSAVE", + "32-bit Mode Debug", + "64-bit Mode Debug", "Memory Mapped" }; -- To view, visit https://review.coreboot.org/28607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5 Gerrit-Change-Number: 28607 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Angel Pons (Code Review) 14 Sep '18

14 Sep '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28596 ) Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/28596/5/src/mainboard/asrock/g41c-gs/acpi/i… File src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl: https://review.coreboot.org/#/c/28596/5/src/mainboard/asrock/g41c-gs/acpi/i… PS5, Line 57: #else /* BOARD_ASROCK_G41M_VS3_R2_0 */ IMHO, this should be the #if's condition. -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 15:03:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

← Newer
1
...
51
52
53
54
55
56
57
...
89
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2018