coreboot-gerrit September 2018

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by build bot (Jenkins) (Code Review) 15 Sep '18

15 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28606 ) Change subject: WIP: Port libpayload to riscv ...................................................................... Patch Set 6: (39 comments) https://review.coreboot.org/#/c/28606/6/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/28606/6/payloads/external/LinuxBoot/Makefil… PS6, Line 78: echo "BEFOR DEF" 'BEFOR' may be misspelled - perhaps 'BEFORE'? https://review.coreboot.org/#/c/28606/6/payloads/libpayload/arch/riscv/core… File payloads/libpayload/arch/riscv/coreboot.c: https://review.coreboot.org/#/c/28606/6/payloads/libpayload/arch/riscv/core… PS6, Line 42: switch(rec->tag) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/asm.h: https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 24: name: labels should not be indented https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 27: .size name, .-name space required before that '-' (ctx:VxV) https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/barrier.h: https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 57: #define mb() memory barrier without comment https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 58: #define rmb() memory barrier without comment https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 59: #define wmb() memory barrier without comment https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/cache.h: https://review.coreboot.org/#/c/28606/6/payloads/libpayload/include/riscv/a… PS6, Line 81: } void function return statements are not generally useful https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/linuxcheck.c File payloads/linuxcheck/linuxcheck.c: https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/linuxcheck.c@31 PS6, Line 31: // buts("Greetings from linuxcheck, via hard-coded calls to serial functions.\n"); line over 80 characters https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c File payloads/linuxcheck/riscv-fu540.c: https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@25 PS6, Line 25: uint32_t txdata; /* Transmit data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@25 PS6, Line 25: uint32_t txdata; /* Transmit data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@26 PS6, Line 26: uint32_t rxdata; /* Receive data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@26 PS6, Line 26: uint32_t rxdata; /* Receive data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@27 PS6, Line 27: uint32_t txctrl; /* Transmit control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@27 PS6, Line 27: uint32_t txctrl; /* Transmit control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@28 PS6, Line 28: uint32_t rxctrl; /* Receive control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@28 PS6, Line 28: uint32_t rxctrl; /* Receive control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@29 PS6, Line 29: uint32_t ie; /* UART interrupt enable */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@29 PS6, Line 29: uint32_t ie; /* UART interrupt enable */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@30 PS6, Line 30: uint32_t ip; /* UART interrupt pending */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@30 PS6, Line 30: uint32_t ip; /* UART interrupt pending */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@31 PS6, Line 31: uint32_t div; /* Baud rate divisor */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@31 PS6, Line 31: uint32_t div; /* Baud rate divisor */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@36 PS6, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@36 PS6, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@41 PS6, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@41 PS6, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@43 PS6, Line 43: while (!uart_can_tx(regs)) code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@43 PS6, Line 43: while (!uart_can_tx(regs)) please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@44 PS6, Line 44: ; /* TODO: implement a timeout */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@44 PS6, Line 44: ; /* TODO: implement a timeout */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@46 PS6, Line 46: write32(&regs->txdata, data); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/6/payloads/linuxcheck/riscv-fu540.c@46 PS6, Line 46: write32(&regs->txdata, data); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: comment Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 12:56:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...
by Jonathan Neuschäfer (Code Review) 15 Sep '18

15 Sep '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28617 ) Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store ...................................................................... Patch Set 2: Code-Review-1 -- To view, visit https://review.coreboot.org/28617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Gerrit-Change-Number: 28617 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Ronald Minnich <rminnich(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 12:56:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28606 to look at the new patch set (#6). Change subject: WIP: Port libpayload to riscv ...................................................................... WIP: Port libpayload to riscv Work-in-progress port of libpayload to RISC-V Do not merge yet Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c A payloads/libpayload/arch/riscv/sysinfo.c A payloads/libpayload/arch/riscv/timer.c A payloads/libpayload/arch/riscv/util.S A payloads/libpayload/arch/riscv/virtual.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/config.riscv A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/barrier.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h M payloads/linuxcheck/Makefile M payloads/linuxcheck/linuxcheck.c M payloads/linuxcheck/linuxcheck.h A payloads/linuxcheck/riscv-fu540.c 29 files changed, 1,140 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28606/6 -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: newpatchset Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...
by Jonathan Neuschäfer (Code Review) 15 Sep '18

15 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28617 to look at the new patch set (#2). Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store ...................................................................... [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store TODO: test! TODO: clean up Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling") Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/misaligned.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/28617/2 -- To view, visit https://review.coreboot.org/28617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Gerrit-Change-Number: 28617 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo: Add libgfxinit support on Lenovo T520
by Evgeny Zinoviev (Code Review) 15 Sep '18

15 Sep '18

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/28620 Change subject: mb/lenovo: Add libgfxinit support on Lenovo T520 ...................................................................... mb/lenovo: Add libgfxinit support on Lenovo T520 Change-Id: I4fcdb7467f1911af722f4c24ce64807079a91340 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/Makefile.inc A src/mainboard/lenovo/t520/gma-mainboard.ads 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/28620/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 85dedb3..79455e2 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -15,6 +15,7 @@ select HAVE_ACPI_RESUME select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 5c450eb..7187013 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -16,3 +16,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t520/gma-mainboard.ads b/src/mainboard/lenovo/t520/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/lenovo/t520/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/28620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4fcdb7467f1911af722f4c24ce64807079a91340 Gerrit-Change-Number: 28620 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>

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Change in coreboot[master]: util/autoport: Add ICH6-M
by Patrick Rudolph (Code Review) 15 Sep '18

15 Sep '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28618 ) Change subject: util/autoport: Add ICH6-M ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Signed-off-by: Must contain real name and email https://review.coreboot.org/#/c/28618/1/util/inteltool/inteltool.h File util/inteltool/inteltool.h: https://review.coreboot.org/#/c/28618/1/util/inteltool/inteltool.h@75 PS1, Line 75: #define PCI_DEVICE_ID_INTEL_ICH6M 0x9d58 Wrong PCI ID, 9d58 is "Kaby Lake U Premium" -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 12:29:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/autoport: Add ICH6-M
by Daniel Maslowski (Code Review) 15 Sep '18

15 Sep '18

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/28618 Change subject: util/autoport: Add ICH6-M ...................................................................... util/autoport: Add ICH6-M Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Signed-off-by: YOLO --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28618/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index d0b4279..9b95650 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -147,6 +147,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6M, "ICH6-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 5de73aa..d096d43 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -72,6 +72,7 @@ #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc #define PCI_DEVICE_ID_INTEL_ICH5 0x24d0 #define PCI_DEVICE_ID_INTEL_ICH6 0x2640 +#define PCI_DEVICE_ID_INTEL_ICH6M 0x9d58 #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org>

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Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...
by build bot (Jenkins) (Code Review) 15 Sep '18

15 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28617 ) Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28617/1/src/arch/riscv/misaligned.c File src/arch/riscv/misaligned.c: https://review.coreboot.org/#/c/28617/1/src/arch/riscv/misaligned.c@273 PS1, Line 273: write_csr(mepc, read_csr(mepc) + is_compressed? 2:4); spaces required around that '?' (ctx:VxW) -- To view, visit https://review.coreboot.org/28617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Gerrit-Change-Number: 28617 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 11:52:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...
by Jonathan Neuschäfer (Code Review) 15 Sep '18

15 Sep '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28617 ) Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store ...................................................................... Patch Set 1: Code-Review-1 Don't merge it yet -- To view, visit https://review.coreboot.org/28617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Gerrit-Change-Number: 28617 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Comment-Date: Sat, 15 Sep 2018 11:52:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...
by Jonathan Neuschäfer (Code Review) 15 Sep '18

15 Sep '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28617 Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store ...................................................................... [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store TODO: test! TODO: clean up Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling") Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/misaligned.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/28617/1 diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index cb045b8..7ac810f 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -174,11 +174,15 @@ { uintptr_t insn = 0; union endian_buf buff; + bool is_compressed = false; /* try to fetch 16/32 bits instruction */ - if (fetch_16bit_instruction(tf->epc, &insn)) - if (fetch_32bit_instruction(tf->epc, &insn)) + if (fetch_16bit_instruction(tf->epc, &insn) < 0) { + if (fetch_32bit_instruction(tf->epc, &insn) < 0) redirect_trap(); + } else { + is_compressed = true; + } /* matching instruction */ struct memory_instruction_info *match = match_instruction(insn); @@ -264,4 +268,7 @@ mprv_write_u8(addr, buff.b[i]); } } + + /* return to where we came from */ + write_csr(mepc, read_csr(mepc) + is_compressed? 2:4); } -- To view, visit https://review.coreboot.org/28617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Gerrit-Change-Number: 28617 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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coreboot-gerrit September 2018