coreboot-gerrit September 2018

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Change in coreboot[master]: drivers/spi: Read Winbond's flash protection bits
by Philipp Deppenwiese (Code Review) 16 Sep '18

16 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/25082 ) Change subject: drivers/spi: Read Winbond's flash protection bits ...................................................................... drivers/spi: Read Winbond's flash protection bits Extend the generic flash interface to probe for write protected regions. Add Winbond custom code to return flash protection. Tested on Cavium EVB CN81xx using W25Q128. Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/25082 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c M src/include/spi_flash.h 3 files changed, 202 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f271479..c484088 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -432,6 +432,28 @@ return -1; } +int spi_flash_is_write_protected(const struct spi_flash *flash, + const struct region *region) +{ + struct region flash_region = { 0 }; + + if (!flash || !region) + return -1; + + flash_region.size = flash->size; + + if (!region_is_subregion(&flash_region, region)) + return -1; + + if (!flash->ops->get_write_protection) { + printk(BIOS_WARNING, "SPI: Write-protection gathering not " + "implemented for this vendor.\n"); + return 0; + } + + return flash->ops->get_write_protection(flash, region); +} + static uint32_t volatile_group_count CAR_GLOBAL; int spi_flash_volatile_group_begin(const struct spi_flash *flash) diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index a25c9a6..a0e3884 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -9,6 +9,7 @@ #include <spi_flash.h> #include <spi-generic.h> #include <string.h> +#include <assert.h> #include "spi_flash_internal.h" @@ -17,6 +18,8 @@ #define CMD_W25_WRDI 0x04 /* Write Disable */ #define CMD_W25_RDSR 0x05 /* Read Status Register */ #define CMD_W25_WRSR 0x01 /* Write Status Register */ +#define CMD_W25_RDSR2 0x35 /* Read Status2 Register */ +#define CMD_W25_WRSR2 0x31 /* Write Status2 Register */ #define CMD_W25_READ 0x03 /* Read Data Bytes */ #define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ #define CMD_W25_PP 0x02 /* Page Program */ @@ -32,9 +35,46 @@ uint8_t pages_per_sector_shift : 4; uint8_t sectors_per_block_shift : 4; uint8_t nr_blocks_shift; + uint8_t bp_bits : 3; + uint8_t protection_granularity_shift : 5; char name[10]; }; +union status_reg1_bp3 { + uint8_t u; + struct { + uint8_t busy : 1; + uint8_t wel : 1; + uint8_t bp : 3; + uint8_t tb : 1; + uint8_t sec : 1; + uint8_t srp0 : 1; + }; +}; + +union status_reg1_bp4 { + uint8_t u; + struct { + uint8_t busy : 1; + uint8_t wel : 1; + uint8_t bp : 4; + uint8_t tb : 1; + uint8_t srp0 : 1; + }; +}; + +union status_reg2 { + uint8_t u; + struct { + uint8_t srp1 : 1; + uint8_t qe : 1; + uint8_t res : 1; + uint8_t lb : 3; + uint8_t cmp : 1; + uint8_t sus : 1; + }; +}; + static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { { .id = 0x3015, @@ -75,6 +115,8 @@ .sectors_per_block_shift = 4, .nr_blocks_shift = 5, .name = "W25Q16", + .protection_granularity_shift = 16, + .bp_bits = 3, }, { .id = 0x4016, @@ -83,6 +125,8 @@ .sectors_per_block_shift = 4, .nr_blocks_shift = 6, .name = "W25Q32", + .protection_granularity_shift = 16, + .bp_bits = 3, }, { .id = 0x6016, @@ -91,6 +135,8 @@ .sectors_per_block_shift = 4, .nr_blocks_shift = 6, .name = "W25Q32DW", + .protection_granularity_shift = 16, + .bp_bits = 3, }, { .id = 0x4017, @@ -99,6 +145,8 @@ .sectors_per_block_shift = 4, .nr_blocks_shift = 7, .name = "W25Q64", + .protection_granularity_shift = 17, + .bp_bits = 3, }, { .id = 0x6017, @@ -107,6 +155,8 @@ .sectors_per_block_shift = 4, .nr_blocks_shift = 7, .name = "W25Q64DW", + .protection_granularity_shift = 17, + .bp_bits = 3, }, { .id = 0x4018, @@ -115,6 +165,8 @@ .sectors_per_block_shift = 4, .nr_blocks_shift = 8, .name = "W25Q128", + .protection_granularity_shift = 18, + .bp_bits = 3, }, { .id = 0x6018, @@ -123,6 +175,8 @@ .sectors_per_block_shift = 4, .nr_blocks_shift = 8, .name = "W25Q128FW", + .protection_granularity_shift = 18, + .bp_bits = 3, }, { .id = 0x4019, @@ -131,6 +185,8 @@ .sectors_per_block_shift = 4, .nr_blocks_shift = 9, .name = "W25Q256", + .protection_granularity_shift = 16, + .bp_bits = 4, }, }; @@ -191,6 +247,102 @@ return ret; } +/* + * Convert BPx, TB and CMP to a region. + * SEC (if available) must be zero. + */ +static void winbond_bpbits_to_region(const size_t granularity, + const u8 bp, + bool tb, + const bool cmp, + const size_t flash_size, + struct region *out) +{ + size_t protected_size = + min(bp ? granularity << (bp - 1) : 0, flash_size); + + if (cmp) { + protected_size = flash_size - protected_size; + tb = !tb; + } + + out->offset = tb ? flash_size - protected_size : 0; + out->size = protected_size; +} + +/* + * Available on all devices. + * Read block protect bits from Status/Status2 Reg. + * Converts block protection bits to a region. + * + * Returns: + * -1 on error + * 1 if region is covered by write protection + * 0 if a part of region isn't covered by write protection + */ +static int winbond_get_write_protection(const struct spi_flash *flash, + const struct region *region) +{ + const struct winbond_spi_flash_params *params; + struct region wp_region; + union status_reg2 reg2; + u8 bp, tb; + int ret; + + params = (const struct winbond_spi_flash_params *)flash->driver_private; + const size_t granularity = (1 << params->protection_granularity_shift); + + if (params->bp_bits == 3) { + union status_reg1_bp3 reg1_bp3; + + ret = spi_flash_cmd(&flash->spi, flash->status_cmd, &reg1_bp3.u, + sizeof(reg1_bp3.u)); + if (ret) + return ret; + + if (reg1_bp3.sec) { + // FIXME: not supported + return -1; + } + + bp = reg1_bp3.bp; + tb = reg1_bp3.tb; + } else if (params->bp_bits == 4) { + union status_reg1_bp4 reg1_bp4; + + ret = spi_flash_cmd(&flash->spi, flash->status_cmd, &reg1_bp4.u, + sizeof(reg1_bp4.u)); + if (ret) + return ret; + + bp = reg1_bp4.bp; + tb = reg1_bp4.tb; + } else { + // FIXME: not supported + return -1; + } + + ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR2, &reg2.u, + sizeof(reg2.u)); + if (ret) + return ret; + + winbond_bpbits_to_region(granularity, bp, tb, reg2.cmp, flash->size, + &wp_region); + + if (!reg2.srp1 || !wp_region.size) { + printk(BIOS_DEBUG, "WINBOND: flash isn't protected\n"); + + return 0; + } + + printk(BIOS_DEBUG, "WINBOND: flash protected range 0x%08zx-0x%08zx\n", + wp_region.offset, wp_region.size); + + return region_is_subregion(&wp_region, region); +} + + static const struct spi_flash_ops spi_flash_ops = { .write = winbond_write, .erase = spi_flash_cmd_erase, @@ -200,6 +352,7 @@ #else .read = spi_flash_cmd_read_fast, #endif + .get_write_protection = winbond_get_write_protection, }; int spi_flash_probe_winbond(const struct spi_slave *spi, u8 *idcode, @@ -234,6 +387,7 @@ flash->status_cmd = CMD_W25_RDSR; flash->ops = &spi_flash_ops; + flash->driver_private = params; return 0; } diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index f7f3b3d..9f8d2d0 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -40,6 +40,16 @@ const void *buf); int (*erase)(const struct spi_flash *flash, u32 offset, size_t len); int (*status)(const struct spi_flash *flash, u8 *reg); + /* + * Returns 1 if the whole region is software write protected. + * Hardware write protection mechanism aren't accounted. + * If the write protection could be changed, due to unlocked status + * register for example, 0 should be returned. + * Returns -1 on error. + */ + int (*get_write_protection)(const struct spi_flash *flash, + const struct region *region); + }; struct spi_flash { @@ -51,6 +61,7 @@ u8 erase_cmd; u8 status_cmd; const struct spi_flash_ops *ops; + const void *driver_private; }; void lb_spi_flash(struct lb_header *header); @@ -93,6 +104,21 @@ const void *buf); int spi_flash_erase(const struct spi_flash *flash, u32 offset, size_t len); int spi_flash_status(const struct spi_flash *flash, u8 *reg); + +/* + * Return the vendor dependent SPI flash write protection state. + * @param flash : A SPI flash device + * @param region: A subregion of the device's region + * + * Returns: + * -1 on error + * 0 if the device doesn't support block protection + * 0 if the device doesn't enable block protection + * 0 if given range isn't covered by block protection + * 1 if given range is covered by block protection + */ +int spi_flash_is_write_protected(const struct spi_flash *flash, + const struct region *region); /* * Some SPI controllers require exclusive access to SPI flash when volatile * operations like erase or write are being performed. In such cases, -- To view, visit https://review.coreboot.org/25082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5 Gerrit-Change-Number: 25082 Gerrit-PatchSet: 21 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: README: Convert to Markdown
by Philipp Deppenwiese (Code Review) 16 Sep '18

16 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28624 ) Change subject: README: Convert to Markdown ...................................................................... README: Convert to Markdown Markdown allows easy conversion to HTML, so this change should make the GitHub mirror look a little better. Change-Id: I1a9fde648b8960c01b69fc682f0908c5243d2013 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/28624 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- R README.md 1 file changed, 10 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/README b/README.md similarity index 80% rename from README rename to README.md index 651aa61..b13ace5 100644 --- a/README +++ b/README.md @@ -1,6 +1,5 @@ -------------------------------------------------------------------------------- coreboot README -------------------------------------------------------------------------------- +=============== coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of @@ -24,7 +23,7 @@ After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. -See https://www.coreboot.org/Payloads for a list of supported payloads. +See <https://www.coreboot.org/Payloads> for a list of supported payloads. Supported Hardware @@ -34,8 +33,8 @@ For details please consult: - * https://www.coreboot.org/Supported_Motherboards - * https://www.coreboot.org/Supported_Chipsets_and_Devices + * <https://www.coreboot.org/Supported_Motherboards> + * <https://www.coreboot.org/Supported_Chipsets_and_Devices> Build Requirements @@ -48,7 +47,7 @@ to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the - ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this + `ANY_TOOLCHAIN` Kconfig option if you're feeling lucky (no support in this case). * iasl (for targets with ACPI support) * pkg-config @@ -58,14 +57,14 @@ * doxygen (for generating/viewing documentation) * gdb (for better debugging facilities on some targets) - * ncurses (for 'make menuconfig' and 'make nconfig') + * ncurses (for `make menuconfig` and `make nconfig`) * flex and bison (for regenerating parsers) Building coreboot ----------------- -Please consult https://www.coreboot.org/Build_HOWTO for details. +Please consult <https://www.coreboot.org/Build_HOWTO> for details. Testing coreboot Without Modifying Your Hardware @@ -75,7 +74,7 @@ to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. -Please see https://www.coreboot.org/QEMU for details. +Please see <https://www.coreboot.org/QEMU> for details. Website and Mailing List @@ -84,11 +83,11 @@ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: - https://www.coreboot.org + <https://www.coreboot.org> You can contact us directly on the coreboot mailing list: - https://www.coreboot.org/Mailinglist + <https://www.coreboot.org/Mailinglist> Copyright and License -- To view, visit https://review.coreboot.org/28624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I1a9fde648b8960c01b69fc682f0908c5243d2013 Gerrit-Change-Number: 28624 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Documentation/mb/intel/sandybridge/nri: Change column name to "Comments"
by Patrick Rudolph (Code Review) 16 Sep '18

16 Sep '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28625 ) Change subject: Documentation/mb/intel/sandybridge/nri: Change column name to "Comments" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I714972ee336bc1f8a4feb75292ee9efa583f0bb1 Gerrit-Change-Number: 28625 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 16 Sep 2018 12:58:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Felix Held (Code Review) 16 Sep '18

16 Sep '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28596 ) Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/28596/5/src/mainboard/asrock/g41c-gs/gpio.c File src/mainboard/asrock/g41c-gs/gpio.c: https://review.coreboot.org/#/c/28596/5/src/mainboard/asrock/g41c-gs/gpio.c… PS5, Line 75: #if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0) : .gpio8 = GPIO_LEVEL_LOW, : .gpio9 = GPIO_LEVEL_LOW, : #endif this IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0) is always false, since it's inside the IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) block and only one board is or at least should be selected at a time -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 16 Sep 2018 10:59:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Add support for Sunsetrise Point LP to inteltool
by Felix Held (Code Review) 16 Sep '18

16 Sep '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28623 ) Change subject: Add support for Sunsetrise Point LP to inteltool ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28623/1/util/inteltool/inteltool.h File util/inteltool/inteltool.h: https://review.coreboot.org/#/c/28623/1/util/inteltool/inteltool.h@148 PS1, Line 148: SUNRISEPOINT_LP the device name in the datasheet is "PCH-U with iHDCP 2.2 Premium", so just SUNRISEPOINT_LP isn't specific enough. See https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th… page 23. Would also be good if you add all PCI IDs of the LPC controllers of the PCH SKUs. The PCI ID of the LPC controller is the way to identify the different SKUs. Maybe also try to coordinate the patch with #28618 -- To view, visit https://review.coreboot.org/28623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Gerrit-Change-Number: 28623 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 16 Sep 2018 10:48:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/inteltool: Add Sunrise Point LP
by Felix Held (Code Review) 16 Sep '18

16 Sep '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28618 ) Change subject: util/inteltool: Add Sunrise Point LP ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/28618/5/util/inteltool/inteltool.h File util/inteltool/inteltool.h: https://review.coreboot.org/#/c/28618/5/util/inteltool/inteltool.h@144 PS5, Line 144: PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP > 0x9d58 should be KabyLake. […] Yep, that PCI ID is the LPC controller of 7 series (Kabylake) PCH-U Premium. See https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th… page 23 vs. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/6th… page 28. Would be good if you'd add support for those different SKUs -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 5 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 16 Sep 2018 10:36:22 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Documentation/mb/intel/sandybridge/nri: Change column name to "Comments"
by Jonathan Neuschäfer (Code Review) 16 Sep '18

16 Sep '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28625 Change subject: Documentation/mb/intel/sandybridge/nri: Change column name to "Comments" ...................................................................... Documentation/mb/intel/sandybridge/nri: Change column name to "Comments" This column doesn't really contain a description, but additional comments. Change-Id: I714972ee336bc1f8a4feb75292ee9efa583f0bb1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/northbridge/intel/sandybridge/nri_features.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/28625/1 diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md index 6305e78..51297bd 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_features.md +++ b/Documentation/northbridge/intel/sandybridge/nri_features.md @@ -16,7 +16,7 @@ ```eval_rst +---------------------------+----------------------+-------------+---------+---------------------+ -| Option | Supported | Implemented | Working | Description | +| Option | Supported | Implemented | Working | Comments | +===========================+======================+=============+=========+=====================+ | **Supported channels** | +---------------------------+----------------------+-------------+---------+---------------------+ -- To view, visit https://review.coreboot.org/28625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I714972ee336bc1f8a4feb75292ee9efa583f0bb1 Gerrit-Change-Number: 28625 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: README: Convert to Markdown
by Jonathan Neuschäfer (Code Review) 16 Sep '18

16 Sep '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28624 Change subject: README: Convert to Markdown ...................................................................... README: Convert to Markdown Markdown allows easy conversion to HTML, so this change should make the GitHub mirror look a little better. Change-Id: I1a9fde648b8960c01b69fc682f0908c5243d2013 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- R README.md 1 file changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28624/1 diff --git a/README b/README.md similarity index 80% rename from README rename to README.md index 651aa61..b13ace5 100644 --- a/README +++ b/README.md @@ -1,6 +1,5 @@ -------------------------------------------------------------------------------- coreboot README -------------------------------------------------------------------------------- +=============== coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of @@ -24,7 +23,7 @@ After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. -See https://www.coreboot.org/Payloads for a list of supported payloads. +See <https://www.coreboot.org/Payloads> for a list of supported payloads. Supported Hardware @@ -34,8 +33,8 @@ For details please consult: - * https://www.coreboot.org/Supported_Motherboards - * https://www.coreboot.org/Supported_Chipsets_and_Devices + * <https://www.coreboot.org/Supported_Motherboards> + * <https://www.coreboot.org/Supported_Chipsets_and_Devices> Build Requirements @@ -48,7 +47,7 @@ to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the - ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this + `ANY_TOOLCHAIN` Kconfig option if you're feeling lucky (no support in this case). * iasl (for targets with ACPI support) * pkg-config @@ -58,14 +57,14 @@ * doxygen (for generating/viewing documentation) * gdb (for better debugging facilities on some targets) - * ncurses (for 'make menuconfig' and 'make nconfig') + * ncurses (for `make menuconfig` and `make nconfig`) * flex and bison (for regenerating parsers) Building coreboot ----------------- -Please consult https://www.coreboot.org/Build_HOWTO for details. +Please consult <https://www.coreboot.org/Build_HOWTO> for details. Testing coreboot Without Modifying Your Hardware @@ -75,7 +74,7 @@ to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. -Please see https://www.coreboot.org/QEMU for details. +Please see <https://www.coreboot.org/QEMU> for details. Website and Mailing List @@ -84,11 +83,11 @@ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: - https://www.coreboot.org + <https://www.coreboot.org> You can contact us directly on the coreboot mailing list: - https://www.coreboot.org/Mailinglist + <https://www.coreboot.org/Mailinglist> Copyright and License -- To view, visit https://review.coreboot.org/28624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1a9fde648b8960c01b69fc682f0908c5243d2013 Gerrit-Change-Number: 28624 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: util/inteltool: Add Sunrise Point LP
by Johanna Schander (Code Review) 16 Sep '18

16 Sep '18

Johanna Schander has posted comments on this change. ( https://review.coreboot.org/28618 ) Change subject: util/inteltool: Add Sunrise Point LP ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/28618/5/util/inteltool/inteltool.h File util/inteltool/inteltool.h: https://review.coreboot.org/#/c/28618/5/util/inteltool/inteltool.h@144 PS5, Line 144: PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP 0x9d58 should be KabyLake. Can you provide source, if you are sure? -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 5 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 16 Sep 2018 00:31:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Makefile.inc: Fix dependency tracking of fmap{_config.h, .desc}
by Alex Thiessen (Code Review) 15 Sep '18

15 Sep '18

Alex Thiessen has posted comments on this change. ( https://review.coreboot.org/28198 ) Change subject: Makefile.inc: Fix dependency tracking of fmap{_config.h,.desc} ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > The code looks quite strange and in fact, these are false dependencies. If you e.g. `touch fmap.fmap`, `make` will call `true` in an attempt to update `fmap_config.h`, every time without real success. > > > > If you have a recipe like the one for `fmap.fmap` that builds a number of targets, then the right thing to do is to define multiple targets in the rule: https://www.gnu.org/software/make/manual/html_node/Multiple-Targets.html > > > > Feel free to update the fix :) > > well, don't touch fmap.fmap then :) > > The problem with multiple targets in make is that it's just a shorthand: > > a b c: d > foo > > means that it call foo to generate a, call foo to generate b, and call foo to generate c. in a parallelized build, it will even call them in parallel, which means you have three processes trying to write to the same three files at the same time - which might or might not work out well (nevermind the additional build load) You're right, guess I forgot to think about that. But then, order-only dependencies should do the job. It would be a nice exercise to make the build interlock for the three files, to get rid of these dependency games altogether. -- To view, visit https://review.coreboot.org/28198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic7ecb88cf7df7f2488defd47ea02255fc10a67e9 Gerrit-Change-Number: 28198 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 15 Sep 2018 16:18:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit September 2018