coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

1 participants
886 discussions

Change in coreboot[master]: mb/lenovo/t400: Link the gpio.c settings
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28628 to look at the new patch set (#3). Change subject: mb/lenovo/t400: Link the gpio.c settings ...................................................................... mb/lenovo/t400: Link the gpio.c settings Linking this file instead of including a header makes it possible to easily change gpio settings for a variant. Change-Id: Ifd496510d4868f5901a9dbbf7f1523ccffaf15ab Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/Makefile.inc R src/mainboard/lenovo/t400/gpio.c M src/mainboard/lenovo/t400/romstage.c 3 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/28628/3 -- To view, visit https://review.coreboot.org/28628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifd496510d4868f5901a9dbbf7f1523ccffaf15ab Gerrit-Change-Number: 28628 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/lenovo/x200: Use lower C-states on battery
by build bot (Jenkins) (Code Review) 16 Sep '18

16 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22932 ) Change subject: mb/lenovo/x200: Use lower C-states on battery ...................................................................... Patch Set 11: (3 comments) https://review.coreboot.org/#/c/22932/11/src/arch/x86/include/arch/acpigen.h File src/arch/x86/include/arch/acpigen.h: https://review.coreboot.org/#/c/22932/11/src/arch/x86/include/arch/acpigen.… PS11, Line 354: int get_bat_cst_entries(acpi_cstate_t **); function definition argument 'acpi_cstate_t **' should also have an identifier name https://review.coreboot.org/#/c/22932/11/src/cpu/intel/speedstep/acpi.c File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/#/c/22932/11/src/cpu/intel/speedstep/acpi.c@182 PS11, Line 182: generate_C_state_entries(cstates, num_cstates); code indent should use tabs where possible https://review.coreboot.org/#/c/22932/11/src/cpu/intel/speedstep/acpi.c@187 PS11, Line 187: num_bat_cstates); line over 80 characters -- To view, visit https://review.coreboot.org/22932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Gerrit-Change-Number: 22932 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 16 Sep 2018 14:42:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/lenovo/Thinkpad{T500, R400, W500}: Unify under T400
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28626 to look at the new patch set (#2). Change subject: mb/lenovo/Thinkpad{T500, R400, W500}: Unify under T400 ...................................................................... mb/lenovo/Thinkpad{T500, R400, W500}: Unify under T400 A negative side-effect is that those boards disappear from the board-status output, but this is an issue on all variants. Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/lenovo/r400/Kconfig D src/mainboard/lenovo/r400/Kconfig.name D src/mainboard/lenovo/r400/board_info.txt M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/Kconfig.name D src/mainboard/lenovo/t500/Kconfig D src/mainboard/lenovo/t500/Kconfig.name D src/mainboard/lenovo/t500/board_info.txt D src/mainboard/lenovo/w500/Kconfig D src/mainboard/lenovo/w500/Kconfig.name D src/mainboard/lenovo/w500/board_info.txt 11 files changed, 15 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/28626/2 -- To view, visit https://review.coreboot.org/28626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c Gerrit-Change-Number: 28626 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/lenovo/t400: Trim down the gpio.h file
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28627 Change subject: mb/lenovo/t400: Trim down the gpio.h file ...................................................................... mb/lenovo/t400: Trim down the gpio.h file Some settings like direction are only used if the mode is GPIO. Change-Id: I4efc54dfef3721b528b90d49f490014d9132cdf8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/gpio.h 1 file changed, 20 insertions(+), 201 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/28627/1 diff --git a/src/mainboard/lenovo/t400/gpio.h b/src/mainboard/lenovo/t400/gpio.h index 6757c94..261c912 100644 --- a/src/mainboard/lenovo/t400/gpio.h +++ b/src/mainboard/lenovo/t400/gpio.h @@ -16,8 +16,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NATIVE, +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -27,273 +26,93 @@ .gpio7 = GPIO_MODE_GPIO, .gpio8 = GPIO_MODE_GPIO, .gpio9 = GPIO_MODE_GPIO, - .gpio10 = GPIO_MODE_NATIVE, - .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_NATIVE, .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, - .gpio15 = GPIO_MODE_NATIVE, - .gpio16 = GPIO_MODE_NATIVE, .gpio17 = GPIO_MODE_GPIO, .gpio18 = GPIO_MODE_GPIO, .gpio19 = GPIO_MODE_GPIO, .gpio20 = GPIO_MODE_GPIO, .gpio21 = GPIO_MODE_GPIO, .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_NATIVE, .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_NATIVE, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_OUTPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_OUTPUT, +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_OUTPUT, - .gpio16 = GPIO_DIR_OUTPUT, .gpio17 = GPIO_DIR_INPUT, .gpio18 = GPIO_DIR_INPUT, .gpio19 = GPIO_DIR_OUTPUT, .gpio20 = GPIO_DIR_OUTPUT, .gpio21 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_OUTPUT, - .gpio26 = GPIO_DIR_OUTPUT, .gpio27 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_HIGH, - .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_HIGH, - .gpio9 = GPIO_LEVEL_HIGH, - .gpio10 = GPIO_LEVEL_HIGH, - .gpio11 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_HIGH, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_LOW, +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, .gpio19 = GPIO_LEVEL_HIGH, .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_HIGH, .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_HIGH, - .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { - .gpio0 = GPIO_NO_BLINK, - .gpio1 = GPIO_NO_BLINK, - .gpio2 = GPIO_NO_BLINK, - .gpio3 = GPIO_NO_BLINK, - .gpio4 = GPIO_NO_BLINK, - .gpio5 = GPIO_NO_BLINK, - .gpio6 = GPIO_NO_BLINK, - .gpio7 = GPIO_NO_BLINK, - .gpio8 = GPIO_NO_BLINK, - .gpio9 = GPIO_NO_BLINK, - .gpio10 = GPIO_NO_BLINK, - .gpio11 = GPIO_NO_BLINK, - .gpio12 = GPIO_NO_BLINK, - .gpio13 = GPIO_NO_BLINK, - .gpio14 = GPIO_NO_BLINK, - .gpio15 = GPIO_NO_BLINK, - .gpio16 = GPIO_NO_BLINK, - .gpio17 = GPIO_NO_BLINK, - .gpio18 = GPIO_NO_BLINK, - .gpio19 = GPIO_NO_BLINK, - .gpio20 = GPIO_NO_BLINK, - .gpio21 = GPIO_NO_BLINK, - .gpio22 = GPIO_NO_BLINK, - .gpio23 = GPIO_NO_BLINK, - .gpio24 = GPIO_NO_BLINK, - .gpio25 = GPIO_NO_BLINK, - .gpio26 = GPIO_NO_BLINK, - .gpio27 = GPIO_NO_BLINK, - .gpio28 = GPIO_NO_BLINK, - .gpio29 = GPIO_NO_BLINK, - .gpio30 = GPIO_NO_BLINK, - .gpio31 = GPIO_NO_BLINK, +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio0 = GPIO_NO_INVERT, - .gpio1 = GPIO_INVERT, - .gpio2 = GPIO_NO_INVERT, - .gpio3 = GPIO_NO_INVERT, - .gpio4 = GPIO_NO_INVERT, - .gpio5 = GPIO_NO_INVERT, - .gpio6 = GPIO_NO_INVERT, - .gpio7 = GPIO_NO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio9 = GPIO_NO_INVERT, - .gpio10 = GPIO_NO_INVERT, - .gpio11 = GPIO_NO_INVERT, - .gpio12 = GPIO_NO_INVERT, - .gpio13 = GPIO_NO_INVERT, - .gpio14 = GPIO_NO_INVERT, - .gpio15 = GPIO_NO_INVERT, - .gpio16 = GPIO_NO_INVERT, - .gpio17 = GPIO_NO_INVERT, - .gpio18 = GPIO_NO_INVERT, - .gpio19 = GPIO_NO_INVERT, - .gpio20 = GPIO_NO_INVERT, - .gpio21 = GPIO_NO_INVERT, - .gpio22 = GPIO_NO_INVERT, - .gpio23 = GPIO_NO_INVERT, - .gpio24 = GPIO_NO_INVERT, - .gpio25 = GPIO_NO_INVERT, - .gpio26 = GPIO_NO_INVERT, - .gpio27 = GPIO_NO_INVERT, - .gpio28 = GPIO_NO_INVERT, - .gpio29 = GPIO_NO_INVERT, - .gpio30 = GPIO_NO_INVERT, - .gpio31 = GPIO_NO_INVERT, +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_NATIVE, .gpio36 = GPIO_MODE_GPIO, .gpio37 = GPIO_MODE_GPIO, .gpio38 = GPIO_MODE_GPIO, .gpio39 = GPIO_MODE_GPIO, - .gpio40 = GPIO_MODE_NATIVE, .gpio41 = GPIO_MODE_GPIO, .gpio42 = GPIO_MODE_GPIO, - .gpio43 = GPIO_MODE_NATIVE, - .gpio44 = GPIO_MODE_NATIVE, - .gpio45 = GPIO_MODE_NATIVE, - .gpio46 = GPIO_MODE_NATIVE, - .gpio47 = GPIO_MODE_NATIVE, .gpio48 = GPIO_MODE_GPIO, .gpio49 = GPIO_MODE_GPIO, - .gpio50 = GPIO_MODE_NATIVE, - .gpio51 = GPIO_MODE_NATIVE, - .gpio52 = GPIO_MODE_NATIVE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NATIVE, - .gpio55 = GPIO_MODE_NATIVE, .gpio56 = GPIO_MODE_GPIO, .gpio57 = GPIO_MODE_GPIO, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_NATIVE, - .gpio61 = GPIO_MODE_NATIVE, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, .gpio38 = GPIO_DIR_INPUT, .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, .gpio41 = GPIO_DIR_OUTPUT, .gpio42 = GPIO_DIR_OUTPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio47 = GPIO_DIR_INPUT, .gpio48 = GPIO_DIR_INPUT, .gpio49 = GPIO_DIR_OUTPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_OUTPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_OUTPUT, .gpio56 = GPIO_DIR_INPUT, .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_INPUT, - .gpio61 = GPIO_DIR_OUTPUT, - .gpio62 = GPIO_DIR_OUTPUT, - .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_HIGH, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, .gpio41 = GPIO_LEVEL_HIGH, .gpio42 = GPIO_LEVEL_HIGH, - .gpio43 = GPIO_LEVEL_HIGH, - .gpio44 = GPIO_LEVEL_HIGH, - .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, - .gpio47 = GPIO_LEVEL_HIGH, - .gpio48 = GPIO_LEVEL_HIGH, .gpio49 = GPIO_LEVEL_HIGH, - .gpio50 = GPIO_LEVEL_HIGH, - .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_HIGH, - .gpio55 = GPIO_LEVEL_HIGH, - .gpio56 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_HIGH, - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, }; const struct pch_gpio_map t400_gpio_map = { -- To view, visit https://review.coreboot.org/28627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4efc54dfef3721b528b90d49f490014d9132cdf8 Gerrit-Change-Number: 28627 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: mb/lenovo/t400: Link the gpio.c settings
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28628 Change subject: mb/lenovo/t400: Link the gpio.c settings ...................................................................... mb/lenovo/t400: Link the gpio.c settings Linking this file instead of including a header makes it possible to easily change gpio settings for a variant. Change-Id: Ifd496510d4868f5901a9dbbf7f1523ccffaf15ab Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/Makefile.inc R src/mainboard/lenovo/t400/gpio.c M src/mainboard/lenovo/t400/romstage.c 3 files changed, 5 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/28628/1 diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index 62e27d3..7721e03 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c romstage-y += dock.c ramstage-y += dock.c diff --git a/src/mainboard/lenovo/t400/gpio.h b/src/mainboard/lenovo/t400/gpio.c similarity index 96% rename from src/mainboard/lenovo/t400/gpio.h rename to src/mainboard/lenovo/t400/gpio.c index 261c912..ef340f2 100644 --- a/src/mainboard/lenovo/t400/gpio.h +++ b/src/mainboard/lenovo/t400/gpio.c @@ -11,9 +11,6 @@ * GNU General Public License for more details. */ -#ifndef LENOVO_T400_GPIO_H -#define LENOVO_T400_GPIO_H - #include <southbridge/intel/common/gpio.h> static const struct pch_gpio_set1 pch_gpio_set1_mode = { @@ -115,7 +112,7 @@ .gpio49 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_map t400_gpio_map = { +const struct pch_gpio_map mainboard_gpio_map = { .set1 = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, @@ -129,5 +126,3 @@ .level = &pch_gpio_set2_level, }, }; - -#endif diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 1974ab6..c66dacb 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -27,12 +27,12 @@ #include <lib.h> #include <romstage_handoff.h> #include <console/console.h> -#include <southbridge/intel/i82801ix/i82801ix.h> +#include <southbridge/intel/i82801ix/i82801ix.h +#include <southbridge/intel/common/gpio.h> #include <northbridge/intel/gm45/gm45.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <timestamp.h> #include "dock.h" -#include "gpio.h" #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) @@ -93,7 +93,7 @@ gm45_early_reset(); } - setup_pch_gpios(&t400_gpio_map); + setup_pch_gpios(&mainboard_gpio_map); /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); -- To view, visit https://review.coreboot.org/28628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd496510d4868f5901a9dbbf7f1523ccffaf15ab Gerrit-Change-Number: 28628 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: mb/lenovo/Thinkpad{T500, R400, W500}: Unify under T400
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28626 Change subject: mb/lenovo/Thinkpad{T500, R400, W500}: Unify under T400 ...................................................................... mb/lenovo/Thinkpad{T500, R400, W500}: Unify under T400 A negative side-effect is that those boards disappear from the board-status output, but this is an issue on all variants. Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/lenovo/r400/Kconfig D src/mainboard/lenovo/r400/Kconfig.name D src/mainboard/lenovo/r400/board_info.txt M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/Kconfig.name D src/mainboard/lenovo/t500/Kconfig D src/mainboard/lenovo/t500/Kconfig.name D src/mainboard/lenovo/t500/board_info.txt D src/mainboard/lenovo/w500/Kconfig D src/mainboard/lenovo/w500/Kconfig.name D src/mainboard/lenovo/w500/board_info.txt 11 files changed, 13 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/28626/1 diff --git a/src/mainboard/lenovo/r400/Kconfig b/src/mainboard/lenovo/r400/Kconfig deleted file mode 100644 index 0966bf1..0000000 --- a/src/mainboard/lenovo/r400/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if BOARD_LENOVO_R400 - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad R400" - -endif diff --git a/src/mainboard/lenovo/r400/Kconfig.name b/src/mainboard/lenovo/r400/Kconfig.name deleted file mode 100644 index 15a99b1..0000000 --- a/src/mainboard/lenovo/r400/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_R400 - bool "ThinkPad R400" diff --git a/src/mainboard/lenovo/r400/board_info.txt b/src/mainboard/lenovo/r400/board_info.txt deleted file mode 100644 index 007ec6c..0000000 --- a/src/mainboard/lenovo/r400/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: laptop -ROM package: SOIC-16 or SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Clone of: lenovo/t400 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index bea8737..ddd3c5c 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -28,13 +28,12 @@ string default lenovo/t400 -if BOARD_LENOVO_T400 - config MAINBOARD_PART_NUMBER string - default "ThinkPad T400" - -endif + default "ThinkPad T400" if BOARD_LENOVO_T400 + default "ThinkPad T500" if BOARD_LENOVO_T500 + default "ThinkPad R400" if BOARD_LENOVO_R400 + default "ThinkPad W500" if BOARD_LENOVO_W500 config USBDEBUG_HCD_INDEX int diff --git a/src/mainboard/lenovo/t400/Kconfig.name b/src/mainboard/lenovo/t400/Kconfig.name index 56a575e..364de37 100644 --- a/src/mainboard/lenovo/t400/Kconfig.name +++ b/src/mainboard/lenovo/t400/Kconfig.name @@ -1,2 +1,11 @@ config BOARD_LENOVO_T400 bool "ThinkPad T400" + +config BOARD_LENOVO_T500 + bool "ThinkPad T500" + +config BOARD_LENOVO_W500 + bool "ThinkPad R400" + +config BOARD_LENOVO_W500 + bool "ThinkPad W500" diff --git a/src/mainboard/lenovo/t500/Kconfig b/src/mainboard/lenovo/t500/Kconfig deleted file mode 100644 index e1e8420..0000000 --- a/src/mainboard/lenovo/t500/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if BOARD_LENOVO_T500 - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad T500" - -endif diff --git a/src/mainboard/lenovo/t500/Kconfig.name b/src/mainboard/lenovo/t500/Kconfig.name deleted file mode 100644 index 89c6087..0000000 --- a/src/mainboard/lenovo/t500/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_T500 - bool "ThinkPad T500" diff --git a/src/mainboard/lenovo/t500/board_info.txt b/src/mainboard/lenovo/t500/board_info.txt deleted file mode 100644 index 007ec6c..0000000 --- a/src/mainboard/lenovo/t500/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: laptop -ROM package: SOIC-16 or SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Clone of: lenovo/t400 diff --git a/src/mainboard/lenovo/w500/Kconfig b/src/mainboard/lenovo/w500/Kconfig deleted file mode 100644 index e9ee3ad..0000000 --- a/src/mainboard/lenovo/w500/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if BOARD_LENOVO_W500 - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad W500" - -endif diff --git a/src/mainboard/lenovo/w500/Kconfig.name b/src/mainboard/lenovo/w500/Kconfig.name deleted file mode 100644 index 2097b77..0000000 --- a/src/mainboard/lenovo/w500/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_W500 - bool "ThinkPad W500" diff --git a/src/mainboard/lenovo/w500/board_info.txt b/src/mainboard/lenovo/w500/board_info.txt deleted file mode 100644 index 007ec6c..0000000 --- a/src/mainboard/lenovo/w500/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: laptop -ROM package: SOIC-16 or SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Clone of: lenovo/t400 -- To view, visit https://review.coreboot.org/28626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c Gerrit-Change-Number: 28626 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/28596 ) Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/28596/5/src/mainboard/asrock/g41c-gs/gpio.c File src/mainboard/asrock/g41c-gs/gpio.c: https://review.coreboot.org/#/c/28596/5/src/mainboard/asrock/g41c-gs/gpio.c… PS5, Line 75: #if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0) : .gpio8 = GPIO_LEVEL_LOW, : .gpio9 = GPIO_LEVEL_LOW, : #endif > this IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0) is always false, since it's inside the IS_ENABLED […] This file is becoming a mess. I'll just link them separately, while removing the preprocessor statements I think... -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 16 Sep 2018 14:02:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: payloads/external: Add yabits payload
by Philipp Deppenwiese (Code Review) 16 Sep '18

16 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28590 ) Change subject: payloads/external: Add yabits payload ...................................................................... payloads/external: Add yabits payload Yabits (Yet another UEFI bootloader) is designed to be a slim and quick alternative to Tianocore. It is still under heavy development. https://web.archive.org/web/https://yabits.github.io/ Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899 Signed-off-by: Martin Roth <martin(a)coreboot.org> Reviewed-on: https://review.coreboot.org/28590 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> --- M payloads/Makefile.inc M payloads/external/Makefile.inc A payloads/external/Yabits/Kconfig A payloads/external/Yabits/Kconfig.name A payloads/external/Yabits/Makefile 5 files changed, 140 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Marc Jones: Looks good to me, approved diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index 0d142d6..83d3910 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -36,6 +36,7 @@ payloads/external/tianocore \ payloads/external/GRUB2 \ payloads/external/LinuxBoot \ +payloads/external/Yabits \ payloads/coreinfo/build/coreinfo.elf coreinfo: $(MAKE) -C payloads/coreinfo defaultbuild diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index e4d6d4f..c730bba 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -283,3 +283,15 @@ payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz: linuxboot payloads/external/LinuxBoot/linuxboot/kernel/.config: linuxboot payloads/external/LinuxBoot/linuxboot/go/src/github.com/u-root/u-root/.git: linuxboot + +payloads/external/Yabits/uefi/build/uefi.elf yabits: + $(MAKE) -C payloads/external/Yabits all \ + CC="$(CC_x86_32)" \ + LD="$(LD_x86_32)" \ + OBJCOPY="$(OBJCOPY_x86_32)" \ + AS="$(AS_x86_32)" \ + CONFIG_YABITS_REVISION=$(CONFIG_YABITS_REVISION) \ + CONFIG_YABITS_REVISION_ID=$(CONFIG_YABITS_REVISION_ID) \ + CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \ + CONFIG_YABITS_STABLE=$(CONFIG_YABITS_STABLE) \ + MFLAGS= MAKEFLAGS= diff --git a/payloads/external/Yabits/Kconfig b/payloads/external/Yabits/Kconfig new file mode 100644 index 0000000..cd1ade8 --- /dev/null +++ b/payloads/external/Yabits/Kconfig @@ -0,0 +1,47 @@ +if PAYLOAD_YABITS + +choice + prompt "Yabits version" + default YABITS_STABLE + +config YABITS_STABLE + bool "Stable" + help + Stable Yabits version. + + For reproducible builds, this option must be selected. + +config YABITS_MASTER + bool "Master" + help + Newest version. + + This option will fetch the newest version of the Yabits code, + updating as new changes are committed. This makes the build + non-reproducible, as it can fetch different code each time. + +config YABITS_REVISION + bool "git revision" + help + Select this option if you have a specific commit or branch + that you want to use as the revision from which to + build Yabits. Using a branch name makes the build + non-reproducible, as it can fetch different code as the + branch changes. + + You will be able to specify the name of a branch or a commit id + later. + +endchoice + +config YABITS_REVISION_ID + string "Insert a commit's SHA-1 or a branch name" + depends on YABITS_REVISION + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. + +config PAYLOAD_FILE + default "payloads/external/Yabits/uefi/build/uefi.elf" + +endif diff --git a/payloads/external/Yabits/Kconfig.name b/payloads/external/Yabits/Kconfig.name new file mode 100644 index 0000000..84f860f --- /dev/null +++ b/payloads/external/Yabits/Kconfig.name @@ -0,0 +1,11 @@ +config PAYLOAD_YABITS + bool "Yabits - Yet another UEFI Bootloader (Under Development)" + depends on ARCH_X86 + help + Yabits - yabits.github.io + yabits is a pure UEFI coreboot payload. Compared with + TianoCore, it is fast and lightweight. yabits is based on the + part of Minoca OS. It can run GRUB2, Linux, OpenBSD, and other + UEFI applications. + + It is still under the development and not ready for production. diff --git a/payloads/external/Yabits/Makefile b/payloads/external/Yabits/Makefile new file mode 100644 index 0000000..ec3c9c5 --- /dev/null +++ b/payloads/external/Yabits/Makefile @@ -0,0 +1,69 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +TAG-$(CONFIG_YABITS_MASTER)=origin/master +NAME-$(CONFIG_YABITS_MASTER)=Master +TAG-$(CONFIG_YABITS_STABLE)=d25abb067431dee9af9f8a874a209730ab7f0e91 +NAME-$(CONFIG_YABITS_STABLE)=Stable +TAG-$(CONFIG_YABITS_REVISION)=$(CONFIG_YABITS_REVISION_ID) + +project_name=Yabits +project_dir=$(CURDIR)/uefi +project_git_repo=https://github.com/yabits/uefi.git +LIBCONFIG_PATH="../../../libpayload" + +all: build + +$(project_dir): + echo " Cloning $(project_name) from Git" + git clone $(project_git_repo) $(project_dir) + +fetch: $(project_dir) +ifeq ($(TAG-y),) + echo "Error: The specified tag is invalid" +ifeq ($(CONFIG_YABITS_REVISION),y) + echo "Error: There is no revision specified for $(project_name)" + false +endif + false +endif + -cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \ + if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \ + echo " Fetching new commits from the $(project_name) git repo"; \ + git fetch; fi + +checkout: fetch + echo " Checking out $(project_name) revision $(NAME-y) ($(TAG-y))" + cd $(project_dir); \ + git checkout master; \ + git branch -D coreboot 2>/dev/null; \ + git checkout -b coreboot $(TAG-y) + +build: checkout + echo " MAKE $(project_name) $(NAME-y)" + $(if $(wildcard uefi/.xcompile),,$(shell bash ../../../util/xcompile/xcompile > uefi/.xcompile)) + $(MAKE) -C $(project_dir) defconfig LIBCONFIG_PATH=$(LIBCONFIG_PATH) XGCC=$(XGCCPATH) + $(MAKE) -C $(project_dir) all LIBCONFIG_PATH=$(LIBCONFIG_PATH) XGCC=$(XGCCPATH) + +clean: + test -d $(project_dir) && $(MAKE) -C $(project_dir) clean LIBCONFIG_PATH=$(LIBCONFIG_PATH) XGCC=$(XGCCPATH) || exit 0 + +distclean: + rm -rf $(project_dir) + +print-repo-info: + echo "$(project_git_repo) $(project_dir)" + +.PHONY: all build checkout clean distclean fetch print-repo-info -- To view, visit https://review.coreboot.org/28590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899 Gerrit-Change-Number: 28590 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: Documentation/mb/intel/sandybridge/nri: Change column name to "Comments"
by Philipp Deppenwiese (Code Review) 16 Sep '18

16 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28625 ) Change subject: Documentation/mb/intel/sandybridge/nri: Change column name to "Comments" ...................................................................... Documentation/mb/intel/sandybridge/nri: Change column name to "Comments" This column doesn't really contain a description, but additional comments. Change-Id: I714972ee336bc1f8a4feb75292ee9efa583f0bb1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/28625 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/northbridge/intel/sandybridge/nri_features.md 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md index 6305e78..51297bd 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_features.md +++ b/Documentation/northbridge/intel/sandybridge/nri_features.md @@ -16,7 +16,7 @@ ```eval_rst +---------------------------+----------------------+-------------+---------+---------------------+ -| Option | Supported | Implemented | Working | Description | +| Option | Supported | Implemented | Working | Comments | +===========================+======================+=============+=========+=====================+ | **Supported channels** | +---------------------------+----------------------+-------------+---------+---------------------+ -- To view, visit https://review.coreboot.org/28625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I714972ee336bc1f8a4feb75292ee9efa583f0bb1 Gerrit-Change-Number: 28625 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: configs: add sercon port and disable pxe serial console for apu{2, 3, 4, 5}
by Philipp Deppenwiese (Code Review) 16 Sep '18

16 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28616 ) Change subject: configs: add sercon port and disable pxe serial console for apu{2,3,4,5} ...................................................................... configs: add sercon port and disable pxe serial console for apu{2,3,4,5} To avoid mangled characters on serial output from iPXE we have to disable serial from iPXE console. More to that to have correct serial input we have to enable SeaBIOS SERCON option with default configuration. The only limitation of this configs is that apu5 doesn't detect iPXE - that platform is not for public use so it doesn't affect anyone. Change-Id: I124705bd691b3c8dcd9a2636b17c019d02732c5a Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/28616 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- A configs/config.pcengines_apu1 M configs/config.pcengines_apu2 A configs/config.pcengines_apu3 A configs/config.pcengines_apu4 A configs/config.pcengines_apu5 5 files changed, 48 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1 new file mode 100644 index 0000000..e511d65 --- /dev/null +++ b/configs/config.pcengines_apu1 @@ -0,0 +1,10 @@ +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_BOARD_PCENGINES_APU1=y +CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_PXE_ROM_ID="10ec,8168" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 index 2754024..08d4d4e 100644 --- a/configs/config.pcengines_apu2 +++ b/configs/config.pcengines_apu2 @@ -4,7 +4,9 @@ CONFIG_APU2_PINMUX_UART_C=y CONFIG_APU2_PINMUX_UART_D=y CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,157b" +# CONFIG_PXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 new file mode 100644 index 0000000..7acf014 --- /dev/null +++ b/configs/config.pcengines_apu3 @@ -0,0 +1,12 @@ +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_BOARD_PCENGINES_APU3=y +CONFIG_APU2_PINMUX_UART_C=y +CONFIG_APU2_PINMUX_UART_D=y +CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_PXE_ROM_ID="8086,1539" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 new file mode 100644 index 0000000..9e7ca5a --- /dev/null +++ b/configs/config.pcengines_apu4 @@ -0,0 +1,12 @@ +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_BOARD_PCENGINES_APU4=y +CONFIG_APU2_PINMUX_UART_C=y +CONFIG_APU2_PINMUX_UART_D=y +CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_PXE_ROM_ID="8086,1539" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 new file mode 100644 index 0000000..e5ddcee --- /dev/null +++ b/configs/config.pcengines_apu5 @@ -0,0 +1,12 @@ +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_BOARD_PCENGINES_APU5=y +CONFIG_APU2_PINMUX_UART_C=y +CONFIG_APU2_PINMUX_UART_D=y +CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_PXE_ROM_ID="8086,1539" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -- To view, visit https://review.coreboot.org/28616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I124705bd691b3c8dcd9a2636b17c019d02732c5a Gerrit-Change-Number: 28616 Gerrit-PatchSet: 2 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

← Newer
1
...
45
46
47
48
49
50
51
...
89
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2018