coreboot-gerrit September 2018

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Change in coreboot[master]: mb/asrock/g41c-gs: Link separate gpio.c files
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28630 to look at the new patch set (#2). Change subject: mb/asrock/g41c-gs: Link separate gpio.c files ...................................................................... mb/asrock/g41c-gs: Link separate gpio.c files With the addition of new boards using macros to set per board settings in the same gpio.c file is getting too complicated so link separate files. Change-Id: I3ab05f1af6ba0a04dd827816b3bcaa506a3f6aff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Makefile.inc C src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c C src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c R src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c 5 files changed, 7 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28630/2 -- To view, visit https://review.coreboot.org/28630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3ab05f1af6ba0a04dd827816b3bcaa506a3f6aff Gerrit-Change-Number: 28630 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/amd/sr5650/sr5650.h: Get rid of device_t
by Elyes HAOUAS (Code Review) 16 Sep '18

16 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28633 Change subject: sb/amd/sr5650/sr5650.h: Get rid of device_t ...................................................................... sb/amd/sr5650/sr5650.h: Get rid of device_t Use of device_t has been abandoned in ramstage. Change-Id: Ib4dbb607cfd1e02d45efe141b498d6505574d6e6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/sr5650/sr5650.h 1 file changed, 35 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28633/1 diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h index ea7005c..2e6b728 100644 --- a/src/southbridge/amd/sr5650/sr5650.h +++ b/src/southbridge/amd/sr5650/sr5650.h @@ -89,47 +89,52 @@ extern PCIE_CFG AtiPcieCfg; /* ----------------- export functions ----------------- */ -u32 nbpcie_p_read_index(device_t dev, u32 index); -void nbpcie_p_write_index(device_t dev, u32 index, u32 data); -u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); -void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data); -uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index); -void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data); -uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index); -void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data); -u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg); -void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); -void sr5650_set_tom(device_t nb_dev); +u32 nbpcie_p_read_index(struct device *dev, u32 index); +void nbpcie_p_write_index(struct device *dev, u32 index, u32 data); +u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index); +void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data); +uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index); +void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index, + uint32_t data); +uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index); +void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, + uint32_t data); +u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg); +void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg, + u32 mask, u32 val); +void sr5650_set_tom(struct device *nb_dev); -unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, - struct acpi_rsdp *rsdp); +unsigned long southbridge_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp); void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); -void enable_pcie_bar3(device_t nb_dev); -void disable_pcie_bar3(device_t nb_dev); +void enable_pcie_bar3(struct device *nb_dev); +void disable_pcie_bar3(struct device *nb_dev); void enable_sr5650_dev8(void); void sr5650_htinit(void); void sr5650_htinit_dect_and_enable_isochronous_link(void); void sr5650_early_setup(void); void sr5650_before_pci_init(void); -void sr5650_enable(device_t dev); -void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port); -void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port); -void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); -void config_gpp_core(device_t nb_dev, device_t sb_dev); -void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); -u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); -void pcie_config_misc_clk(device_t nb_dev); +void sr5650_enable(struct device *dev); +void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port); +void sr5650_gfx_init(struct device *nb_dev, struct device *dev, u32 port); +void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev); +void config_gpp_core(struct device *nb_dev, struct device *sb_dev); +void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, + u32 port); +u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port); +void pcie_config_misc_clk(struct device *nb_dev); void fam10_optimization(void); void sr5650_disable_pcie_bridge(void); -u32 get_vid_did(device_t dev); -void detect_and_enable_iommu(device_t iommu_dev); -void sr5650_iommu_read_resources(device_t dev); -void sr5650_iommu_set_resources(device_t dev); -void sr5650_iommu_enable_resources(device_t dev); -void sr5650_nb_pci_table(device_t nb_dev); -void init_gen2(device_t nb_dev, device_t dev, u8 port); +u32 get_vid_did(struct device *dev); +void detect_and_enable_iommu(struct device *iommu_dev); +void sr5650_iommu_read_resources(struct device *dev); +void sr5650_iommu_set_resources(struct device *dev); +void sr5650_iommu_enable_resources(struct device *dev); +void sr5650_nb_pci_table(struct device *nb_dev); +void init_gen2(struct device *nb_dev, struct device *dev, u8 port); void sr56x0_lock_hwinitreg(void); struct resource * sr5650_retrieve_cpu_mmio_resource(void); #endif /* __SR5650_H__ */ -- To view, visit https://review.coreboot.org/28633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4dbb607cfd1e02d45efe141b498d6505574d6e6 Gerrit-Change-Number: 28633 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Felix Held (Code Review) 16 Sep '18

16 Sep '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28596 ) Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/28596/5/src/mainboard/asrock/g41c-gs/gpio.c File src/mainboard/asrock/g41c-gs/gpio.c: https://review.coreboot.org/#/c/28596/5/src/mainboard/asrock/g41c-gs/gpio.c… PS5, Line 75: : : : > This file is becoming a mess. […] this probably needs the makefile to be adapted, so that the file in the new location is used for that boards -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 16 Sep 2018 16:44:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium/cn81xx: Don't use device_t in ramstage
by Elyes HAOUAS (Code Review) 16 Sep '18

16 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28632 Change subject: soc/cavium/cn81xx: Don't use device_t in ramstage ...................................................................... soc/cavium/cn81xx: Don't use device_t in ramstage Use of device_t has been abandoned in ramstage. Change-Id: Ifa54624664c06c606fb4e083bae98b4accc61be0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/cavium/cn81xx/soc.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28632/1 diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 4a4312d..d9eb052 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -326,7 +326,7 @@ BM_MEM_RESERVED); } -static void soc_read_resources(device_t dev) +static void soc_read_resources(struct device *dev) { // HACK: Don't advertise bootblock romstage CAR region, it's broken... ram_resource(dev, 0, 2 * KiB, sdram_size_mb() * KiB - 2 * KiB); @@ -358,7 +358,7 @@ register_bl31_param(&cbtable_param.h); } -static void soc_init(device_t dev) +static void soc_init(struct device *dev) { /* Init ECAM, MDIO, PEM, PHY, QLM ... */ bdk_boot(); @@ -378,7 +378,7 @@ soc_init_atf(); } -static void soc_final(device_t dev) +static void soc_final(struct device *dev) { watchdog_disable(0); } @@ -392,7 +392,7 @@ .scan_bus = NULL, }; -static void enable_soc_dev(device_t dev) +static void enable_soc_dev(struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN && dev->path.domain.domain == 0) { -- To view, visit https://review.coreboot.org/28632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa54624664c06c606fb4e083bae98b4accc61be0 Gerrit-Change-Number: 28632 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/intel/common/block: Don't use device_t in ramstage
by Elyes HAOUAS (Code Review) 16 Sep '18

16 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28631 Change subject: soc/intel/common/block: Don't use device_t in ramstage ...................................................................... soc/intel/common/block: Don't use device_t in ramstage Use of device_t has been abandoned in ramstage. Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/systemagent/systemagent.c 7 files changed, 15 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28631/1 diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index f58f914..6b1b9bd 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -42,7 +42,7 @@ * Calls acpi_write_hpet which creates and fills HPET table and * adds it to the RSDT (and XSDT) structure. */ -unsigned long southbridge_write_acpi_tables(device_t device, +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp); @@ -50,7 +50,7 @@ * Creates acpi gnvs and adds it to the DSDT table. * GNVS creation is chipset specific and is done in soc specific acpi.c file. */ -void southbridge_inject_dsdt(device_t device); +void southbridge_inject_dsdt(struct device *device); /* * This function populates the gnvs structure in acpi table. diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index f489e27..58f07ea 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -34,7 +34,7 @@ /* * Write ASL entry for Graphics opregion * Input: - * device_t device: device structure + * strcut device *device: device structure * current: start address of graphics opregion * rsdp: pointer to RSDT (and XSDT) structure * diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 4ad51d0..c5677e4 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -75,7 +75,7 @@ * In this function SOC must perform CPU feature programming * during Ramstage phase. */ -void soc_core_init(device_t dev); +void soc_core_init(struct device *dev); /* * In this function SOC must fill required mp_ops params, also it diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index c462d9d..ef8417a 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -46,7 +46,7 @@ res->flags = flags; } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { /* Add the default claimed legacy IO range for the LPC device. */ pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO | @@ -56,7 +56,7 @@ pch_lpc_soc_fill_io_resources(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { /* Get the PCI resources of this device. */ pci_dev_read_resources(dev); @@ -101,7 +101,7 @@ } } -static void pch_lpc_set_resources(device_t dev) +static void pch_lpc_set_resources(struct device *dev) { pci_dev_set_resources(dev); diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 4cd057d..c4b266a 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -64,7 +64,7 @@ pci_write_config16(dev, PCI_SEC_STATUS, reg16); } -static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset) +static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) { /* Set max snoop and non-snoop latency for the SOC */ pci_write_config32(dev, offset, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 3793025..9bb9436 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -22,7 +22,7 @@ #include <soc/smbus.h> #include "smbuslib.h" -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -33,7 +33,7 @@ return smbus_read8(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -50,7 +50,7 @@ .write_byte = lsmbus_write_byte, }; -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; @@ -64,7 +64,7 @@ outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_IO_BASE; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 72cecb1..45ee940 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -88,7 +88,7 @@ }; /* Read DRAM memory map register value through PCI configuration space */ -static void sa_read_map_entry(device_t dev, +static void sa_read_map_entry(struct device *dev, const struct sa_mem_map_descriptor *entry, uint64_t *result) { uint64_t value = 0; @@ -213,7 +213,8 @@ return !!(imr_base_reg & (1 << 31)); } -static void imr_resource(device_t dev, int idx, uint32_t base, uint32_t mask) +static void imr_resource(struct device *dev, int idx, uint32_t base, + uint32_t mask) { uint32_t base_k, size_k; /* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */ -- To view, visit https://review.coreboot.org/28631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19 Gerrit-Change-Number: 28631 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28596 to look at the new patch set (#7). Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... mb/asrock/g41m_vs3_r2: Add mainboard The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Kconfig.name M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c 5 files changed, 308 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28596/7 -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: mb/asrock/g41c-gs: Link separate gpio.c files
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28630 Change subject: mb/asrock/g41c-gs: Link separate gpio.c files ...................................................................... mb/asrock/g41c-gs: Link separate gpio.c files With the addition of new boards using macros to set per board settings in the same gpio.c file is getting too complicated so link separate files. Change-Id: I3ab05f1af6ba0a04dd827816b3bcaa506a3f6aff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Makefile.inc C src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c C src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c R src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c 5 files changed, 7 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28630/1 diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index ad2fe22..f9dddfd 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -41,6 +41,12 @@ string default "asrock/g41c-gs" +config VARIANT_DIR + string + default "g41c_gs_r2" if BOARD_ASROCK_G41C_GS_R2_0 + default "g41c-gs" if BOARD_ASROCK_G41C_GS + default "g41m-gs" if BOARD_ASROCK_G41M_GS + config MAINBOARD_PART_NUMBER string default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0 diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc index 0786d6f..82e72fb 100644 --- a/src/mainboard/asrock/g41c-gs/Makefile.inc +++ b/src/mainboard/asrock/g41c-gs/Makefile.inc @@ -1,4 +1,4 @@ ramstage-y += cstates.c -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c similarity index 79% copy from src/mainboard/asrock/g41c-gs/gpio.c copy to src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c index b6ccbad..6299d62 100644 --- a/src/mainboard/asrock/g41c-gs/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c @@ -45,27 +45,18 @@ .gpio10 = GPIO_DIR_OUTPUT, .gpio12 = GPIO_DIR_INPUT, .gpio13 = GPIO_DIR_INPUT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio14 = GPIO_DIR_OUTPUT, -#else .gpio14 = GPIO_DIR_INPUT, -#endif .gpio15 = GPIO_DIR_OUTPUT, .gpio16 = GPIO_DIR_OUTPUT, .gpio18 = GPIO_DIR_OUTPUT, .gpio20 = GPIO_DIR_OUTPUT, .gpio24 = GPIO_DIR_OUTPUT, .gpio25 = GPIO_DIR_OUTPUT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio26 = GPIO_DIR_OUTPUT, -#else .gpio26 = GPIO_DIR_INPUT, -#endif .gpio27 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_INPUT, }; -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio10 = GPIO_LEVEL_LOW, .gpio15 = GPIO_LEVEL_LOW, @@ -76,31 +67,10 @@ .gpio25 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, }; -#else /* BOARD_ASROCK_G41C_GS, BOARD_ASROCK_G41M_GS*/ -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio10 = GPIO_LEVEL_LOW, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio14 = GPIO_LEVEL_HIGH, -#endif - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_HIGH, - .gpio25 = GPIO_LEVEL_LOW, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio26 = GPIO_LEVEL_LOW, -#endif - .gpio27 = GPIO_LEVEL_LOW, -}; -#endif static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_INVERT, .gpio6 = GPIO_INVERT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio8 = GPIO_INVERT, -#endif .gpio12 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; diff --git a/src/mainboard/asrock/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c similarity index 79% copy from src/mainboard/asrock/g41c-gs/gpio.c copy to src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c index b6ccbad..52cd611 100644 --- a/src/mainboard/asrock/g41c-gs/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c @@ -45,62 +45,32 @@ .gpio10 = GPIO_DIR_OUTPUT, .gpio12 = GPIO_DIR_INPUT, .gpio13 = GPIO_DIR_INPUT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio14 = GPIO_DIR_OUTPUT, -#else .gpio14 = GPIO_DIR_INPUT, -#endif .gpio15 = GPIO_DIR_OUTPUT, .gpio16 = GPIO_DIR_OUTPUT, .gpio18 = GPIO_DIR_OUTPUT, .gpio20 = GPIO_DIR_OUTPUT, .gpio24 = GPIO_DIR_OUTPUT, .gpio25 = GPIO_DIR_OUTPUT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio26 = GPIO_DIR_OUTPUT, -#else .gpio26 = GPIO_DIR_INPUT, -#endif .gpio27 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_INPUT, }; -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio10 = GPIO_LEVEL_LOW, .gpio15 = GPIO_LEVEL_LOW, .gpio16 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_HIGH, - .gpio25 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_LOW, -}; -#else /* BOARD_ASROCK_G41C_GS, BOARD_ASROCK_G41M_GS*/ -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio10 = GPIO_LEVEL_LOW, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio14 = GPIO_LEVEL_HIGH, -#endif - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, .gpio18 = GPIO_LEVEL_LOW, .gpio20 = GPIO_LEVEL_HIGH, .gpio24 = GPIO_LEVEL_HIGH, .gpio25 = GPIO_LEVEL_LOW, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio26 = GPIO_LEVEL_LOW, -#endif .gpio27 = GPIO_LEVEL_LOW, }; -#endif static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_INVERT, .gpio6 = GPIO_INVERT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) - .gpio8 = GPIO_INVERT, -#endif .gpio12 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; diff --git a/src/mainboard/asrock/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c similarity index 81% rename from src/mainboard/asrock/g41c-gs/gpio.c rename to src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c index b6ccbad..cea01cf 100644 --- a/src/mainboard/asrock/g41c-gs/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c @@ -45,62 +45,35 @@ .gpio10 = GPIO_DIR_OUTPUT, .gpio12 = GPIO_DIR_INPUT, .gpio13 = GPIO_DIR_INPUT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) .gpio14 = GPIO_DIR_OUTPUT, -#else - .gpio14 = GPIO_DIR_INPUT, -#endif .gpio15 = GPIO_DIR_OUTPUT, .gpio16 = GPIO_DIR_OUTPUT, .gpio18 = GPIO_DIR_OUTPUT, .gpio20 = GPIO_DIR_OUTPUT, .gpio24 = GPIO_DIR_OUTPUT, .gpio25 = GPIO_DIR_OUTPUT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) .gpio26 = GPIO_DIR_OUTPUT, -#else - .gpio26 = GPIO_DIR_INPUT, -#endif .gpio27 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_INPUT, }; -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio10 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_HIGH, - .gpio25 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_LOW, -}; -#else /* BOARD_ASROCK_G41C_GS, BOARD_ASROCK_G41M_GS*/ -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio10 = GPIO_LEVEL_LOW, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) .gpio14 = GPIO_LEVEL_HIGH, -#endif .gpio15 = GPIO_LEVEL_LOW, .gpio16 = GPIO_LEVEL_HIGH, .gpio18 = GPIO_LEVEL_LOW, .gpio20 = GPIO_LEVEL_HIGH, .gpio24 = GPIO_LEVEL_HIGH, .gpio25 = GPIO_LEVEL_LOW, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) .gpio26 = GPIO_LEVEL_LOW, -#endif .gpio27 = GPIO_LEVEL_LOW, }; -#endif static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_INVERT, .gpio6 = GPIO_INVERT, -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) .gpio8 = GPIO_INVERT, -#endif .gpio12 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -- To view, visit https://review.coreboot.org/28630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3ab05f1af6ba0a04dd827816b3bcaa506a3f6aff Gerrit-Change-Number: 28630 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/asrock/g41m_vs3_r2: Add mainboard
by Arthur Heymans (Code Review) 16 Sep '18

16 Sep '18

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28596 to look at the new patch set (#6). Change subject: mb/asrock/g41m_vs3_r2: Add mainboard ...................................................................... mb/asrock/g41m_vs3_r2: Add mainboard The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asrock/g41c-gs/Kconfig.name M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c 5 files changed, 308 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28596/6 -- To view, visit https://review.coreboot.org/28596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Gerrit-Change-Number: 28596 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: nb/amd/pi/00730F01: Don't use device_t in ramstage
by Elyes HAOUAS (Code Review) 16 Sep '18

16 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28629 Change subject: nb/amd/pi/00730F01: Don't use device_t in ramstage ...................................................................... nb/amd/pi/00730F01: Don't use device_t in ramstage Use of device_t has been abandoned in ramstage Change-Id: Ifc32b0f6964a8c3e3a100c787ac2a889b39322a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/28629/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 2b81998..ab67b43 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -583,7 +583,7 @@ { uint8_t *p; - device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); -- To view, visit https://review.coreboot.org/28629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifc32b0f6964a8c3e3a100c787ac2a889b39322a6 Gerrit-Change-Number: 28629 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/lenovo/x200: Use lower C-states on battery
by build bot (Jenkins) (Code Review) 16 Sep '18

16 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22932 ) Change subject: mb/lenovo/x200: Use lower C-states on battery ...................................................................... Patch Set 12: (2 comments) https://review.coreboot.org/#/c/22932/12/src/arch/x86/include/arch/acpigen.h File src/arch/x86/include/arch/acpigen.h: https://review.coreboot.org/#/c/22932/12/src/arch/x86/include/arch/acpigen.… PS12, Line 354: int get_bat_cst_entries(acpi_cstate_t **); function definition argument 'acpi_cstate_t **' should also have an identifier name https://review.coreboot.org/#/c/22932/12/src/cpu/intel/speedstep/acpi.c File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/#/c/22932/12/src/cpu/intel/speedstep/acpi.c@187 PS12, Line 187: num_bat_cstates); line over 80 characters -- To view, visit https://review.coreboot.org/22932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Gerrit-Change-Number: 22932 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 16 Sep 2018 14:47:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018