coreboot-gerrit September 2018

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Change in coreboot[master]: payloads/tianocore: Remove out dated ptches
by Lijian Zhao (Code Review) 17 Sep '18

17 Sep '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28650 Change subject: payloads/tianocore: Remove out dated ptches ...................................................................... payloads/tianocore: Remove out dated ptches The following two changes already got merged in EDK2 main branch, no need to apply patches any more. They are: 07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch 08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch BUG=N/A TEST=Build with tianocore pass. Change-Id: Ia6b4d1105360a3ea3319711a14d3e980bc0bf776 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- D payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch D payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch 2 files changed, 0 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/28650/1 diff --git a/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch b/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch deleted file mode 100644 index 9b2569a..0000000 --- a/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 2e75f9ad6ef625575185dfc262c6803a89850dd5 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur(a)aheymans.xyz> -Date: Wed, 24 Jan 2018 10:07:08 +0100 -Subject: [PATCH] CorebootPayloadPkg: Use correct BytesPerScanLine - -Fetch BytesPerScanLine from coreboot table to reflect how the actual -framebuffer is set up instead of guessing it from the horizontal -resolution. - -This fixes a garbled display when HorizontalResolution * (BitsPerPixel -/ 8) and pFbInfo->BytesPerScanLine don't match. - -Contributed-under: TianoCore Contribution Agreement 1.1 -Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> ---- - CorebootPayloadPkg/FbGop/FbGop.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c -index 37d6def7f780..679061703358 100644 ---- a/CorebootPayloadPkg/FbGop/FbGop.c -+++ b/CorebootPayloadPkg/FbGop/FbGop.c -@@ -822,7 +822,7 @@ FbGopCheckForVbe ( - BitsPerPixel = pFbInfo->BitsPerPixel; - HorizontalResolution = pFbInfo->HorizontalResolution; - VerticalResolution = pFbInfo->VerticalResolution; -- BytesPerScanLine = HorizontalResolution * (BitsPerPixel / 8); -+ BytesPerScanLine = pFbInfo->BytesPerScanLine; - - ModeBuffer = (FB_VIDEO_MODE_DATA *) AllocatePool ( - ModeNumber * sizeof (FB_VIDEO_MODE_DATA) --- -2.17.0 - diff --git a/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch b/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch deleted file mode 100644 index 4881fff..0000000 --- a/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 8cb365e9ec90420e3d04b77f6e7999a65d5983a6 Mon Sep 17 00:00:00 2001 -From: Patrick Rudolph <siro(a)das-labor.org> -Date: Sun, 17 Jun 2018 08:44:51 +0200 -Subject: [PATCH] BaseTools: Fix building with -Werror=stringop-truncation - -Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> ---- - BaseTools/Source/C/GenVtf/GenVtf.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/BaseTools/Source/C/GenVtf/GenVtf.c b/BaseTools/Source/C/GenVtf/GenVtf.c -index 65ae08eeceb8..d4200621457c 100644 ---- a/BaseTools/Source/C/GenVtf/GenVtf.c -+++ b/BaseTools/Source/C/GenVtf/GenVtf.c -@@ -129,9 +129,9 @@ Returns: - } else { - Length = strlen(Str); - if (Length < 4) { -- strncpy (TemStr + 4 - Length, Str, Length); -+ memcpy (TemStr + 4 - Length, Str, Length); - } else { -- strncpy (TemStr, Str + Length - 4, 4); -+ memcpy (TemStr, Str + Length - 4, 4); - } - - sscanf ( -@@ -1521,7 +1521,7 @@ Returns: - // - FitStartPtr = (FIT_TABLE *) RelativeAddress; - -- strncpy ((CHAR8 *) &FitStartPtr->CompAddress, FIT_SIGNATURE, 8); // "_FIT_ " -+ memcpy ((CHAR8 *) &FitStartPtr->CompAddress, FIT_SIGNATURE, 8); // "_FIT_ " - assert (((VtfInfo->CompSize & 0x00FFFFFF) % 16) == 0); - FitStartPtr->CompSize = (VtfInfo->CompSize & 0x00FFFFFF) / 16; - FitStartPtr->CompVersion = MAKE_VERSION (VtfInfo->MajorVer, VtfInfo->MinorVer); --- -2.17.0 - -- To view, visit https://review.coreboot.org/28650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia6b4d1105360a3ea3319711a14d3e980bc0bf776 Gerrit-Change-Number: 28650 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mainboard/google/kahlee: EMMC reset needs to be output low
by Raul Rangel (Code Review) 17 Sep '18

17 Sep '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28649 ) Change subject: mainboard/google/kahlee: EMMC reset needs to be output low ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife014b8a879274df5d892c1de386976808de1df0 Gerrit-Change-Number: 28649 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Sep 2018 16:17:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/kahlee: EMMC reset needs to be output low
by Martin Roth (Code Review) 17 Sep '18

17 Sep '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28649 Change subject: mainboard/google/kahlee: EMMC reset needs to be output low ...................................................................... mainboard/google/kahlee: EMMC reset needs to be output low While the pin was set to a pull-down, with the external pull-up, this wasn't enough to keep the pin low. Set to output low to drive to 0V. TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V. BUG=b:115661061 Change-Id: Ife014b8a879274df5d892c1de386976808de1df0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/28649/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 75a8ab5..95064bc 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -54,7 +54,7 @@ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* GPIO_40 - EMMC_BRIDGE_RST */ - PAD_GPI(GPIO_40, PULL_DOWN), + PAD_GPO(GPIO_40, LOW), /* GPIO_70 - WLAN_PE_RST_L */ PAD_GPO(GPIO_70, HIGH), -- To view, visit https://review.coreboot.org/28649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife014b8a879274df5d892c1de386976808de1df0 Gerrit-Change-Number: 28649 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by Elyes HAOUAS (Code Review) 17 Sep '18

17 Sep '18

Hello Arthur Heymans, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28648 to look at the new patch set (#2). Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank CxDRT1 bit #16 "Pre-All to Activate Delay" must be set if any rank is populated with 8-bank device technology. Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28648/2 -- To view, visit https://review.coreboot.org/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by Elyes HAOUAS (Code Review) 17 Sep '18

17 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28648 Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank CxDRT1 bit #16 Pre-All to Activate Delay mut be set if any rank is populated with 8-bank device technology. Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28648/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c259530..b53afac 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1491,6 +1491,11 @@ temp_drt |= (sysinfo->trfc) << 10; /* Pre-All to Activate Delay */ + for (i = 0; i < 2*DIMM_SOCKETS; i++) { + if (sysinfo->banks[i] != 8) + continue; + temp_drt |= (1 << 16); + } temp_drt |= (0 << 16); /* Precharge to Precharge Delay stays at 1 clock */ -- To view, visit https://review.coreboot.org/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/drivers/intel/fsp1_1: Configure UART after memory init
by Patrick Rudolph (Code Review) 17 Sep '18

17 Sep '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28464 ) Change subject: src/drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > There should be an UPD to configure FSP to enable / disable the onboard UART. Am I wrong ? > > Braswell FSP MR2 does not have UPD to enable/disable onboard UART. There's PcdEnableHsuart0/PcdEnableHsuart1. Did you test if that works for you ? -- To view, visit https://review.coreboot.org/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 17 Sep 2018 10:40:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/arm/include/armv7/arch: Don't hide pointer behind typedef
by Elyes HAOUAS (Code Review) 17 Sep '18

17 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28646 to look at the new patch set (#2). Change subject: arch/arm/include/armv7/arch: Don't hide pointer behind typedef ...................................................................... arch/arm/include/armv7/arch: Don't hide pointer behind typedef Use of device_t has been abandoned in ramstage. Change-Id: Id3199d130825a5f796108ae45ce965325511ce8b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/include/armv7/arch/cpu.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/28646/2 -- To view, visit https://review.coreboot.org/28646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id3199d130825a5f796108ae45ce965325511ce8b Gerrit-Change-Number: 28646 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/drivers/intel/fsp1_1: Configure UART after memory init
by Frans Hendriks (Code Review) 17 Sep '18

17 Sep '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/28464 ) Change subject: src/drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 1: > Patch Set 1: > > There should be an UPD to configure FSP to enable / disable the onboard UART. Am I wrong ? Braswell FSP MR2 does not have UPD to enable/disable onboard UART. -- To view, visit https://review.coreboot.org/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 17 Sep 2018 09:34:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/arm/include/armv7/arch: Don't hide pointer behind typedef
by Elyes HAOUAS (Code Review) 17 Sep '18

17 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28646 Change subject: arch/arm/include/armv7/arch: Don't hide pointer behind typedef ...................................................................... arch/arm/include/armv7/arch: Don't hide pointer behind typedef Use of device_t has been abandoned in ramstage. Change-Id: Id3199d130825a5f796108ae45ce965325511ce8b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/include/armv7/arch/cpu.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/28646/1 diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 18d86e0..5f65b37 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -31,7 +31,7 @@ struct thread; struct cpu_info { - device_t cpu; + strcut device *cpu; unsigned long index; #if IS_ENABLED(CONFIG_COOP_MULTITASKING) struct thread *thread; -- To view, visit https://review.coreboot.org/28646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id3199d130825a5f796108ae45ce965325511ce8b Gerrit-Change-Number: 28646 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/device/device.c: Don't use device_t in ramstage
by Elyes HAOUAS (Code Review) 17 Sep '18

17 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28645 Change subject: src/device/device.c: Don't use device_t in ramstage ...................................................................... src/device/device.c: Don't use device_t in ramstage Use of device_t has been abandoned in ramstage. Change-Id: I3d1bdefd00c91a98116ede5dc03c3ce253d1f0ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/device.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/28645/1 diff --git a/src/device/device.c b/src/device/device.c index 7ba9d0a..dcbaef1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -118,7 +118,7 @@ * * @see device_path */ -static device_t __alloc_dev(struct bus *parent, struct device_path *path) +static struct device *__alloc_dev(struct bus *parent, struct device_path *path) { struct device *dev, *child; @@ -152,7 +152,7 @@ return dev; } -device_t alloc_dev(struct bus *parent, struct device_path *path) +struct device *alloc_dev(struct bus *parent, struct device_path *path) { struct device *dev; spin_lock(&dev_lock); @@ -168,7 +168,7 @@ * @param path The relative path from the bus to the appropriate device. * @return Pointer to a device structure for the device on bus at path. */ -device_t alloc_find_dev(struct bus *parent, struct device_path *path) +struct device *alloc_find_dev(struct bus *parent, struct device_path *path) { struct device *child; spin_lock(&dev_lock); -- To view, visit https://review.coreboot.org/28645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3d1bdefd00c91a98116ede5dc03c3ce253d1f0ed Gerrit-Change-Number: 28645 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit September 2018