coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

1 participants
886 discussions

Change in coreboot[master]: mb/clevo/n130wu: Add mainboard
by build bot (Jenkins) (Code Review) 18 Sep '18

18 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28640 ) Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... Patch Set 6: (4 comments) https://review.coreboot.org/#/c/28640/6/src/mainboard/clevo/n130wu/gpio.h File src/mainboard/clevo/n130wu/gpio.h: https://review.coreboot.org/#/c/28640/6/src/mainboard/clevo/n130wu/gpio.h@1… PS6, Line 111: /* ISH_UART0_RXD/SML0BDATA/I2C4B_SDA */_PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0), line over 80 characters https://review.coreboot.org/#/c/28640/6/src/mainboard/clevo/n130wu/gpio.h@1… PS6, Line 112: /* ISH_UART0_TXD/SML0BCLK/I2C4B_SCL */ _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0), line over 80 characters https://review.coreboot.org/#/c/28640/6/src/mainboard/clevo/n130wu/gpio.h@1… PS6, Line 113: /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), line over 80 characters https://review.coreboot.org/#/c/28640/6/src/mainboard/clevo/n130wu/gpio.h@1… PS6, Line 114: /* ISH_UART0_CTS#/SML0BALERT# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), line over 80 characters -- To view, visit https://review.coreboot.org/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Sep 2018 02:42:46 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/clevo/n130wu: Add mainboard
by build bot (Jenkins) (Code Review) 18 Sep '18

18 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28640 ) Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... Patch Set 5: (4 comments) https://review.coreboot.org/#/c/28640/5/src/mainboard/clevo/n130wu/gpio.h File src/mainboard/clevo/n130wu/gpio.h: https://review.coreboot.org/#/c/28640/5/src/mainboard/clevo/n130wu/gpio.h@1… PS5, Line 111: /* ISH_UART0_RXD/SML0BDATA/I2C4B_SDA */_PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0), line over 80 characters https://review.coreboot.org/#/c/28640/5/src/mainboard/clevo/n130wu/gpio.h@1… PS5, Line 112: /* ISH_UART0_TXD/SML0BCLK/I2C4B_SCL */ _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0), line over 80 characters https://review.coreboot.org/#/c/28640/5/src/mainboard/clevo/n130wu/gpio.h@1… PS5, Line 113: /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), line over 80 characters https://review.coreboot.org/#/c/28640/5/src/mainboard/clevo/n130wu/gpio.h@1… PS5, Line 114: /* ISH_UART0_CTS#/SML0BALERT# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), line over 80 characters -- To view, visit https://review.coreboot.org/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Sep 2018 02:38:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mainboard/google/kahlee: Don't set global subsystem IDs
by Marc Jones (Code Review) 17 Sep '18

17 Sep '18

Marc Jones has posted comments on this change. ( https://review.coreboot.org/28652 ) Change subject: mainboard/google/kahlee: Don't set global subsystem IDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064 Gerrit-Change-Number: 28652 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Sep 2018 21:15:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mainboard/google/kahlee: Don't set global subsystem IDs
by Raul Rangel (Code Review) 17 Sep '18

17 Sep '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28652 ) Change subject: mainboard/google/kahlee: Don't set global subsystem IDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064 Gerrit-Change-Number: 28652 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Sep 2018 21:05:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mainboard/google/kahlee: allow oem.bin file to update smbios
by Raul Rangel (Code Review) 17 Sep '18

17 Sep '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28651 ) Change subject: mainboard/google/kahlee: allow oem.bin file to update smbios ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28651/1/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/baseboard/mainboard.c: https://review.coreboot.org/#/c/28651/1/src/mainboard/google/kahlee/variant… PS1, Line 93: const char *smbios_mainboard_manufacturer(void) ah, it looks like nami already does this. Should we extract the struct and method into a common file? https://review.coreboot.org/#/c/28651/1/src/mainboard/google/kahlee/variant… PS1, Line 111: It might be easier to read if you calculated the number of oem_entries and just did a for loop over the count. -- To view, visit https://review.coreboot.org/28651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Gerrit-Change-Number: 28651 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Sep 2018 21:05:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mainboard/google/kahlee: allow oem.bin file to update smbios
by Martin Roth (Code Review) 17 Sep '18

17 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28651 ) Change subject: mainboard/google/kahlee: allow oem.bin file to update smbios ...................................................................... Patch Set 1: This just sets up coreboot so it can be used. The change for the .bin is in the internal private overlay repo, and the saved .config files will need to be updated for the variants that need this. -- To view, visit https://review.coreboot.org/28651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Gerrit-Change-Number: 28651 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Sep 2018 20:52:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mainboard/google/kahlee: allow oem.bin file to update smbios
by build bot (Jenkins) (Code Review) 17 Sep '18

17 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28651 ) Change subject: mainboard/google/kahlee: allow oem.bin file to update smbios ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28651/1/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/baseboard/mainboard.c: https://review.coreboot.org/#/c/28651/1/src/mainboard/google/kahlee/variant… PS1, Line 84: /* "oem.bin" in cbfs contains an array of records using the following structure. */ line over 80 characters https://review.coreboot.org/#/c/28651/1/src/mainboard/google/kahlee/variant… PS1, Line 101: if (! IS_ENABLED(CONFIG_USE_OEM_BIN)) space prohibited after that '!' (ctx:BxW) -- To view, visit https://review.coreboot.org/28651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Gerrit-Change-Number: 28651 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Sep 2018 20:50:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mainboard/kahlee: Use devicetree override files
by Martin Roth (Code Review) 17 Sep '18

17 Sep '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28653 Change subject: mainboard/kahlee: Use devicetree override files ...................................................................... mainboard/kahlee: Use devicetree override files BUG=b:115793865 TEST=Build each variant, make sure the final static.c files are valid Change-Id: I907b313e2b3079babf4aeb894ba126e6510454ba Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/Kconfig D src/mainboard/google/kahlee/variants/aleena/devicetree.cb A src/mainboard/google/kahlee/variants/aleena/overridetree.cb R src/mainboard/google/kahlee/variants/baseboard/devicetree.cb D src/mainboard/google/kahlee/variants/careena/devicetree.cb A src/mainboard/google/kahlee/variants/careena/overridetree.cb A src/mainboard/google/kahlee/variants/grunt/overridetree.cb D src/mainboard/google/kahlee/variants/liara/devicetree.cb A src/mainboard/google/kahlee/variants/liara/overridetree.cb 9 files changed, 174 insertions(+), 500 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28653/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 5ea904c..a9e90ee 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -69,7 +69,11 @@ config DEVICETREE string - default "variants/${CONFIG_VARIANT_DIR}/devicetree.cb" + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_FAMILY string diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb deleted file mode 100644 index e33ed2c..0000000 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ /dev/null @@ -1,163 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" - - # Enable I2C0 for audio, USB3 hub at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 95, - .fall_time_ns = 3, - }" - - # Enable I2C1 for H1 at 400kHz - register "i2c[1]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, - .fall_time_ns = 4, - }" - - # Enable I2C2 for trackpad, pen at 400kHz - register "i2c[2]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 117, - .fall_time_ns = 113, - }" - - # Enable I2C3 for touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 82, - .fall_time_ns = 67, - }" - - device cpu_cluster 0 on - device lapic 10 on end - end - device domain 0 on - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # - device pci 2.2 on end # - device pci 2.3 on end # - device pci 2.4 on - chip drivers/generic/bayhub - register "power_saving" = "1" - device pci 00.0 on end - end - end # - device pci 2.5 on end # - device pci 8.0 on end # PSP - device pci 9.0 on end # PCIe Host Bridge - device pci 9.2 on end # HDA - device pci 10.0 on end # xHCI - device pci 11.0 off end # SATA - device pci 12.0 on end # EHCI - device pci 14.0 on # SMbus - end # SMbus - device pci 14.3 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC - device pci 14.7 on end # SD - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - end #domain - device mmio 0xfedc2000 on - chip drivers/generic/adau7002 - device generic 0.0 on end - end - chip drivers/i2c/da7219 - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - register "mclk_name" = ""oscout1"" - device i2c 1a on end - end - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" - register "sdmode_delay" = "5" - device generic 0.1 on end - end - end - device mmio 0xfedc3000 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end - device mmio 0xfedc4000 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "wake" = "7" - device i2c 15 on end - end - end - device mmio 0xfedc5000 on - chip drivers/i2c/generic - register "hid" = ""RAYD0001"" - register "desc" = ""Raydium Touchscreen"" - register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 39 on end - end - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end -end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/aleena/overridetree.cb b/src/mainboard/google/kahlee/variants/aleena/overridetree.cb new file mode 100644 index 0000000..dd66094 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/overridetree.cb @@ -0,0 +1,52 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 84, + .fall_time_ns = 4, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 117, + .fall_time_ns = 113, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 82, + .fall_time_ns = 67, + }" + + device mmio 0xfedc5000 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb similarity index 100% rename from src/mainboard/google/kahlee/variants/grunt/devicetree.cb rename to src/mainboard/google/kahlee/variants/baseboard/devicetree.cb diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb deleted file mode 100644 index 1677cdf..0000000 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ /dev/null @@ -1,163 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" - - # Enable I2C0 for audio, USB3 hub at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 95, - .fall_time_ns = 3, - }" - - # Enable I2C1 for H1 at 400kHz - register "i2c[1]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 45, - .fall_time_ns = 4, - }" - - # Enable I2C2 for trackpad, pen at 400kHz - register "i2c[2]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 67, - .fall_time_ns = 55, - }" - - # Enable I2C3 for touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 22, - .fall_time_ns = 19, - }" - - device cpu_cluster 0 on - device lapic 10 on end - end - device domain 0 on - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # - device pci 2.2 on end # - device pci 2.3 on end # - device pci 2.4 on - chip drivers/generic/bayhub - register "power_saving" = "1" - device pci 00.0 on end - end - end # - device pci 2.5 on end # - device pci 8.0 on end # PSP - device pci 9.0 on end # PCIe Host Bridge - device pci 9.2 on end # HDA - device pci 10.0 on end # xHCI - device pci 11.0 off end # SATA - device pci 12.0 on end # EHCI - device pci 14.0 on # SMbus - end # SMbus - device pci 14.3 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC - device pci 14.7 on end # SD - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - end #domain - device mmio 0xfedc2000 on - chip drivers/generic/adau7002 - device generic 0.0 on end - end - chip drivers/i2c/da7219 - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - register "mclk_name" = ""oscout1"" - device i2c 1a on end - end - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" - register "sdmode_delay" = "5" - device generic 0.1 on end - end - end - device mmio 0xfedc3000 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end - device mmio 0xfedc4000 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "wake" = "7" - device i2c 15 on end - end - end - device mmio 0xfedc5000 on - chip drivers/i2c/generic - register "hid" = ""RAYD0001"" - register "desc" = ""Raydium Touchscreen"" - register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 39 on end - end - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end -end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/careena/overridetree.cb b/src/mainboard/google/kahlee/variants/careena/overridetree.cb new file mode 100644 index 0000000..516ce77 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/careena/overridetree.cb @@ -0,0 +1,53 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 45, + .fall_time_ns = 4, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 67, + .fall_time_ns = 55, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 22, + .fall_time_ns = 19, + }" + + device mmio 0xfedc5000 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/grunt/overridetree.cb b/src/mainboard/google/kahlee/variants/grunt/overridetree.cb new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/grunt/overridetree.cb diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb deleted file mode 100644 index 636f0c6..0000000 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ /dev/null @@ -1,173 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" - - # Enable I2C0 for audio, USB3 hub at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 85, - .fall_time_ns = 3, - }" - - # Enable I2C1 for H1 at 400kHz - register "i2c[1]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 45, - .fall_time_ns = 4, - }" - - # Enable I2C2 for trackpad, pen at 400kHz - register "i2c[2]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 48, - .fall_time_ns = 37, - }" - - # Enable I2C3 for touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 82, - .fall_time_ns = 67, - }" - - device cpu_cluster 0 on - device lapic 10 on end - end - device domain 0 on - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # - device pci 2.2 on end # - device pci 2.3 on end # - device pci 2.4 on - chip drivers/generic/bayhub - register "power_saving" = "1" - device pci 00.0 on end - end - end # - device pci 2.5 on end # - device pci 8.0 on end # PSP - device pci 9.0 on end # PCIe Host Bridge - device pci 9.2 on end # HDA - device pci 10.0 on end # xHCI - device pci 11.0 off end # SATA - device pci 12.0 on end # EHCI - device pci 14.0 on # SMbus - end # SMbus - device pci 14.3 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC - device pci 14.7 on end # SD - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - end #domain - device mmio 0xfedc2000 on - chip drivers/generic/adau7002 - device generic 0.0 on end - end - chip drivers/i2c/da7219 - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - register "mclk_name" = ""oscout1"" - device i2c 1a on end - end - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" - register "sdmode_delay" = "5" - device generic 0.1 on end - end - end - device mmio 0xfedc3000 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - device i2c 50 on end - end - end - device mmio 0xfedc4000 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "wake" = "7" - register "probed" = "1" - device i2c 15 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "generic.wake" = "7" - register "generic.probed" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end - device mmio 0xfedc5000 on - chip drivers/i2c/generic - register "hid" = ""RAYD0001"" - register "desc" = ""Raydium Touchscreen"" - register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 39 on end - end - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end -end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/liara/overridetree.cb b/src/mainboard/google/kahlee/variants/liara/overridetree.cb new file mode 100644 index 0000000..7860961 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/overridetree.cb @@ -0,0 +1,64 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + # Enable I2C0 for audio, USB3 hub at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 85, + .fall_time_ns = 3, + }" + + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 45, + .fall_time_ns = 4, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 48, + .fall_time_ns = 37, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 82, + .fall_time_ns = 67, + }" + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end +end #chip soc/amd/stoneyridge -- To view, visit https://review.coreboot.org/28653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I907b313e2b3079babf4aeb894ba126e6510454ba Gerrit-Change-Number: 28653 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: mainboard/google/kahlee: Don't set global subsystem IDs
by Martin Roth (Code Review) 17 Sep '18

17 Sep '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28652 Change subject: mainboard/google/kahlee: Don't set global subsystem IDs ...................................................................... mainboard/google/kahlee: Don't set global subsystem IDs These values override the default subsystem IDs, and aren't needed. Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb M src/mainboard/google/kahlee/variants/careena/devicetree.cb M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/mainboard/google/kahlee/variants/liara/devicetree.cb 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/28652/1 diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 61476a2..e33ed2c 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -54,7 +54,6 @@ device lapic 10 on end end device domain 0 on - subsystemid 0x1022 0x1410 inherit device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 513bd4e..1677cdf 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -54,7 +54,6 @@ device lapic 10 on end end device domain 0 on - subsystemid 0x1022 0x1410 inherit device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index b749a94..b140939 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -54,7 +54,6 @@ device lapic 10 on end end device domain 0 on - subsystemid 0x1022 0x1410 inherit device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index 9b39b78..636f0c6 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -54,7 +54,6 @@ device lapic 10 on end end device domain 0 on - subsystemid 0x1022 0x1410 inherit device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia -- To view, visit https://review.coreboot.org/28652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064 Gerrit-Change-Number: 28652 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: mainboard/google/kahlee: allow oem.bin file to update smbios
by Martin Roth (Code Review) 17 Sep '18

17 Sep '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28651 Change subject: mainboard/google/kahlee: allow oem.bin file to update smbios ...................................................................... mainboard/google/kahlee: allow oem.bin file to update smbios Grunt variants need a way to customize the mainboard vendor based on the platform. For future boards, this can probably be done via CBI, but grunt doesn't support that method. BUG=b:79874904 TEST=Build, see updated mainboard vendor Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/variants/baseboard/Makefile.inc M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 3 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/28651/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 9180906..5ea904c 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -128,4 +128,15 @@ hex default 0x50 +config USE_OEM_BIN + bool "Add an oem.bin file" + help + Add an oem.bin file to identify the manufacturer in smbios, overriding the + CONFIG_MAINBOARD_SMBIOS_MANUFACTURER value. + +config OEM_BIN_FILE + string "OEM ID table" + depends on USE_OEM_BIN + default "" + endif # BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc index 1f6d8ce..6ffbf53 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc @@ -25,3 +25,10 @@ ramstage-y += gpio.c ramstage-y += tpm_tis.c + +# Add OEM ID table +ifeq ($(CONFIG_USE_OEM_BIN),y) +cbfs-files-y += oem.bin +oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) +oem.bin-type := raw +endif #($(CONFIG_USE_OEM_BIN),y) diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 3edcd65..657fef9 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -15,7 +15,9 @@ #include <ec/google/chromeec/ec.h> #include <baseboard/variants.h> +#include <cbfs.h> #include <gpio.h> +#include <smbios.h> #include <variant/gpio.h> #include <device/pci.h> #include <drivers/generic/bayhub/bh720.h> @@ -73,3 +75,52 @@ write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); } + +static uint8_t calc_oem_id(void) +{ + return variant_board_sku() / 0x10; +} + +/* "oem.bin" in cbfs contains an array of records using the following structure. */ +struct oem_mapping { + uint8_t oem_id; + char oem_name[10]; +} __packed; + +/* Local buffer to read "oem.bin" */ +static char oem_bin_data[200]; + +const char *smbios_mainboard_manufacturer(void) +{ + uint8_t oem_id; + const struct oem_mapping *oem_entry = (void *)&oem_bin_data; + size_t oem_data_size; + size_t curr; + static const char *manuf; + + if (! IS_ENABLED(CONFIG_USE_OEM_BIN)) + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + if (manuf) + return manuf; + + oem_data_size = cbfs_boot_load_file("oem.bin", oem_bin_data, + sizeof(oem_bin_data), + CBFS_TYPE_RAW); + oem_id = calc_oem_id(); + curr = 0; + while ((curr < oem_data_size) && + ((oem_data_size - curr) >= sizeof(*oem_entry))) { + if (oem_id == oem_entry->oem_id) { + manuf = oem_entry->oem_name; + break; + } + curr += sizeof(*oem_entry); + oem_entry++; + } + + if (manuf == NULL) + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + return manuf; +} -- To view, visit https://review.coreboot.org/28651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Gerrit-Change-Number: 28651 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

← Newer
1
...
40
41
42
43
44
45
46
...
89
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2018