coreboot-gerrit September 2018

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Change in coreboot[master]: [RFC] Documentation: Remove Kconfig.tex and related files
by Jonathan Neuschäfer (Code Review) 18 Sep '18

18 Sep '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28665 Change subject: [RFC] Documentation: Remove Kconfig.tex and related files ...................................................................... [RFC] Documentation: Remove Kconfig.tex and related files This part of our documentation has bitrotted for a long time. Any remaining information should ideally be moved to Documentation/getting_started/kconfig.md. Change-Id: I3920d002813c2838285446dc0ed8dacfa5364581 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M .gitignore D Documentation/Kconfig.tex M Documentation/Makefile 3 files changed, 3 insertions(+), 511 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28665/1 diff --git a/.gitignore b/.gitignore index 7523a5f..6801bcd 100644 --- a/.gitignore +++ b/.gitignore @@ -127,10 +127,6 @@ documentation/*.toc documentation/*.out documentation/*.pdf -documentation/cpukconfig.tex -documentation/mainboardkconfig.tex -documentation/skconfig.tex -documentation/socketfkconfig.tex Documentation/_build doxygen/* diff --git a/Documentation/Kconfig.tex b/Documentation/Kconfig.tex deleted file mode 100644 index bac8f2b..0000000 --- a/Documentation/Kconfig.tex +++ /dev/null @@ -1,480 +0,0 @@ -\documentclass[10pt,letterpaper]{article} -\usepackage[latin1]{inputenc} -\usepackage{amsmath} -\usepackage{amsfonts} -\usepackage{amssymb} -\author{Ron Minnich} -\title{Kconfig usage in coreboot v2} -\begin{document} -\section{Introduction} -This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them. -\section{Kconfig variations} -Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard. - -For variables set by the user, see src/console/Kconfig. - -For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as RAM base. These are highly mainboard dependent. - -Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally. - -\section{Makefile and Makefile.inc} -There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y. - -Make is not recursive. There is only one make process. -\subsection{subdirs usage} -Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y. - -We define the common rules for which variation to use below. -\subsection{object file specification} -There are several different types of objects specified in the tree. They are: -\begin{description} -\item[obj]objects for the RAM part of the code -\item[driver]drivers for the RAM part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. -\item[initobj]seperately-compiled code for the ROM section of coreboot -\end{description} -These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax. - -\section{Example: AMD serengeti cheetah} -\subsection{mainboard/Kconfig} -Defines Vendor variables. Currently defined variables are: -Sources all Kconfig files in the vendor directories. -\input{ mainboardkconfig.tex} -\subsection{mainboard/Makefile.inc} -There is none at this time. -\subsection{mainboard/$<$vendor$>$/Kconfig} -We use the amd as a model. The only action currently taken is to source all Kconfig's in the -subdirectories. -\subsection{mainboard/$<$vendor$>$/Makefile.inc} -We use amd as a model. There is currently no Makefile.inc at this level. -\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig} -The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines -and rules in here determine everything about how a mainboard target is built. -We will use serengeti\_cheetah as a model. It defines these variables. -\input{ mainboardkconfig.tex} -\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc} -This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece. -Note that this is the mainboard as of August, 2009, and it may change over time. -\subsubsection{objects} -We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional: -\begin{verbatim} -driver-y += mainboard.o - -#needed by irq_tables and mptable and acpi_tables -obj-y += get_bus_conf.o -obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o -obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o - -#./ssdt.o is in northbridge/amd/amdk8/Config.lb -obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o -obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o -driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o - -# This is part of the conversion to init-obj and away from included code. - -initobj-y += crt0.o -\end{verbatim} -\subsubsection{romcc legacy support} -We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define -crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the -old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally. -\begin{verbatim} -crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc -crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc -crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc -crt0-y += ../../../../src/arch/i386/lib/id.inc -crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc -crt0-y += auto.inc - -ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb -ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds -ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds -ldscript-y += ../../../../src/arch/i386/lib/id.lds -ldscript-y += ../../../../src/arch/i386/lib/failover.lds - -\end{verbatim} -\subsubsection{POST\_EVALUATION} -POST\_EVALUATION rules should be placed after this section: -\begin{verbatim} -ifdef POST_EVALUATION -\end{verbatim} -to ensure that the values of variables are correct. -Here are the post-evaluation rules for this mainboard: -\begin{verbatim} -$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl - iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl - mv dsdt.hex $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ - -$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl - iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl - perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex - mv pci2.hex ssdt2.c - -$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" - iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ - perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex - mv pci3.hex ssdt3.c - -$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" - iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl - perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex - mv pci4.hex ssdt4.c - -$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@ - perl -e 's/\.rodata/.rom.data/g' -pi $@ - perl -e 's/\.text/.section .rom.text/g' -pi $@ - -\end{verbatim} -The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables. -\subsubsection{devicetree.cb} -Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard -properly, as it defines topology and chips that can be defined no other way. -Let's go through the tree. -\begin{verbatim} -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end - end -\end{verbatim} -This topology is always somewhat confusing to newcomers, and even to coreboot veterans. - -We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we -have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge -somewhere, since it runs memory. - - -What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the -CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains -its own APIC, and will define any parameters needed. In this case, we have a northbridge of type -{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on, -which connects to a {\it cpu/amd/socket\_F}, -which has a local apic, which is on. - -Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here -is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many -BIOSes) that the BSP be CPU 0; any CPU will do. -\begin{verbatim} - device domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 -\end{verbatim} -Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On -Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up. -\begin{verbatim} - chip southbridge/amd/amd8132 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end -\end{verbatim} -This is the 8132, a bridge to a secondary PCI bus. -\begin{verbatim} - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - end -\end{verbatim} -The 8111 is a bridge to other busses and to the legacy ISA devices such as superio. -\begin{verbatim} - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end -\end{verbatim} -The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the -2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN. -\begin{verbatim} - device pci 1.1 on end - device pci 1.2 on end -\end{verbatim} -More devices. These statements set up placeholders in the device tree. -\begin{verbatim} - device pci 1.3 on - chip drivers/i2c/i2cmux # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-2-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-2-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-3-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-3-1 - device i2c 57 on end - end - end - end - end # acpi -\end{verbatim} -These are the i2c devices. -\begin{verbatim} - device pci 1.5 off end - device pci 1.6 off end -\end{verbatim} -More placeholders. -\begin{verbatim} - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - -\end{verbatim} -These "register" commands set controls in the southbridge. -\begin{verbatim} - device pci 18.0 on end - device pci 18.0 on end -\end{verbatim} -These are the other two hypertransport links. -\begin{verbatim} - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end -\end{verbatim} -The 18.1 devices are, again, northbridge control for various k8 functions. -\begin{verbatim} - end - \end{verbatim} -That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here. -\begin{verbatim} - chip northbridge/amd/amdk8 - device pci 19.0 on # northbridge - chip southbridge/amd/amd8151 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 1.0 on end - end - end # device pci 19.0 - - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - - -\end{verbatim} - -\subsection{cpu socket} -The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only -the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus -of all defines and Makefile controls for building the CPU components of a board. - -\subsubsection{ cpu/Kconfig} -Defines variables. Current variables are: -\input{cpukconfig.tex} -Sources all Kconfig files in the vendor directories. -\subsubsection{ cpu/Makefile.inc} -Unconditionally sources all Makefile.inc in the vendor directories. - -\subsection{cpu/$<$vendor$>$/Kconfig} -The only action currently taken is to source all Kconfig's in the -subdirectories. -\subsection{cpu/$<$vendor$>$/Makefile.inc} -{\em Conditionally} source the socket directories. -Example: -\begin{verbatim} -subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F -\end{verbatim} -. -CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file. - -\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig} -Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that -the socket, as much as possible, should control the models, because the models may plug into many sockets. -Socket\_F currently sets: -\input{socketfkconfig.tex} - -It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced. - -\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig} -CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that -if needed. -\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc} -The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional -compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all} -objects, because it is not possible to determine at build time what options may be needed for a given model CPU. -This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc. - -\subsection{northbridge} -\subsubsection{northbridge/Kconfig} -No variables. Source all vendor directory Kconfigs. -\subsubsection{northbridge/Makefile.inc} -No variables. unconditionally include all vendor Makefile.inc -\subsubsection{northbridge/$<$vendor$>$/Kconfig} -No variables. Source all chip directory Kconfigs. -\subsubsection{northbridge/$<$vendor$>$/Makefile.inc} -No variables. {\em Conditionally} include all chipset Makefile.inc. The variable -is the name of the part, e.g. -\begin{verbatim} -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8 -\end{verbatim} -. -\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig} -Typically a small number of variables. One defines the part name. Here is an example -of the variables defined for the K8. -\begin{verbatim} -config NORTHBRIDGE_AMD_AMDK8 - bool - default n - -config AGP_APERTURE_SIZE - hex - default 0x4000000 -\end{verbatim} -\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc} -Typically very small set of rules, and very simple. -Since this file is already conditionally included, -we don't need to test for the chipset CONFIG variable. We -can therefore test other variables (which is part of the reason -we set up conditional inclusion of this file, instead -of unconditionally including it). Here is an example from AMD K8. -Note that we can make a variable conditional on the ACPI tables. -\begin{verbatim} -driver-y += northbridge.o -driver-y += misc_control.o -obj-y += get_sblk_pci1234.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o -\end{verbatim} - -\subsection{southbridge} -\subsubsection{southbridge/Kconfig} -No variables. Source all vendor directory Kconfigs. -\subsubsection{southbridge/Makefile.inc} -No variables. {\em Unconditionally} include all vendor Makefile.inc -\subsubsection{southbridge/$<$vendor$>$/Kconfig} -No variables. Source all chip directory Kconfigs. -\subsubsection{southbridge/$<$vendor$>$/Makefile.inc} -No variables. {\em Conditionally} include all chipset Makefile.inc. The variable -is the name of the part, e.g. -\begin{verbatim} -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111 -\end{verbatim} -. -\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig} -Typically a small number of variables. One defines the part name. Here is an example -of the variables defined for the K8. -\begin{verbatim} -config SOUTHBRIDGE_AMD_AMD8111 - bool - default n - -\end{verbatim} -\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc} -Typically very small set of rules, and very simple. -Since this file is already conditionally included, -we don't need to test for the chipset CONFIG variable. We -can therefore test other variables (which is part of the reason -we set up conditional inclusion of this file, instead -of unconditionally including it). Here is an example from AMD 8111. -No conditionals in this one yet. -\begin{verbatim} -driver-y += amd8111.o -driver-y += amd8111_usb.o -driver-y += amd8111_lpc.o -driver-y += amd8111_ide.o -driver-y += amd8111_acpi.o -driver-y += amd8111_usb2.o -driver-y += amd8111_ac97.o -driver-y += amd8111_nic.o -driver-y += amd8111_pci.o -driver-y += amd8111_smbus.o -obj-y += amd8111_reset.o -\end{verbatim} - -\subsubsection{vendor and part} -\subsection{southbridge} -\subsubsection{vendor and part} -\subsection{superio} -\subsection{drivers/i2c} -This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed. -To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have: -\begin{verbatim} -\end{verbatim} - -\subsubsection{vendor and part} - -\end{document} diff --git a/Documentation/Makefile b/Documentation/Makefile index 0fb21f5..ed08936 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -7,7 +7,7 @@ FIGS=codeflow.pdf hypertransport.pdf -all: corebootPortingGuide.pdf Kconfig.pdf +all: corebootPortingGuide.pdf SVG2PDF=$(shell which svg2pdf) INKSCAPE=$(shell which inkscape) @@ -39,30 +39,6 @@ corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc $(PDFLATEX) corebootBuildingGuide.tex -Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex - $(PDFLATEX) $< - -# quick, somebody! make me a macro! -mainboardkconfig.tex: ../src/mainboard/Kconfig - cat beginverbatim.tex > $@ - grep '^config' $< | awk '{print $2}' >>$@ - cat endverbatim.tex >> $@ - -skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig - cat beginverbatim.tex > $@ - grep '^config' $< | awk '{print $2}' >>$@ - cat endverbatim.tex >> $@ - -cpukconfig.tex: ../src/cpu/Kconfig - cat beginverbatim.tex > $@ - grep '^config' $< | awk '{print $2}' >>$@ - cat endverbatim.tex >> $@ - -socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig - cat beginverbatim.tex > $@ - grep '^config' $< | awk '{print $2}' >>$@ - cat endverbatim.tex >> $@ - sphinx: $(MAKE) -f Makefile.sphinx html @@ -70,10 +46,10 @@ $(MAKE) -f Makefile.sphinx clean clean: clean-sphinx - rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex + rm -f *.aux *.idx *.log *.toc *.out $(FIGS) distclean: clean - rm -f corebootPortingGuide.pdf Kconfig.pdf + rm -f corebootPortingGuide.pdf livesphinx: $(MAKE) -f Makefile.sphinx livehtml -- To view, visit https://review.coreboot.org/28665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3920d002813c2838285446dc0ed8dacfa5364581 Gerrit-Change-Number: 28665 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

1 0

Change in coreboot[master]: src/lib/edid: avoid buffer overflow
by Julius Werner (Code Review) 18 Sep '18

18 Sep '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/28659 ) Change subject: src/lib/edid: avoid buffer overflow ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28659/1/src/lib/edid.c File src/lib/edid.c: https://review.coreboot.org/#/c/28659/1/src/lib/edid.c@178 PS1, Line 178: + 1 > because the type it's put in (ascii_string in edid.h) is defined the same way. Oh it just relies on the last byte always staying '\0'. I see. -- To view, visit https://review.coreboot.org/28659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3934bd6965318cdffe5c636b01b3e0c4426e8d1d Gerrit-Change-Number: 28659 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Sep 2018 20:06:22 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src/lib/edid: avoid buffer overflow
by Patrick Georgi (Code Review) 18 Sep '18

18 Sep '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/28659 ) Change subject: src/lib/edid: avoid buffer overflow ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28659/1/src/lib/edid.c File src/lib/edid.c: https://review.coreboot.org/#/c/28659/1/src/lib/edid.c@178 PS1, Line 178: + 1 > Why the +1? because the type it's put in (ascii_string in edid.h) is defined the same way. -- To view, visit https://review.coreboot.org/28659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3934bd6965318cdffe5c636b01b3e0c4426e8d1d Gerrit-Change-Number: 28659 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Sep 2018 19:59:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src/lib/edid: avoid buffer overflow
by Julius Werner (Code Review) 18 Sep '18

18 Sep '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/28659 ) Change subject: src/lib/edid: avoid buffer overflow ...................................................................... Patch Set 1: Code-Review+2 (1 comment) LGTM although I think you're off by one. https://review.coreboot.org/#/c/28659/1/src/lib/edid.c File src/lib/edid.c: https://review.coreboot.org/#/c/28659/1/src/lib/edid.c@178 PS1, Line 178: + 1 Why the +1? -- To view, visit https://review.coreboot.org/28659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3934bd6965318cdffe5c636b01b3e0c4426e8d1d Gerrit-Change-Number: 28659 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Sep 2018 19:56:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Fix coverity report
by Lijian Zhao (Code Review) 18 Sep '18

18 Sep '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28664 Change subject: soc/intel/cannonlake: Fix coverity report ...................................................................... soc/intel/cannonlake: Fix coverity report Remove const define for spd_smbus_address to fix error reported from coverity. BUG=CID 1395725 TEST=N/A Change-Id: Ib933ed872e9f85087bb3cd76a1f1e29cca75cd54 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28664/1 diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index 7a76eb0..245d2cf 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -46,7 +46,7 @@ int spd_index; struct spd_by_pointer spd_data_ptr_info; } spd_spec; - const uint8_t spd_smbus_address[4]; + uint8_t spd_smbus_address[4]; }; /* Board-specific memory dq mapping information */ -- To view, visit https://review.coreboot.org/28664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib933ed872e9f85087bb3cd76a1f1e29cca75cd54 Gerrit-Change-Number: 28664 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR
by Marshall Dawson (Code Review) 18 Sep '18

18 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28608 ) Change subject: amd/stoneyridge: Sync PSP base to MSR ...................................................................... Patch Set 1: (1 comment) It may be worth another try to ask AMD why they think the GPF occurs. https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c File src/soc/amd/stoneyridge/cpu.c: https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c@123 PS1, Line 123: setup_lapic(); > I did a small modification based on your code, and tested. […] It'd be nice to comment properly what's really needed. Did you check whether the value survived the S3 cycle? Maybe there's a lock on the register? Perhaps engaged when we call psp_notify_boot_done(), so I'd probably experiment with jamming the MSR at various times to see whether I can create a GPF. Seems unlikely that it would be writable only a single time. -- To view, visit https://review.coreboot.org/28608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Gerrit-Change-Number: 28608 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Sep 2018 18:30:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Create ampton variant
by Justin TerAvest (Code Review) 18 Sep '18

18 Sep '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/28663 Change subject: mb/google/octopus: Create ampton variant ...................................................................... mb/google/octopus: Create ampton variant This creates an ampton variant for Octopus. The initial settings were copied from Bip, but the followint changes were made to support hardware changes: * GPIO_66 is not connected (LTE). * GPIO_67 is not connected (LTE). * Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet. * Pen connection interrupts are on PEN_INT_ODL at GPIO_139. * GPIO_143 is not connected. * GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected. * EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146. * GPIO_213 is not connected. * GPIO_214 is not connected. BUG=111498206 TEST=None Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/ampton/Makefile.inc A src/mainboard/google/octopus/variants/ampton/gpio.c A src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/ampton/include/variant/ec.h A src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h A src/mainboard/google/octopus/variants/ampton/overridetree.cb 8 files changed, 449 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/28663/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3ed88bd..e0f3ff1 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -52,6 +52,7 @@ default "fleex" if BOARD_GOOGLE_FLEEX default "bobba" if BOARD_GOOGLE_BOBBA default "meep" if BOARD_GOOGLE_MEEP + default "ampton" if BOARD_GOOGLE_AMPTON default "octopus" if BOARD_GOOGLE_OCTOPUS config DEVICETREE @@ -70,6 +71,7 @@ default "Fleex" if BOARD_GOOGLE_FLEEX default "Bobba" if BOARD_GOOGLE_BOBBA default "Meep" if BOARD_GOOGLE_MEEP + default "Ampton" if BOARD_GOOGLE_AMPTON default "Octopus" if BOARD_GOOGLE_OCTOPUS config MAINBOARD_FAMILY @@ -85,6 +87,7 @@ default "FLEEX TEST 7423" if BOARD_GOOGLE_FLEEX default "BOBBA TEST 4516" if BOARD_GOOGLE_BOBBA default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP + default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS config MAX_CPUS @@ -124,6 +127,7 @@ default 9 if BOARD_GOOGLE_FLEEX default 9 if BOARD_GOOGLE_BOBBA default 9 if BOARD_GOOGLE_MEEP + default 255 if BOARD_GOOGLE_AMPTON default 255 if BOARD_GOOGLE_OCTOPUS endif # BOARD_GOOGLE_OCTOPUS diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 633a456..a6ee8d0 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -40,3 +40,9 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_AMPTON + bool "-> AMPTON" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/ampton/Makefile.inc b/src/mainboard/google/octopus/variants/ampton/Makefile.inc new file mode 100644 index 0000000..7c092e4 --- /dev/null +++ b/src/mainboard/google/octopus/variants/ampton/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/ampton/gpio.c b/src/mainboard/google/octopus/variants/ampton/gpio.c new file mode 100644 index 0000000..c7c3eec --- /dev/null +++ b/src/mainboard/google/octopus/variants/ampton/gpio.c @@ -0,0 +1,321 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + /* NORTHWEST COMMUNITY GPIOS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_0, NONE, DEEP, NF1), /* TCK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_1, DN_20K, DEEP, NF1), /* TRST_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_2, NONE, DEEP, NF1), /* TMS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_3, NONE, DEEP, NF1), /* TDI */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_4, NONE, DEEP, NF1), /* TDO */ + PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_6, UP_20K, DEEP, NF1), /* CX_PREQ_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_7, UP_20K, DEEP, NF1), /* CX_PRDY_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */ + PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ + PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA6_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA7_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_CLK_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA0_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA1_VNN 0*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA2_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA3_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA4_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA5_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA6_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA7_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_CLK_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ + PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */ + PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */ + PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */ + PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ + PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */ + PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */ + + /* PMC stays active in suspend so disable standby for these pins */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ + PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */ + PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ + PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA - unused */ + PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL - unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ + PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ + PAD_NC(GPIO_66, UP_20K), /* LTE_OFF_ODL -- unused */ + PAD_NC(GPIO_67, UP_20K), /*EN_PP3300_DX_LTE_SOC -- unused */ + PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */ + PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */ + PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */ + PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */ + PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */ + PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ + PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */ + PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ + PAD_NC(GPIO_213, UP_20K), /* TP_AP_GPIO213 -- unused */ + PAD_NC(GPIO_214, UP_20K), /* P_SENSOR_INT_L -- unused */ + + /* NORTH COMMUNITY GPIOS */ + + /* svid - unused */ + PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */ + PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */ + PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */ + + /* LPSS */ + PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ + PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */ + PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */ + PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ + PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ + PAD_NC(GPIO_84, NONE), /* LPSS_SPI_2_CLK - unused */ + PAD_NC(GPIO_85, DN_20K), /* LPSS_SPI_2_FS0 - unused */ + PAD_NC(GPIO_86, DN_20K), /* LPSS_SPI_2_FS1 - unused */ + PAD_NC(GPIO_87, DN_20K), /* LPSS_SPI_2_FS2 - unused */ + PAD_NC(GPIO_88, DN_20K), /* LPSS_SPI_2_RXD - unused */ + PAD_NC(GPIO_89, DN_20K), /* LPSS_SPI_2_TXD - unused */ + + /* Fast SPI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ + PAD_NC(GPIO_94, NATIVE),/* FST_SPI_IO2 - unused */ + PAD_NC(GPIO_95, NATIVE),/* FST_SPI_IO3 - unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ + + /* PMU Signals */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ + PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ + PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */ + + /* I2C5 - Audio */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */ + + /* I2C6 - Trackpad */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */ + + /* I2C7 - Touchscreen */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ + + /* PCIE_WAKE[0:3]_B */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ + PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ + PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */ + PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ + + /* + * PCIE_CLKREQ[0:3]_B. For unused pins, follow the termination + * guideline for unused PCIE ports as described in PDG i.e. keep + * the pins in native mode and deploy the internal pull up. + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ + + /* DDI[0:1] SDA and SCL -- unused */ + PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */ + PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */ + PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */ + PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */ + + /* Panel 0 control */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTEN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTCTL */ + + /* Hot plug detect. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ + + PAD_NC(GPIO_134, NONE),/* GPIO_134 -- EC_AP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, + DISPUPD),/* GPIO_137 -- HP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ + // Also we may be able to use eSPI WAKE# Virtual Wire instead + PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ + PAD_NC(GPIO_143, UP_20K), /* GPIO_143 - NC */ + PAD_NC(GPIO_144, UP_20K), /* GPIO_144 - PEN_EJECT */ + PAD_NC(GPIO_145, UP_20K), /* GPIO_145 - PEN_EJECT */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ + + /* + * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for + * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO + * and kept unconnected to allow S0ix entry. + */ + + /* AUDIO COMMUNITY GPIOS*/ + PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */ + PAD_NC(GPIO_157, DN_20K),/* AVS_I2S0_BCLK -- unused */ + PAD_NC(GPIO_158, DN_20K),/* AVS_I2S0_WS_SYNC -- unused */ + PAD_NC(GPIO_159, DN_20K),/* AVS_I2S0_SDI -- unused */ + PAD_NC(GPIO_160, DN_20K),/* AVS_I2S0_SDO -- unused */ + PAD_NC(GPIO_161, DN_20K),/* AVS_I2S1_MCLK -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */ + + /* Disable standby for GPIO_171 and GPIO_173 to support Wake on Voice */ + PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_A1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ + PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_1 */ + PAD_NC(GPIO_174, DN_20K), /* AVS_M_CLK_AB2 -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ + + /* SCC COMMUNITY GPIOS */ + PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */ + PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */ + PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ + PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */ + PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */ + PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */ + PAD_NC(GPIO_182, UP_20K), /* SDCARD_D1 -- unused */ + PAD_NC(GPIO_183, UP_20K), /* SDCARD_D2 -- unused */ + PAD_NC(GPIO_184, UP_20K), /* SDCARD_D3 -- unused */ + PAD_NC(GPIO_185, UP_20K), /* SDCARD_CMD -- unused */ + PAD_NC(GPIO_186, UP_20K), /* SDCARD_CD_N -- unused */ + PAD_NC(GPIO_187, NONE), /* SDCARD_LVL_WP -- unused */ + PAD_NC(GPIO_188, UP_20K), /* SDCARD_PWR_DWN_N -- unused */ + PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ + PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ + + /* + * Disable standby state for these CNVI pins to allow wake on + * WiFI & Bluetooth. + */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ + PAD_NC(GPIO_210, DN_20K), +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ + /* GSPI0_INT */ + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + DISPUPD), /* H1_PCH_INT_ODL */ + /* GSPI0_CLK */ + PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ + /* GSPI0_CS# */ + PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */ + /* GSPI0_MISO */ + PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ + /* GSPI0_MOSI */ + PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ + + /* Enable power to wifi early in bootblock and de-assert PERST#. */ + PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ + + /* + * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * pull-up for proper operation. Since there is no external pull present + * on this platform, configure an internal weak pull-up. + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, + ENPU), /* ESPI_IO1 */ +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb new file mode 100644 index 0000000..cd0ea18 --- /dev/null +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -0,0 +1,55 @@ +chip soc/intel/apollolake + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW2_02" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # - I2C 7 + end +end -- To view, visit https://review.coreboot.org/28663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3 Gerrit-Change-Number: 28663 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

1 0

Change in coreboot[master]: mb/intel/cannonlake_rvp: Move FSP param override function to separate...
by Rizwan Qureshi (Code Review) 18 Sep '18

18 Sep '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28662 Change subject: mb/intel/cannonlake_rvp: Move FSP param override function to separate file ...................................................................... mb/intel/cannonlake_rvp: Move FSP param override function to separate file Move the FSP param initialization function to a separate file. Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/Makefile.inc M src/mainboard/intel/cannonlake_rvp/romstage.c A src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c 3 files changed, 54 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/28662/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc index 7e82196..49d74a6 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -22,6 +22,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_FSP_PARAM_OVERRIDE) += romstage_fsp_params.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c index e0699da..6d9d549 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage.c @@ -13,42 +13,3 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <fsp/api.h> -#include <soc/romstage.h> -#include "spd/spd.h" -#include <string.h> -#include <spd_bin.h> - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *mem_cfg; - mem_cfg = &mupd->FspmConfig; - u8 spd_index; - - mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); - mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); - mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - spd_index = 2; - - struct region_device spd_rdev; - - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found\n"); - - mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; -} diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c new file mode 100644 index 0000000..457be7f --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include "spd/spd.h" +#include <string.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + u8 spd_index; + + mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + spd_index = 2; + + struct region_device spd_rdev; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; +} -- To view, visit https://review.coreboot.org/28662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa Gerrit-Change-Number: 28662 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Move the FSP related callbacks to separate files
by Rizwan Qureshi (Code Review) 18 Sep '18

18 Sep '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28661 Change subject: soc/intel/cannonlake: Move the FSP related callbacks to separate files ...................................................................... soc/intel/cannonlake: Move the FSP related callbacks to separate files Move funtions callbacks used to override FSP upd values to separate files. This helps in compiling SoC code without referencing the UPD structure params and hence not relying on the FSP header files being released by Intel. The code will compile with basic header files which only include the architectural FSP structures. Add a Kconfig which allows plugging in these separate files for compilation. The fact is, FSP header files are not released externally until PRQ. However the teams at intel and some partners have access to the development version of these files. To continue development on the pre-PRQ silicons and submit related code to coreboot.org, this Kconfig helps in working with UPD param overrides internally while still being to compile the code on coreboot.org without the UPD structure definition. BUG=None BRANCH=None TEST=Build for cnlrvp Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/cannonlake/romstage/Makefile.inc A src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/romstage.c 8 files changed, 285 insertions(+), 225 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/28661/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 256cf1b..5a74b6f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -75,6 +75,7 @@ select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO + select FSP_PARAM_OVERRIDE config UART_DEBUG bool "Enable UART debug port." @@ -257,4 +258,11 @@ endchoice +config FSP_PARAM_OVERRIDE + bool + default n + help + Use This should be selected if the SoC and the mainboard implement + function callbacks to populate/override the FSP UPD parameters. + endif diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 065d92b..761fe81 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += finalize.c +ramstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += gspi.c diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 30719ed..0c0a05d 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -95,43 +95,6 @@ } #endif -static void parse_devicetree(FSP_S_CONFIG *params) -{ - struct device *dev = SA_DEV_ROOT; - if (!dev) { - printk(BIOS_ERR, "Could not find root device\n"); - return; - } - - const config_t *config = dev->chip_info; - const int SerialIoDev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 - }; - - for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) { - dev = dev_find_slot(0, SerialIoDev[i]); - if (!dev->enabled) { - params->SerialIoDevMode[i] = PchSerialIoDisabled; - continue; - } - params->SerialIoDevMode[i] = PchSerialIoPci; - if (config->SerialIoDevMode[i] == PchSerialIoAcpi || - config->SerialIoDevMode[i] == PchSerialIoHidden) - params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; - } -} - void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -177,139 +140,3 @@ .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; - -/* UPD parameters to be initialized before SiliconInit */ -void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) -{ - int i; - FSP_S_CONFIG *params = &supd->FspsConfig; - FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; - - /* Parse device tree and enable/disable devices */ - parse_devicetree(params); - - /* Load VBT before devicetree-specific config. */ - params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - - /* Set USB OC pin to 0 first */ - for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { - params->Usb2OverCurrentPin[i] = 0; - } - - for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { - params->Usb3OverCurrentPin[i] = 0; - } - - mainboard_silicon_init_params(params); - - /* Unlock upper 8 bytes of RTC RAM */ - params->PchLockDownRtcMemoryLock = 0; - - /* SATA */ - params->SataEnable = config->SataEnable; - params->SataMode = config->SataMode; - params->SataSalpSupport = config->SataSalpSupport; - memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); - memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); - - /* Lan */ - params->PchLanEnable = config->PchLanEnable; - - /* Audio */ - params->PchHdaDspEnable = config->PchHdaDspEnable; - params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; - params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; - params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; - params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0; - params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1; - params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2; - params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1; - params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2; - params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3; - params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4; - - /* S0ix */ - params->PchPmSlpS0Enable = config->s0ix_enable; - - /* USB */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; - } - - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { - params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; - if (config->usb3_ports[i].tx_de_emp) { - params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; - } - if (config->usb3_ports[i].tx_downscale_amp) { - params->Usb3HsioTxDownscaleAmpEnable[i] = 1; - params->Usb3HsioTxDownscaleAmp[i] = - config->usb3_ports[i].tx_downscale_amp; - } - } - - /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = dev_find_slot(0, PCH_DEVFN_USBOTG); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; - - /* PCI Express */ - for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { - if (config->PcieClkSrcUsage[i] == 0) - config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; - } - memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, - sizeof(config->PcieClkSrcUsage)); - memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, - sizeof(config->PcieClkSrcClkReq)); - - /* eMMC and SD */ - params->ScsEmmcEnabled = config->ScsEmmcEnabled; - params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed; - if (config->EmmcHs400DllNeed == 1) { - params->PchScsEmmcHs400RxStrobeDll1 = - config->EmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll; - } - params->ScsSdCardEnabled = config->ScsSdCardEnabled; - params->ScsUfsEnabled = config->ScsUfsEnabled; - - params->Heci3Enabled = config->Heci3Enabled; - params->Device4Enable = config->Device4Enable; - params->SkipMpInit = !chip_get_fsp_mp_init(); - - /* VrConfig Settings for 5 domains - * 0 = System Agent, 1 = IA Core, 2 = Ring, - * 3 = GT unsliced, 4 = GT sliced */ - for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) - fill_vr_domain_config(params, i, &config->domain_vr_config[i]); - - /* Vt-D config */ - tconfig->VtdDisable = config->VtdDisable; -} - -/* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c new file mode 100644 index 0000000..4b983d6 --- /dev/null +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <chip.h> +#include <compiler.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <intelblocks/xdci.h> +#include <soc/intel/common/vbt.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <string.h> + +static void parse_devicetree(FSP_S_CONFIG *params) +{ + struct device *dev = SA_DEV_ROOT; + if (!dev) { + printk(BIOS_ERR, "Could not find root device\n"); + return; + } + + const config_t *config = dev->chip_info; + const int SerialIoDev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 + }; + + for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) { + dev = dev_find_slot(0, SerialIoDev[i]); + if (!dev->enabled) { + params->SerialIoDevMode[i] = PchSerialIoDisabled; + continue; + } + params->SerialIoDevMode[i] = PchSerialIoPci; + if (config->SerialIoDevMode[i] == PchSerialIoAcpi || + config->SerialIoDevMode[i] == PchSerialIoHidden) + params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; + } +} + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + int i; + FSP_S_CONFIG *params = &supd->FspsConfig; + FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + struct device *dev = SA_DEV_ROOT; + config_t *config = dev->chip_info; + + /* Parse device tree and enable/disable devices */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + /* Set USB OC pin to 0 first */ + for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { + params->Usb2OverCurrentPin[i] = 0; + } + + for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { + params->Usb3OverCurrentPin[i] = 0; + } + + mainboard_silicon_init_params(params); + + /* Unlock upper 8 bytes of RTC RAM */ + params->PchLockDownRtcMemoryLock = 0; + + /* SATA */ + params->SataEnable = config->SataEnable; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + + /* Lan */ + params->PchLanEnable = config->PchLanEnable; + + /* Audio */ + params->PchHdaDspEnable = config->PchHdaDspEnable; + params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; + params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; + params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; + params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0; + params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1; + params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2; + params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1; + params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2; + params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3; + params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4; + + /* S0ix */ + params->PchPmSlpS0Enable = config->s0ix_enable; + + /* USB */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = + config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = + config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = + config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = + config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = + config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = + config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + + /* PCI Express */ + for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { + if (config->PcieClkSrcUsage[i] == 0) + config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; + } + memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + /* eMMC and SD */ + params->ScsEmmcEnabled = config->ScsEmmcEnabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed; + if (config->EmmcHs400DllNeed == 1) { + params->PchScsEmmcHs400RxStrobeDll1 = + config->EmmcHs400RxStrobeDll1; + params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll; + } + params->ScsSdCardEnabled = config->ScsSdCardEnabled; + params->ScsUfsEnabled = config->ScsUfsEnabled; + + params->Heci3Enabled = config->Heci3Enabled; + params->Device4Enable = config->Device4Enable; + params->SkipMpInit = !chip_get_fsp_mp_init(); + + /* VrConfig Settings for 5 domains + * 0 = System Agent, 1 = IA Core, 2 = Ring, + * 3 = GT unsliced, 4 = GT sliced */ + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(params, i, &config->domain_vr_config[i]); + + /* Vt-D config */ + tconfig->VtdDisable = config->VtdDisable; +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index 9ea60ae..6faf110 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -18,6 +18,7 @@ #define _SOC_ROMSTAGE_H_ #include <arch/cpu.h> +#include <chip.h> #include <fsp/api.h> void mainboard_memory_init_params(FSPM_UPD *mupd); diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index 99bc25f..ab3e8e2 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -15,4 +15,5 @@ romstage-y += power_state.c romstage-y += romstage.c +romstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c romstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c new file mode 100644 index 0000000..67aa0ec --- /dev/null +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <chip.h> +#include <console/console.h> +#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) +{ + unsigned int i; + uint32_t mask = 0; + + /* Set IGD stolen size to 64MB. */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable Cpu Ratio Override temporary. */ + m_cfg->CpuRatio = 0; + m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; + /* Disable Vmx if Vt-d is already disabled */ + if (config->VtdDisable) + m_cfg->VmxEnable = 0; + else + m_cfg->VmxEnable = config->VmxEnable; +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + assert(dev != NULL); + const config_t *config = dev->chip_info; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg, config); + + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = config->DebugConsent; + + mainboard_memory_init_params(mupd); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* Do nothing */ +} diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index ae1ba4d..113798d 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -146,55 +146,3 @@ run_postcar_phase(&pcf); } - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) -{ - unsigned int i; - uint32_t mask = 0; - - /* Set IGD stolen size to 64MB. */ - m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->RMT; - - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = config->PrmrrSize; - m_cfg->EnableC6Dram = config->enable_c6dram; - /* Disable Cpu Ratio Override temporary. */ - m_cfg->CpuRatio = 0; - m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; - /* Disable Vmx if Vt-d is already disabled */ - if (config->VtdDisable) - m_cfg->VmxEnable = 0; - else - m_cfg->VmxEnable = config->VmxEnable; -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); - assert(dev != NULL); - const config_t *config = dev->chip_info; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - soc_memory_init_params(m_cfg, config); - - /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; - - mainboard_memory_init_params(mupd); -} - -__weak void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - /* Do nothing */ -} -- To view, visit https://review.coreboot.org/28661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e Gerrit-Change-Number: 28661 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: driver/intel/fsp2_0: Add weak functions for fsp param initialization
by Rizwan Qureshi (Code Review) 18 Sep '18

18 Sep '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28660 Change subject: driver/intel/fsp2_0: Add weak functions for fsp param initialization ...................................................................... driver/intel/fsp2_0: Add weak functions for fsp param initialization Add weak functions for callbacks that should be implementted by SoC. This loosens the contraint on the SoC for implementing these. This helps with building platforms without requiring the full FSP upd header files e.g., SoCs for which FSP is still under development. The header files can only contain architectural FSP structures excluding the SoC related structures. Change-Id: I5ecf1d5e16b8478394975e369e1006e218890655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/28660/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index accb70b..ba7413e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -411,3 +411,9 @@ do_fsp_memory_init(&hdr, s3wake, &memmap); } + +__weak void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, + uint32_t version) +{ + /* Do Nothing */ +} diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0461b68..b51ff43 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -127,3 +127,8 @@ fsps_load(s3wake); do_silicon_init(&fsps_hdr); } + +__weak void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + /* Do Nothing */ +} -- To view, visit https://review.coreboot.org/28660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5ecf1d5e16b8478394975e369e1006e218890655 Gerrit-Change-Number: 28660 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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coreboot-gerrit September 2018