coreboot-gerrit September 2018

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Change in coreboot[master]: arch/{mips, power8}/include/arch: Don't use device_t
by Elyes HAOUAS (Code Review) 19 Sep '18

19 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28675 Change subject: arch/{mips,power8}/include/arch: Don't use device_t ...................................................................... arch/{mips,power8}/include/arch: Don't use device_t Use of device_t is deprecated. Change-Id: I8790bc333caa367ef46bf80b5fecc3e90ef89ca0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/mips/include/arch/cpu.h M src/arch/power8/include/arch/cpu.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28675/1 diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index f9f6197..8e35908 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -30,7 +30,7 @@ struct thread; struct cpu_info { - device_t cpu; + struct device *cpu; unsigned long index; }; diff --git a/src/arch/power8/include/arch/cpu.h b/src/arch/power8/include/arch/cpu.h index e0fb72c..a4421e5 100644 --- a/src/arch/power8/include/arch/cpu.h +++ b/src/arch/power8/include/arch/cpu.h @@ -29,7 +29,7 @@ struct thread; struct cpu_info { - device_t cpu; + struct device *cpu; unsigned long index; #if IS_ENABLED(CONFIG_COOP_MULTITASKING) struct thread *thread; -- To view, visit https://review.coreboot.org/28675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8790bc333caa367ef46bf80b5fecc3e90ef89ca0 Gerrit-Change-Number: 28675 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/intel/cannonlake: [WIP] Make FSP completely optional
by Rizwan Qureshi (Code Review) 19 Sep '18

19 Sep '18

Rizwan Qureshi has uploaded a new patch set (#2). ( https://review.coreboot.org/28674 ) Change subject: soc/intel/cannonlake: [WIP] Make FSP completely optional ...................................................................... soc/intel/cannonlake: [WIP] Make FSP completely optional Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/lib/coreboot_table.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/cpu.c A src/soc/intel/cannonlake/fsp_igd_bar.c A src/soc/intel/cannonlake/fsp_rst_handle.c M src/soc/intel/cannonlake/graphics.c M src/soc/intel/cannonlake/include/soc/ramstage.h M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/reset.c M src/soc/intel/cannonlake/romstage/Makefile.inc A src/soc/intel/cannonlake/romstage/dimminfo.c A src/soc/intel/cannonlake/romstage/dimminfo.h A src/soc/intel/cannonlake/romstage/meminit.c A src/soc/intel/cannonlake/romstage/meminit.h M src/soc/intel/cannonlake/romstage/romstage.c A src/soc/intel/cannonlake/siliconinit.c A src/soc/intel/cannonlake/siliconinit.h M src/soc/intel/cannonlake/vr_config.c A src/soc/intel/common/basecode/include/intelbasecode/memmap.h 24 files changed, 325 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28674/2 -- To view, visit https://review.coreboot.org/28674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee Gerrit-Change-Number: 28674 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: [WIP] Make FSP optional Completely
by Rizwan Qureshi (Code Review) 19 Sep '18

19 Sep '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28674 Change subject: soc/intel/cannonlake: [WIP] Make FSP optional Completely ...................................................................... soc/intel/cannonlake: [WIP] Make FSP optional Completely Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/lib/coreboot_table.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/cpu.c A src/soc/intel/cannonlake/fsp_igd_bar.c A src/soc/intel/cannonlake/fsp_rst_handle.c M src/soc/intel/cannonlake/graphics.c M src/soc/intel/cannonlake/include/soc/ramstage.h M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/reset.c M src/soc/intel/cannonlake/romstage/Makefile.inc A src/soc/intel/cannonlake/romstage/dimminfo.c A src/soc/intel/cannonlake/romstage/dimminfo.h A src/soc/intel/cannonlake/romstage/meminit.c A src/soc/intel/cannonlake/romstage/meminit.h M src/soc/intel/cannonlake/romstage/romstage.c A src/soc/intel/cannonlake/siliconinit.c A src/soc/intel/cannonlake/siliconinit.h M src/soc/intel/cannonlake/vr_config.c A src/soc/intel/common/basecode/include/intelbasecode/memmap.h 24 files changed, 325 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28674/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 62b3aaa..c83ff76 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -603,3 +603,8 @@ cbmem_list(); return (void *)cbtable_start; } + +int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + die ("platform does not implement fill_lb_framebuffer"); +} diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5a74b6f..9152ee7 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -30,7 +30,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM +# select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select GENERIC_GPIO_LIB @@ -46,7 +46,7 @@ select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK - select PLATFORM_USES_FSP2_0 +# select PLATFORM_USES_FSP2_0 select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT @@ -74,8 +74,9 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING - select DISPLAY_FSP_VERSION_INFO - select FSP_PARAM_OVERRIDE +# select DISPLAY_FSP_VERSION_INFO +# select FSP_PARAM_OVERRIDE + select SOC_INTEL_COMMON_BASECODE config UART_DEBUG bool "Enable UART debug port." diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 761fe81..c453dc0 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -23,6 +23,7 @@ bootblock-$(CONFIG_UART_DEBUG) += uart.c romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_rst_handle.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c @@ -37,6 +38,7 @@ ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += finalize.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_rst_handle.c ramstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c @@ -55,8 +57,9 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c -ramstage-y += vr_config.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += vr_config.c ramstage-y += sd.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += siliconinit.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0c0a05d..4c2f5e5 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -18,8 +18,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/api.h> -#include <fsp/util.h> #include <intelblocks/acpi.h> #include <intelblocks/chip.h> #include <intelblocks/xdci.h> @@ -28,6 +26,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> +#include "siliconinit.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) @@ -98,10 +97,10 @@ void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + silicon_init(romstage_handoff_is_resume()); /* Display FIRMWARE_VERSION_INFO_HOB */ - fsp_display_fvi_version_hob(); + display_fvi_version_hob(); } static void pci_domain_set_resources(struct device *dev) @@ -140,3 +139,13 @@ .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; + +__weak void display_fvi_version_hob(void) +{ + die("No FSP to run display_fvi_version_hob"); +} + +__weak void silicon_init(bool s3wake) +{ + die("No FSP to run silicon_init"); +} diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ba87045..a59530c 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -28,10 +28,11 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smm.h> +#include "siliconinit.h" static void soc_fsp_load(void) { - fsps_load(romstage_handoff_is_resume()); + soc_fsps_load(romstage_handoff_is_resume()); } static void configure_isst(void) @@ -239,3 +240,8 @@ if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } + +__weak void soc_fsps_load(bool s3wake) +{ + die ("No FSP to run fsps_load"); +} diff --git a/src/soc/intel/cannonlake/fsp_igd_bar.c b/src/soc/intel/cannonlake/fsp_igd_bar.c new file mode 100644 index 0000000..ae81189 --- /dev/null +++ b/src/soc/intel/cannonlake/fsp_igd_bar.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <intelblocks/graphics.h> + +uintptr_t fsp_soc_get_igd_bar(void) +{ + return graphics_get_memory_base(); +} diff --git a/src/soc/intel/cannonlake/fsp_rst_handle.c b/src/soc/intel/cannonlake/fsp_rst_handle.c new file mode 100644 index 0000000..8069a1e --- /dev/null +++ b/src/soc/intel/cannonlake/fsp_rst_handle.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <reset.h> + +void chipset_handle_reset(uint32_t status) +{ + switch (status) { + case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ + printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); + do_global_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 58f87f7..bae9dd5 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -16,18 +16,12 @@ #include <arch/acpigen.h> #include <console/console.h> -#include <fsp/util.h> #include <device/device.h> #include <device/pci.h> #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> -uintptr_t fsp_soc_get_igd_bar(void) -{ - return graphics_get_memory_base(); -} - void graphics_soc_init(struct device *dev) { uint32_t ddi_buf_ctl; diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 4a96185..e3953d2 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -19,10 +19,13 @@ #include <chip.h> #include <device/device.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) #include <fsp/api.h> #include <fsp/util.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params); +#endif + void soc_init_pre_device(void *chip_info); #endif diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index 6faf110..a846e26 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -19,9 +19,13 @@ #include <arch/cpu.h> #include <chip.h> + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) #include <fsp/api.h> void mainboard_memory_init_params(FSPM_UPD *mupd); +#endif + void systemagent_early_init(void); /* Board type */ diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index 9121ac3..69766c8 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -19,7 +19,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <intelbasecode/memmap.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 385767d..b993782 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -18,8 +18,6 @@ #ifndef _SOC_VR_CONFIG_H_ #define _SOC_VR_CONFIG_H_ -#include <fsp/api.h> - struct vr_config { /* The below settings will take effect when this is set to 1 diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..aa037f0 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/util.h> +#include <intelbasecode/memmap.h> #include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index 140fbff..bc3d82b 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> -#include <fsp/util.h> #include <reset.h> #include <string.h> #include <timer.h> @@ -88,17 +87,3 @@ pmc_global_reset_enable(1); hard_reset(); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - do_global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index ab3e8e2..195e7aa 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -17,3 +17,4 @@ romstage-y += romstage.c romstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c romstage-y += systemagent.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += meminit.c diff --git a/src/soc/intel/cannonlake/romstage/dimminfo.c b/src/soc/intel/cannonlake/romstage/dimminfo.c new file mode 100644 index 0000000..2110540 --- /dev/null +++ b/src/soc/intel/cannonlake/romstage/dimminfo.c @@ -0,0 +1,90 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dimminfo.h" +#include <fsp/util.h> + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (src_dimm->Status != DIMM_PRESENT) + continue; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + memory_info_hob->DataWidth); + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} diff --git a/src/soc/intel/cannonlake/romstage/dimminfo.h b/src/soc/intel/cannonlake/romstage/dimminfo.h new file mode 100644 index 0000000..237b331 --- /dev/null +++ b/src/soc/intel/cannonlake/romstage/dimminfo.h @@ -0,0 +1 @@ +void save_dimm_info(void); diff --git a/src/soc/intel/cannonlake/romstage/meminit.c b/src/soc/intel/cannonlake/romstage/meminit.c new file mode 100644 index 0000000..b956482 --- /dev/null +++ b/src/soc/intel/cannonlake/romstage/meminit.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/early_variables.h> +#include <assert.h> +#include <chip.h> +#include <cpu/x86/mtrr.h> +#include <cbmem.h> +#include <compiler.h> +#include <console/console.h> +#include <fsp/api.h> +#include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> +#include <memory_info.h> +#include <soc/intel/common/smbios.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <string.h> +#include <timestamp.h> +#include "meminit.h" + +void memory_init(bool s3wake) +{ + fsp_memory_init(s3wake); +} diff --git a/src/soc/intel/cannonlake/romstage/meminit.h b/src/soc/intel/cannonlake/romstage/meminit.h new file mode 100644 index 0000000..233948b --- /dev/null +++ b/src/soc/intel/cannonlake/romstage/meminit.h @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +void memory_init(bool s3wake); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 113798d..071c6cc 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -21,7 +21,6 @@ #include <cbmem.h> #include <compiler.h> #include <console/console.h> -#include <fsp/util.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> #include <memory_info.h> @@ -32,81 +31,11 @@ #include <soc/romstage.h> #include <string.h> #include <timestamp.h> +#include "meminit.h" +#include "dimminfo.h" static struct chipset_power_state power_state CAR_GLOBAL; -#define FSP_SMBIOS_MEMORY_INFO_GUID \ -{ \ - 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ - 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ -} - -/* Save the DIMM information for SMBIOS table 17 */ -static void save_dimm_info(void) -{ - int channel, dimm, dimm_max, index; - size_t hob_size; - const CONTROLLER_INFO *ctrlr_info; - const CHANNEL_INFO *channel_info; - const DIMM_INFO *src_dimm; - struct dimm_info *dest_dimm; - struct memory_info *mem_info; - const MEMORY_INFO_DATA_HOB *memory_info_hob; - const uint8_t smbios_memory_info_guid[16] = - FSP_SMBIOS_MEMORY_INFO_GUID; - - /* Locate the memory info HOB, presence validated by raminit */ - memory_info_hob = fsp_find_extension_hob_by_guid( - smbios_memory_info_guid, - &hob_size); - if (memory_info_hob == NULL || hob_size == 0) { - printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); - return; - } - - /* - * Allocate CBMEM area for DIMM information used to populate SMBIOS - * table 17 - */ - mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - if (mem_info == NULL) { - printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); - return; - } - memset(mem_info, 0, sizeof(*mem_info)); - - /* Describe the first N DIMMs in the system */ - index = 0; - dimm_max = ARRAY_SIZE(mem_info->dimm); - ctrlr_info = &memory_info_hob->Controller[0]; - for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { - channel_info = &ctrlr_info->ChannelInfo[channel]; - if (channel_info->Status != CHANNEL_PRESENT) - continue; - for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { - src_dimm = &channel_info->DimmInfo[dimm]; - dest_dimm = &mem_info->dimm[index]; - - if (src_dimm->Status != DIMM_PRESENT) - continue; - - /* Populate the DIMM information */ - dimm_info_fill(dest_dimm, - src_dimm->DimmCapacity, - memory_info_hob->MemoryType, - memory_info_hob->ConfiguredMemoryClockSpeed, - channel_info->ChannelId, - src_dimm->DimmId, - (const char *)src_dimm->ModulePartNum, - sizeof(src_dimm->ModulePartNum), - memory_info_hob->DataWidth); - index++; - } - } - mem_info->dimm_cnt = index; - printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); -} - asmlinkage void car_stage_entry(void) { bool s3wake; @@ -123,7 +52,7 @@ timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); + memory_init(s3wake); pmc_set_disb(); if (!s3wake) save_dimm_info(); @@ -146,3 +75,13 @@ run_postcar_phase(&pcf); } + +__weak void save_dimm_info() +{ + printk(BIOS_ERR, "%s weak function called\n", __func__); +} + +__weak void memory_init(bool s3wake) +{ + die("No FSP to run memory_init"); +} diff --git a/src/soc/intel/cannonlake/siliconinit.c b/src/soc/intel/cannonlake/siliconinit.c new file mode 100644 index 0000000..892c2ff --- /dev/null +++ b/src/soc/intel/cannonlake/siliconinit.c @@ -0,0 +1,18 @@ +#include <fsp/api.h> +#include <fsp/util.h> +#include "siliconinit.h" + +void silicon_init(bool s3wake) +{ + fsp_silicon_init(s3wake); +} + +void display_fvi_version_hob(void) +{ + fsp_display_fvi_version_hob(); +} + +void soc_fsps_load(bool s3wake) +{ + fsps_load(s3wake); +} diff --git a/src/soc/intel/cannonlake/siliconinit.h b/src/soc/intel/cannonlake/siliconinit.h new file mode 100644 index 0000000..dad9026 --- /dev/null +++ b/src/soc/intel/cannonlake/siliconinit.h @@ -0,0 +1,3 @@ +void silicon_init(bool s3wake); +void display_fvi_version_hob(void); +void soc_fsps_load(bool s3wake); diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index fff68c7..5aa36d5 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -14,7 +14,6 @@ * */ -#include <fsp/api.h> #include <soc/ramstage.h> #include <soc/vr_config.h> diff --git a/src/soc/intel/common/basecode/include/intelbasecode/memmap.h b/src/soc/intel/common/basecode/include/intelbasecode/memmap.h new file mode 100644 index 0000000..965bce6 --- /dev/null +++ b/src/soc/intel/common/basecode/include/intelbasecode/memmap.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _COMMON_MEMMAP_H_ +#define _COMMON_MEMMAP_H_ + +#include <types.h> + +/* + * mmap_region_granularity must to return a size which is a positive non-zero + * integer multiple of the SMM size when SMM is in use. When not using SMM, + * this value should be set to 8 MiB. + */ +size_t mmap_region_granularity(void); + +/* Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. */ +void smm_region(void **start, size_t *size); + +enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* Fills in the start and size for the requested SMM subregion. Returns + * 0 on susccess, < 0 on failure. */ +int smm_subregion(int sub, void **start, size_t *size); + +#endif /* _COMMON_MEMMAP_H_ */ -- To view, visit https://review.coreboot.org/28674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee Gerrit-Change-Number: 28674 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: sb/intel/common/firmware: Ensure warning is put late
by Nico Huber (Code Review) 19 Sep '18

19 Sep '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28673 Change subject: sb/intel/common/firmware: Ensure warning is put late ...................................................................... sb/intel/common/firmware: Ensure warning is put late Change-Id: I400de0a622c2b45ea5ef1f1446f4f489ac397c32 --- M src/southbridge/intel/common/firmware/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28673/1 diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 01a8061..774bb23 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -23,7 +23,7 @@ ifeq ($(CONFIG_HAVE_IFD_BIN),y) INTERMEDIATE+=add_intel_firmware else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) -INTERMEDIATE += warn_intel_firmware +files_added:: warn_intel_firmware endif IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) @@ -89,7 +89,7 @@ warn_intel_firmware: printf "\n\t** WARNING **\n" - printf "coreboot will be built without an Intel Firmware Descriptor.\n" + printf "coreboot has been built without an Intel Firmware Descriptor.\n" printf "Never write a complete coreboot.rom without an IFD to your\n" printf "board's flash chip! You can use flashrom's IFD or layout\n" printf "parameters to flash only to the BIOS region.\n\n" -- To view, visit https://review.coreboot.org/28673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I400de0a622c2b45ea5ef1f1446f4f489ac397c32 Gerrit-Change-Number: 28673 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: fsp_broadwell_de: Add fixed VT-d MMIO range to the resources
by Werner Zeh (Code Review) 19 Sep '18

19 Sep '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/28672 Change subject: fsp_broadwell_de: Add fixed VT-d MMIO range to the resources ...................................................................... fsp_broadwell_de: Add fixed VT-d MMIO range to the resources FSP initializes the VT-d feature on Broadwell-DE and assigns an address space to the MMIO range. coreboots resource allocator needs to be aware of this fixed resource as otherwise the address can be assigned to a different PCI device. In this case addresses are overlapped and the VT-d range is not accessible any more. To deal with it the right way add a fixed MMIO resource to the resources list if VT-d BAR is enabled. Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h M src/soc/intel/fsp_broadwell_de/vtd.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28672/1 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h index dc1ec19..670a68f 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h @@ -20,6 +20,7 @@ #define VTBAR_OFFSET 0x180 #define VTBAR_MASK 0xffffe000 +#define VTBAR_SIZE 0x2000 #define SMM_FEATURE_CONTROL 0x58 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/fsp_broadwell_de/vtd.c b/src/soc/intel/fsp_broadwell_de/vtd.c index eccfdfb..9fb46c1 100644 --- a/src/soc/intel/fsp_broadwell_de/vtd.c +++ b/src/soc/intel/fsp_broadwell_de/vtd.c @@ -20,12 +20,22 @@ #include <device/pci_ids.h> #include <soc/pci_devs.h> #include <soc/acpi.h> +#include <soc/broadwell_de.h> static void vtd_read_resources(struct device *dev) { + uint32_t vtbar; + /* Call the normal read_resources */ pci_dev_read_resources(dev); + /* Add fixed MMIO resource for VT-d which was set up by the FSP. */ + vtbar = pci_read_config32(dev, VTBAR_OFFSET); + /* Make sure VT-d is enabled before adding the resource. */ + if (vtbar & 0x01) { + mmio_resource(dev, VTBAR_OFFSET, + (vtbar & VTBAR_MASK) >> 10, VTBAR_SIZE >> 10); + } } static struct device_operations vtd_ops = { -- To view, visit https://review.coreboot.org/28672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098 Gerrit-Change-Number: 28672 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: fsp_broadwell_de: Move DMAR table generation to belonging VT-d device
by Werner Zeh (Code Review) 19 Sep '18

19 Sep '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/28671 Change subject: fsp_broadwell_de: Move DMAR table generation to belonging VT-d device ...................................................................... fsp_broadwell_de: Move DMAR table generation to belonging VT-d device The DMAR table generation depends on the VT-d feature which is implemented in its own PCI device (for Broadwell-DE it is PCI:00:05.0). Add a new PCI driver for this device and move DMAR table generation to this device driver. Change-Id: I103257c73f5e745e996a441a2535b885270bc204 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/include/soc/acpi.h M src/soc/intel/fsp_broadwell_de/northcluster.c A src/soc/intel/fsp_broadwell_de/vtd.c 5 files changed, 47 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28671/1 diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 386adc1..9312663 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += iou_complto.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += vtd.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 5d65477..b99cc49 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -390,15 +390,14 @@ return current; } -unsigned long northcluster_write_acpi_tables(struct device *const dev, +unsigned long vtd_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { acpi_dmar_t *const dmar = (acpi_dmar_t *)current; - struct device *vtdev = dev_find_slot(0, PCI_DEVFN(5, 0)); /* Create DMAR table only if virtualization is enabled */ - if (!(pci_read_config32(vtdev, 0x180) & 0x01)) + if (!(pci_read_config32(dev, VTBAR_OFFSET) & 0x01)) return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h index da552cc..dce267a 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h @@ -24,7 +24,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); uint16_t get_pmbase(void); -unsigned long northcluster_write_acpi_tables(struct device *const dev, +unsigned long vtd_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp); diff --git a/src/soc/intel/fsp_broadwell_de/northcluster.c b/src/soc/intel/fsp_broadwell_de/northcluster.c index 7090370..8da41d4 100644 --- a/src/soc/intel/fsp_broadwell_de/northcluster.c +++ b/src/soc/intel/fsp_broadwell_de/northcluster.c @@ -137,7 +137,6 @@ static struct device_operations nc_ops = { .read_resources = nc_read_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, - .write_acpi_tables = northcluster_write_acpi_tables, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = NULL, diff --git a/src/soc/intel/fsp_broadwell_de/vtd.c b/src/soc/intel/fsp_broadwell_de/vtd.c new file mode 100644 index 0000000..eccfdfb --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/vtd.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2016 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/acpi.h> + + +static void vtd_read_resources(struct device *dev) +{ + /* Call the normal read_resources */ + pci_dev_read_resources(dev); +} + +static struct device_operations vtd_ops = { + .read_resources = vtd_read_resources, + .write_acpi_tables = vtd_write_acpi_tables, + .set_resources = pci_dev_set_resources, + .scan_bus = 0, + .ops_pci = 0, +}; + +static const struct pci_driver vtd_driver __pci_driver = { + .ops = &vtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = VTD_DEVID, +}; -- To view, visit https://review.coreboot.org/28671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I103257c73f5e745e996a441a2535b885270bc204 Gerrit-Change-Number: 28671 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: google/kukui: Set up EC_IN_RW GPIO for ChromeOS
by Tristan Hsieh (Code Review) 19 Sep '18

19 Sep '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28670 Change subject: google/kukui: Set up EC_IN_RW GPIO for ChromeOS ...................................................................... google/kukui: Set up EC_IN_RW GPIO for ChromeOS Set up EC_IN_RW GPIO to boot depthcharge. Without this patch, depthcharge will fail to tell if the EC firmware is RW. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC_IN_RW GPIO. Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/kukui/gpio.h 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28670/1 diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 9184d88..bb14b1c 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -21,12 +21,14 @@ void setup_chromeos_gpios(void) { + gpio_input_pullup(EC_IN_RW); gpio_input_pullup(EC_IRQ); } void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { + {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h index cb9ad24..a2f7760 100644 --- a/src/mainboard/google/kukui/gpio.h +++ b/src/mainboard/google/kukui/gpio.h @@ -18,7 +18,8 @@ #include <soc/gpio.h> -#define EC_IRQ GPIO(PERIPHERAL_EN1) +#define EC_IRQ GPIO(PERIPHERAL_EN1) +#define EC_IN_RW GPIO(PERIPHERAL_EN14) void setup_chromeos_gpios(void); -- To view, visit https://review.coreboot.org/28670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25 Gerrit-Change-Number: 28670 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Pha...
by Peichao Li (Code Review) 19 Sep '18

19 Sep '18

Peichao Li has uploaded a new patch set (#5). ( https://review.coreboot.org/28669 ) Change subject: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Phaseer ...................................................................... mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Phaseer Since I2C bus 7 attached the touchscreen device however Phaser units that haven't it. So for avoiding side effects, we need close I2C bus 7 SCL and SDA respectilvely. BUG= TEST=according to sku_id(Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3) distinguish whether close these gpios. Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/phaser/gpio.c 1 file changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28669/5 -- To view, visit https://review.coreboot.org/28669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Gerrit-Change-Number: 28669 Gerrit-PatchSet: 5 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>

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Change in coreboot[master]: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Pha...
by Peichao Li (Code Review) 19 Sep '18

19 Sep '18

Peichao Li has uploaded a new patch set (#4). ( https://review.coreboot.org/28669 ) Change subject: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Phaseer ...................................................................... mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Phaseer Since I2C bus 7 attached the touchscreen device however Phaser units that haven't it. So for avoiding side effects, we need close I2C bus 7 SCL and SDA respectilvely. BUG= TEST=according to sku_id(Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3) distinguish whether close these gpios. Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/phaser/gpio.c 1 file changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28669/4 -- To view, visit https://review.coreboot.org/28669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Gerrit-Change-Number: 28669 Gerrit-PatchSet: 4 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>

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Change in coreboot[master]: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Pha...
by Peichao Li (Code Review) 19 Sep '18

19 Sep '18

Peichao Li has uploaded a new patch set (#3). ( https://review.coreboot.org/28669 ) Change subject: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Phaseer ...................................................................... mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Phaseer Since I2C bus 7 attached the touchscreen device however Phaser units that haven't it. So for avoiding side effects, we need close I2C bus 7 SCL and SDA respectilvely. BUG= TEST=according to sku_id(Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3) distinguish whether close these gpios. Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/phaser/gpio.c 1 file changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28669/3 -- To view, visit https://review.coreboot.org/28669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Gerrit-Change-Number: 28669 Gerrit-PatchSet: 3 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>

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coreboot-gerrit September 2018