dhaval v sharma has uploaded this change for review. ( https://review.coreboot.org/28696
Change subject: soc/intel/skylake: Make usage of SMI optional where possible
......................................................................
soc/intel/skylake: Make usage of SMI optional where possible
Make usage of SMI optional where possible 3 different
hooks provided as such:
1. Most modern OSes are ACPI aware-avoid ACPI switch SMI if
possible.
2. Avoid finalize soc SMI. Most finalize implementation
can be done in normal code.
3. Do not need to disable ACPI during boot - leave it
enabled through boot.
Note: With reduced SMI PWRBTN event based graceful shutdown
will not work until OS is booted.
BUG=None
BRANCH=None
TEST=Booted Soraka with option enabled/disabled.
Change-Id: I3f0c64b15ed6d0854ff350fcd75d299e45c23f18
Signed-off-by: Dhaval <dhaval.v.sharma(a)intel.com>
---
M src/ec/google/chromeec/ec.c
M src/soc/intel/common/block/smm/Kconfig
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/pmc.c
5 files changed, 26 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28696/1
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 09550d5..f2f4e0d 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -474,9 +474,6 @@
while (google_chromeec_get_event() != 0)
;
- /* Restore SCI event mask. */
- google_chromeec_set_sci_mask(info->sci_events);
-
} else {
google_chromeec_set_smi_mask(info->smi_events);
@@ -489,6 +486,13 @@
info->s3_wake_events,
info->s0ix_wake_events);
}
+ /* Should be okay to set sci mask for s0 path also because
+ * anyways SCI interrupt gets enabled later during finalize
+ * stage and ACPI_DISABLE calls can explicitely disable it
+ * as required this helps with SMI_REDUCED implementation*/
+
+ google_chromeec_set_sci_mask(info->sci_events);
+
/* Clear wake event mask. */
google_chromeec_set_wake_mask(0);
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index 909382e..064d4d8 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -16,3 +16,9 @@
Time in milliseconds that SLP_SMI for S5 waits for before
enabling sleep. This is required to avoid any race between
SLP_SMI and PWRBTN SMI.
+
+config REDUCED_SMI
+ bool "Reduce SMI usage during boot"
+ default n
+ help
+ Reduce SMI usage
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index d2ec7e7..5f018ef 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -244,7 +244,13 @@
fadt->header.revision = get_acpi_table_revision(FADT);
fadt->sci_int = acpi_sci_irq();
- fadt->smi_cmd = APM_CNT;
+
+ if (IS_ENABLED(CONFIG_REDUCED_SMI))
+ /* ACPI 2.0: if SMI_CMD in FADT is zero no SMI transitions supported */
+ fadt->smi_cmd = 0;
+ else
+ fadt->smi_cmd = APM_CNT;
+
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->s4bios_req = 0x0;
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 4c8a129..996088d 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -144,9 +144,10 @@
soc_lockdown(dev);
- printk(BIOS_DEBUG, "Finalizing SMM.\n");
- outb(APM_CNT_FINALIZE, APM_CNT);
-
+ if (!IS_ENABLED(CONFIG_REDUCED_SMI)){
+ printk(BIOS_DEBUG, "Finalizing SMM.\n");
+ outb(APM_CNT_FINALIZE, APM_CNT);
+ }
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);
}
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index a2623d9..4f77414 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -190,7 +190,8 @@
/* Note that certain bits may be cleared from running script as
* certain bit fields are write 1 to clear. */
reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
- pmc_set_acpi_mode();
+ if (!IS_ENABLED(CONFIG_REDUCED_SMI))
+ pmc_set_acpi_mode();
config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3f0c64b15ed6d0854ff350fcd75d299e45c23f18
Gerrit-Change-Number: 28696
Gerrit-PatchSet: 1
Gerrit-Owner: dhaval v sharma <dhaval.v.sharma(a)intel.com>
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28694
Change subject: soc/intel/common/block: Don't use device_t
......................................................................
soc/intel/common/block: Don't use device_t
Use of device_t is deprecated.
Change-Id: Id82059898844fbe20665250062b67652d6cc1f9e
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/soc/intel/common/block/include/intelblocks/smihandler.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/28694/1
diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index 197268b..050d93a 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -155,7 +155,7 @@
* This function returns a 1 or 0 depending on whether disable_busmaster
* needs to be done for the specified device on S5 entry
*/
-int smihandler_soc_disable_busmaster(device_t dev);
+int smihandler_soc_disable_busmaster(pci_devfn_t dev);
/* SMI handlers that should be serviced in SCI mode too. */
uint32_t smihandler_soc_get_sci_mask(void);
--
To view, visit https://review.coreboot.org/28694
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id82059898844fbe20665250062b67652d6cc1f9e
Gerrit-Change-Number: 28694
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>