coreboot-gerrit September 2018

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Change in coreboot[master]: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Pha...
by build bot (Jenkins) (Code Review) 20 Sep '18

20 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28669 ) Change subject: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Phaseer ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/#/c/28669/9/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/phaser/gpio.c: https://review.coreboot.org/#/c/28669/9/src/mainboard/google/octopus/varian… PS9, Line 64: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), line over 80 characters https://review.coreboot.org/#/c/28669/9/src/mainboard/google/octopus/varian… PS9, Line 99: }else{ space required after that close brace '}' -- To view, visit https://review.coreboot.org/28669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Gerrit-Change-Number: 28669 Gerrit-PatchSet: 9 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Sep 2018 02:00:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Set grip sensor threshold
by Seunghwan Kim (Code Review) 20 Sep '18

20 Sep '18

Seunghwan Kim has created a revert of this change. ( https://review.coreboot.org/28381 ) Change subject: mb/google/poppy/variants/nautilus: Set grip sensor threshold ...................................................................... -- To view, visit https://review.coreboot.org/28381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: revert Gerrit-Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Gerrit-Change-Number: 28381 Gerrit-PatchSet: 3 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"
by Seunghwan Kim (Code Review) 20 Sep '18

20 Sep '18

Hello Enrico Granata, build bot (Jenkins), Enrico Granata, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/28690 to review the following change. Change subject: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" ...................................................................... Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" This reverts commit aef592d9b66aa18d83b0a211ead26013ff1f7d98. Reason for revert: We'd like to configure the grip sensor threshold parameters on driver. (b:113303916) Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28690/1 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 109d2b6..37edd8a 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -334,13 +334,6 @@ register "desc" = ""SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A18_IRQ)" register "device_present_gpio" = "GPP_B20" - register "property_count" = "2" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""STH9321,reg_prox_ctrl6"" - register "property_list[0].integer" = "75" - register "property_list[1].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[1].name" = ""STH9321,reg_prox_ctrl7"" - register "property_list[1].integer" = "99" device i2c 28 on end end end # I2C #2 -- To view, visit https://review.coreboot.org/28690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Gerrit-Change-Number: 28690 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: set DMIC1 to NC
by Nick Vaccaro (Code Review) 20 Sep '18

20 Sep '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/28689 Change subject: mb/google/poppy/variant/nocturne: set DMIC1 to NC ...................................................................... mb/google/poppy/variant/nocturne: set DMIC1 to NC Change GPP_D17 and GPP_D18 to no connects as DMIC was moved to DMIC0. BUG=b:113744731,b:111106010 TEST=none Change-Id: I8ef42627e542182707c81389af9da33a114bc184 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/28689/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 08bb801..15a97c3 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -195,10 +195,10 @@ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), - /* D17 : DMIC_CLK1 ==> PCH_DMIC_CLK */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), - /* D18 : DMIC_DATA1 ==> PCH_DMIC_DATA */ - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ + PAD_CFG_NC(GPP_D17), + /* D18 : DMIC_DATA1 ==> TP131 */ + PAD_CFG_NC(GPP_D18), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ -- To view, visit https://review.coreboot.org/28689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8ef42627e542182707c81389af9da33a114bc184 Gerrit-Change-Number: 28689 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: [DoNotMerge]Local changes to make a platform working
by Lijian Zhao (Code Review) 19 Sep '18

19 Sep '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28688 Change subject: [DoNotMerge]Local changes to make a platform working ...................................................................... [DoNotMerge]Local changes to make a platform working Change-Id: I5449981baabcbb891e1036177307c58f5e2008ac Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- D payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch D payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch D payloads/external/tianocore/patches/03_Library_EndofDXE.patch D payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch D payloads/external/tianocore/patches/05_CorebootPayloadPkg_noserial.patch D payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch D payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch D payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch D payloads/external/tianocore/patches/09_gcc7-Fix-building-with-fpermissive.patch M src/mainboard/intel/cannonlake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/Makefile.inc M src/mainboard/intel/coffeelake_rvp/bootblock.c A src/mainboard/intel/coffeelake_rvp/early_init.c M src/mainboard/intel/coffeelake_rvp/memory.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb M src/soc/intel/cannonlake/Kconfig 17 files changed, 74 insertions(+), 2,951 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/28688/1 diff --git a/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch b/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch deleted file mode 100644 index 448da4a..0000000 --- a/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 4f9d41e69356ce7486b0c74a754ff494256723de Mon Sep 17 00:00:00 2001 -From: CoolStar <coolstarorganization(a)gmail.com> -Date: Sun, 4 Dec 2016 11:23:38 -0800 -Subject: [PATCH] PCI: use Duet's PciNoEnumeration - ---- - CorebootPayloadPkg/CorebootPayloadPkg.fdf | 4 ++-- - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 7 ++----- - CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 7 ++----- - 3 files changed, 6 insertions(+), 12 deletions(-) - -diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -index 303e626842..a39e3999ba 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf -+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -@@ -124,8 +124,8 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - # - # PCI Support - # --INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf --INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf -+INF DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf -+INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - - # - # ISA Support -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -index cdfcb75b59..e838aca61d 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -@@ -450,11 +450,8 @@ - # - # PCI Support - # -- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf -- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { -- <LibraryClasses> -- PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf -- } -+ DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf -+ DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - - # - # SCSI/ATA/IDE/DISK Support -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -index 6b16af63ba..c25d821fd4 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -@@ -451,11 +451,8 @@ - # - # PCI Support - # -- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf -- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { -- <LibraryClasses> -- PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf -- } -+ DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf -+ DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - - # - # SCSI/ATA/IDE/DISK Support --- -2.13.2.725.g09c95d1e9-goog - diff --git a/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch b/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch deleted file mode 100644 index 8013ccd..0000000 --- a/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch +++ /dev/null @@ -1,2551 +0,0 @@ -From 5121087836c1ad2a08857d494c0d9ecb183f4f98 Mon Sep 17 00:00:00 2001 -From: CoolStar <coolstarorganization(a)gmail.com> -Date: Tue, 18 Jul 2017 15:50:38 -0600 -Subject: [PATCH] Rebasing - ---- - CorebootModulePkg/CorebootModulePkg.dec | 8 + - .../Include/Guid/LdrMemoryDescriptor.h | 33 + - .../Include/Guid/PciExpressBaseAddress.h | 46 + - CorebootModulePkg/Include/Guid/PciOptionRomTable.h | 41 + - .../Library/CorebootBdsLib/BdsPlatform.c | 1731 ++++++++++++++++++++ - .../Library/CorebootBdsLib/BdsPlatform.h | 288 ++++ - .../Library/CorebootBdsLib/PlatformBds.inf | 65 + - .../Library/CorebootBdsLib/PlatformData.c | 161 ++ - CorebootPayloadPkg/CorebootPayloadPkg.fdf | 5 +- - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 12 +- - CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 12 +- - 11 files changed, 2388 insertions(+), 14 deletions(-) - create mode 100644 CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h - create mode 100644 CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h - create mode 100644 CorebootModulePkg/Include/Guid/PciOptionRomTable.h - create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c - create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h - create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf - create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c - -diff --git a/CorebootModulePkg/CorebootModulePkg.dec b/CorebootModulePkg/CorebootModulePkg.dec -index 7f1309bdae..20932a1d04 100644 ---- a/CorebootModulePkg/CorebootModulePkg.dec -+++ b/CorebootModulePkg/CorebootModulePkg.dec -@@ -33,8 +33,16 @@ - gUefiCorebootModulePkgTokenSpaceGuid = {0xe6ff49a0, 0x15df, 0x48fd, {0x9a, 0xcf, 0xd7, 0xdc, 0x27, 0x1b, 0x39, 0xd5}} - gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf, 0x89, 0xc4, 0x29, 0x4, 0x33}} - gUefiFrameBufferInfoGuid = {0xdc2cd8bd, 0x402c, 0x4dc4, {0x9b, 0xe0, 0xc, 0x43, 0x2b, 0x7, 0xfa, 0x34}} -+ gEfiPciExpressBaseAddressGuid = {0x3677d529, 0x326f, 0x4603, {0xa9, 0x26, 0xea, 0xac, 0xe0, 0x1d, 0xcb, 0xb0 }} - gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}} - -+ ## Include/Guid/PciOptionRomTable.h -+ gEfiPciOptionRomTableGuid = { 0x7462660F, 0x1CBD, 0x48DA, { 0xAD, 0x11, 0x91, 0x71, 0x79, 0x13, 0x83, 0x1C }} -+ -+ ## Include/Guid/LdrMemoryDescriptor.h -+ gLdrMemoryDescriptorGuid = { 0x7701d7e5, 0x7d1d, 0x4432, { 0xa4, 0x68, 0x67, 0x3d, 0xab, 0x8a, 0xde, 0x60 }} -+ -+ - - [Ppis] - -diff --git a/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h b/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h -new file mode 100644 -index 0000000000..38a997deea ---- /dev/null -+++ b/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h -@@ -0,0 +1,33 @@ -+/** @file -+ Guid is for GUIDED HOB of LDR memory descriptor. -+ -+Copyright (c) 2011, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+**/ -+ -+#ifndef __LDR_MEMORY_DESCRIPTOR__ -+#define __LDR_MEMORY_DESCRIPTOR__ -+ -+#define LDR_MEMORY_DESCRIPTOR_GUID \ -+ { 0x7701d7e5, 0x7d1d, 0x4432, {0xa4, 0x68, 0x67, 0x3d, 0xab, 0x8a, 0xde, 0x60}} -+ -+#pragma pack(1) -+ -+typedef struct { -+ EFI_HOB_GUID_TYPE Hob; -+ UINTN MemDescCount; -+ EFI_MEMORY_DESCRIPTOR *MemDesc; -+} MEMORY_DESC_HOB; -+ -+#pragma pack() -+ -+extern EFI_GUID gLdrMemoryDescriptorGuid; -+ -+#endif -diff --git a/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h b/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h -new file mode 100644 -index 0000000000..ff554383c1 ---- /dev/null -+++ b/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h -@@ -0,0 +1,46 @@ -+/** @file -+ -+Copyright (c) 2006, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+Module Name: -+ -+ PciExpressBaseAddress.h -+ -+Abstract: -+ -+ -+ GUIDs used for PciExpress Base Address -+ -+**/ -+ -+#ifndef _EFI_PCI_EXPRESS_BASE_ADDRESS_H_ -+#define _EFI_PCI_EXPRESS_BASE_ADDRESS_H_ -+ -+#define EFI_PCI_EXPRESS_BASE_ADDRESS_GUID \ -+ { \ -+ 0x3677d529, 0x326f, 0x4603, {0xa9, 0x26, 0xea, 0xac, 0xe0, 0x1d, 0xcb, 0xb0} \ -+ } -+ -+// -+// Following structure defines PCI Express Base Address information. -+// This information is platform specific, and built into hob in PEI phase. -+// It can be consumed by PEI PCI driver and DXE PCI driver. -+// -+#pragma pack(1) -+typedef struct _EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION { -+ UINT32 HostBridgeNumber; -+ UINT32 RootBridgeNumber; -+ UINT64 PciExpressBaseAddress; -+} EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION; -+#pragma pack() -+ -+extern EFI_GUID gEfiPciExpressBaseAddressGuid; -+ -+#endif -diff --git a/CorebootModulePkg/Include/Guid/PciOptionRomTable.h b/CorebootModulePkg/Include/Guid/PciOptionRomTable.h -new file mode 100644 -index 0000000000..a2fb99710a ---- /dev/null -+++ b/CorebootModulePkg/Include/Guid/PciOptionRomTable.h -@@ -0,0 +1,41 @@ -+/** @file -+ GUID and data structure used to describe the list of PCI Option ROMs present in a system. -+ -+Copyright (c) 2006, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+**/ -+ -+#ifndef __PCI_OPTION_ROM_TABLE_GUID_H_ -+#define __PCI_OPTION_ROM_TABLE_GUID_H_ -+ -+#define EFI_PCI_OPTION_ROM_TABLE_GUID \ -+ { 0x7462660f, 0x1cbd, 0x48da, {0xad, 0x11, 0x91, 0x71, 0x79, 0x13, 0x83, 0x1c } } -+ -+extern EFI_GUID gEfiPciOptionRomTableGuid; -+ -+typedef struct { -+ EFI_PHYSICAL_ADDRESS RomAddress; -+ EFI_MEMORY_TYPE MemoryType; -+ UINT32 RomLength; -+ UINT32 Seg; -+ UINT8 Bus; -+ UINT8 Dev; -+ UINT8 Func; -+ BOOLEAN ExecutedLegacyBiosImage; -+ BOOLEAN DontLoadEfiRom; -+} EFI_PCI_OPTION_ROM_DESCRIPTOR; -+ -+typedef struct { -+ UINT64 PciOptionRomCount; -+ EFI_PCI_OPTION_ROM_DESCRIPTOR *PciOptionRomDescriptors; -+} EFI_PCI_OPTION_ROM_TABLE; -+ -+#endif // __PCI_OPTION_ROM_TABLE_GUID_H_ -+ -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -new file mode 100644 -index 0000000000..b6253a17f8 ---- /dev/null -+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -@@ -0,0 +1,1731 @@ -+/*++ -+ -+Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+Module Name: -+ -+ BdsPlatform.c -+ -+Abstract: -+ -+ This file include all platform action which can be customized -+ by IBV/OEM. -+ -+--*/ -+ -+#include "BdsPlatform.h" -+ -+#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0) -+ -+extern BOOLEAN gConnectAllHappened; -+extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath; -+ -+EFI_GUID *gTableGuidArray[] = { -+ &gEfiAcpi20TableGuid, &gEfiAcpiTableGuid, &gEfiSmbiosTableGuid, &gEfiMpsTableGuid -+ }; -+ -+// -+// BDS Platform Functions -+// -+ -+VOID -+GetSystemTablesFromHob ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ Find GUID'ed HOBs that contain EFI_PHYSICAL_ADDRESS of ACPI, SMBIOS, MPs tables -+ -+Arguments: -+ None -+ -+Returns: -+ None. -+ -+--*/ -+{ -+ EFI_PEI_HOB_POINTERS GuidHob; -+ EFI_PEI_HOB_POINTERS HobStart; -+ EFI_PHYSICAL_ADDRESS *Table; -+ UINTN Index; -+ -+ // -+ // Get Hob List -+ // -+ HobStart.Raw = GetHobList (); -+ // -+ // Iteratively add ACPI Table, SMBIOS Table, MPS Table to EFI System Table -+ // -+ for (Index = 0; Index < ARRAY_SIZE (gTableGuidArray); ++Index) { -+ GuidHob.Raw = GetNextGuidHob (gTableGuidArray[Index], HobStart.Raw); -+ if (GuidHob.Raw != NULL) { -+ Table = GET_GUID_HOB_DATA (GuidHob.Guid); -+ if (Table != NULL) { -+ // -+ // Check if Mps Table/Smbios Table/Acpi Table exists in E/F seg, -+ // According to UEFI Spec, we should make sure Smbios table, -+ // ACPI table and Mps tables kept in memory of specified type -+ // -+ ConvertSystemTable(gTableGuidArray[Index], (VOID**)&Table); -+ gBS->InstallConfigurationTable (gTableGuidArray[Index], (VOID *)Table); -+ } -+ } -+ } -+ -+ return ; -+} -+ -+#if 0 -+VOID -+PrintMemoryMap ( -+ VOID -+ ) -+{ -+ EFI_MEMORY_DESCRIPTOR *MemMap; -+ EFI_MEMORY_DESCRIPTOR *MemMapPtr; -+ UINTN MemMapSize; -+ UINTN MapKey, DescriptorSize; -+ UINTN Index; -+ UINT32 DescriptorVersion; -+ UINT64 Bytes; -+ EFI_STATUS Status; -+ -+ MemMapSize = 0; -+ MemMap = NULL; -+ Status = gBS->GetMemoryMap (&MemMapSize, MemMap, &MapKey, &DescriptorSize, &DescriptorVersion); -+ ASSERT (Status == EFI_BUFFER_TOO_SMALL); -+ MemMapSize += EFI_PAGE_SIZE; -+ Status = gBS->AllocatePool (EfiBootServicesData, MemMapSize, &MemMap); -+ ASSERT (Status == EFI_SUCCESS); -+ Status = gBS->GetMemoryMap (&MemMapSize, MemMap, &MapKey, &DescriptorSize, &DescriptorVersion); -+ ASSERT (Status == EFI_SUCCESS); -+ MemMapPtr = MemMap; -+ -+ ASSERT (DescriptorVersion == EFI_MEMORY_DESCRIPTOR_VERSION); -+ -+ for (Index = 0; Index < MemMapSize / DescriptorSize; Index ++) { -+ Bytes = LShiftU64 (MemMap->NumberOfPages, 12); -+ DEBUG ((EFI_D_ERROR, "%lX-%lX %lX %lX %X\n", -+ MemMap->PhysicalStart, -+ MemMap->PhysicalStart + Bytes - 1, -+ MemMap->NumberOfPages, -+ MemMap->Attribute, -+ (UINTN)MemMap->Type)); -+ MemMap = (EFI_MEMORY_DESCRIPTOR *)((UINTN)MemMap + DescriptorSize); -+ } -+ -+ gBS->FreePool (MemMapPtr); -+} -+#endif -+ -+VOID -+UpdateMemoryMap ( -+ VOID -+ ) -+{ -+ EFI_STATUS Status; -+ EFI_PEI_HOB_POINTERS GuidHob; -+ VOID *Table; -+ MEMORY_DESC_HOB MemoryDescHob; -+ UINTN Index; -+ EFI_PHYSICAL_ADDRESS Memory; -+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor; -+ -+ GuidHob.Raw = GetFirstGuidHob (&gLdrMemoryDescriptorGuid); -+ if (GuidHob.Raw == NULL) { -+ DEBUG ((EFI_D_ERROR, "Fail to get gEfiLdrMemoryDescriptorGuid from GUID HOB LIST!\n")); -+ return; -+ } -+ Table = GET_GUID_HOB_DATA (GuidHob.Guid); -+ if (Table == NULL) { -+ DEBUG ((EFI_D_ERROR, "Fail to get gEfiLdrMemoryDescriptorGuid from GUID HOB LIST!\n")); -+ return; -+ } -+ MemoryDescHob.MemDescCount = *(UINTN *)Table; -+ MemoryDescHob.MemDesc = *(EFI_MEMORY_DESCRIPTOR **)((UINTN)Table + sizeof(UINTN)); -+ -+ // -+ // Add ACPINVS, ACPIReclaim, and Reserved memory to MemoryMap -+ // -+ for (Index = 0; Index < MemoryDescHob.MemDescCount; Index++) { -+ if (MemoryDescHob.MemDesc[Index].PhysicalStart < 0x100000) { -+ continue; -+ } -+ if (MemoryDescHob.MemDesc[Index].PhysicalStart >= 0x100000000ULL) { -+ continue; -+ } -+ if ((MemoryDescHob.MemDesc[Index].Type == EfiReservedMemoryType) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesData) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesCode) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiACPIReclaimMemory) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiACPIMemoryNVS)) { -+ DEBUG ((EFI_D_ERROR, "PhysicalStart - 0x%016lx, ", MemoryDescHob.MemDesc[Index].PhysicalStart)); -+ DEBUG ((EFI_D_ERROR, "PageNumber - 0x%016lx, ", MemoryDescHob.MemDesc[Index].NumberOfPages)); -+ DEBUG ((EFI_D_ERROR, "Attribute - 0x%016lx, ", MemoryDescHob.MemDesc[Index].Attribute)); -+ DEBUG ((EFI_D_ERROR, "Type - 0x%08x\n", MemoryDescHob.MemDesc[Index].Type)); -+ if ((MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesData) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesCode)) { -+ // -+ // For RuntimeSevicesData and RuntimeServicesCode, they are BFV or DxeCore. -+ // The memory type is assigned in EfiLdr -+ // -+ Status = gDS->GetMemorySpaceDescriptor (MemoryDescHob.MemDesc[Index].PhysicalStart, &Descriptor); -+ if (EFI_ERROR (Status)) { -+ continue; -+ } -+ if (Descriptor.GcdMemoryType != EfiGcdMemoryTypeReserved) { -+ // -+ // BFV or tested DXE core -+ // -+ continue; -+ } -+ // -+ // Untested DXE Core region, free and remove -+ // -+ Status = gDS->FreeMemorySpace ( -+ MemoryDescHob.MemDesc[Index].PhysicalStart, -+ LShiftU64 (MemoryDescHob.MemDesc[Index].NumberOfPages, EFI_PAGE_SHIFT) -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((EFI_D_ERROR, "FreeMemorySpace fail - %r!\n", Status)); -+ continue; -+ } -+ Status = gDS->RemoveMemorySpace ( -+ MemoryDescHob.MemDesc[Index].PhysicalStart, -+ LShiftU64 (MemoryDescHob.MemDesc[Index].NumberOfPages, EFI_PAGE_SHIFT) -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((EFI_D_ERROR, "RemoveMemorySpace fail - %r!\n", Status)); -+ continue; -+ } -+ -+ // -+ // Convert Runtime type to BootTime type -+ // -+ if (MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesData) { -+ MemoryDescHob.MemDesc[Index].Type = EfiBootServicesData; -+ } else { -+ MemoryDescHob.MemDesc[Index].Type = EfiBootServicesCode; -+ } -+ -+ // -+ // PassThrough, let below code add and alloate. -+ // -+ } -+ // -+ // ACPI or reserved memory -+ // -+ Status = gDS->AddMemorySpace ( -+ EfiGcdMemoryTypeSystemMemory, -+ MemoryDescHob.MemDesc[Index].PhysicalStart, -+ LShiftU64 (MemoryDescHob.MemDesc[Index].NumberOfPages, EFI_PAGE_SHIFT), -+ MemoryDescHob.MemDesc[Index].Attribute -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((EFI_D_ERROR, "AddMemorySpace fail - %r!\n", Status)); -+ if ((MemoryDescHob.MemDesc[Index].Type == EfiACPIReclaimMemory) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiACPIMemoryNVS)) { -+ // -+ // For EfiACPIReclaimMemory and EfiACPIMemoryNVS, it must success. -+ // For EfiReservedMemoryType, there maybe overlap. So skip check here. -+ // -+// ASSERT_EFI_ERROR (Status); -+ } -+ continue; -+ } -+ -+ Memory = MemoryDescHob.MemDesc[Index].PhysicalStart; -+ Status = gBS->AllocatePages ( -+ AllocateAddress, -+ (EFI_MEMORY_TYPE)MemoryDescHob.MemDesc[Index].Type, -+ (UINTN)MemoryDescHob.MemDesc[Index].NumberOfPages, -+ &Memory -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((EFI_D_ERROR, "AllocatePages fail - %r!\n", Status)); -+ // -+ // For the page added, it must be allocated. -+ // -+// ASSERT_EFI_ERROR (Status); -+ continue; -+ } -+ } -+ } -+ -+} -+ -+EFI_STATUS -+DisableUsbLegacySupport( -+ void -+ ) -+/*++ -+ -+Routine Description: -+ Disabble the USB legacy Support in all Ehci and Uhci. -+ This function assume all PciIo handles have been created in system. -+ -+Arguments: -+ None -+ -+Returns: -+ EFI_SUCCESS -+ EFI_NOT_FOUND -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_HANDLE *HandleArray; -+ UINTN HandleArrayCount; -+ UINTN Index; -+ EFI_PCI_IO_PROTOCOL *PciIo; -+ UINT8 Class[3]; -+ UINT16 Command; -+ UINT32 HcCapParams; -+ UINT32 ExtendCap; -+ UINT32 Value; -+ UINT32 TimeOut; -+ -+ // -+ // Find the usb host controller -+ // -+ Status = gBS->LocateHandleBuffer ( -+ ByProtocol, -+ &gEfiPciIoProtocolGuid, -+ NULL, -+ &HandleArrayCount, -+ &HandleArray -+ ); -+ if (!EFI_ERROR (Status)) { -+ for (Index = 0; Index < HandleArrayCount; Index++) { -+ Status = gBS->HandleProtocol ( -+ HandleArray[Index], -+ &gEfiPciIoProtocolGuid, -+ (VOID **)&PciIo -+ ); -+ if (!EFI_ERROR (Status)) { -+ // -+ // Find the USB host controller controller -+ // -+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 3, &Class); -+ if (!EFI_ERROR (Status)) { -+ if ((PCI_CLASS_SERIAL == Class[2]) && -+ (PCI_CLASS_SERIAL_USB == Class[1])) { -+ if (PCI_IF_UHCI == Class[0]) { -+ // -+ // Found the UHCI, then disable the legacy support -+ // -+ Command = 0; -+ Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0xC0, 1, &Command); -+ } else if (PCI_IF_EHCI == Class[0]) { -+ // -+ // Found the EHCI, then disable the legacy support -+ // -+ Status = PciIo->Mem.Read ( -+ PciIo, -+ EfiPciIoWidthUint32, -+ 0, //EHC_BAR_INDEX -+ (UINT64) 0x08, //EHC_HCCPARAMS_OFFSET -+ 1, -+ &HcCapParams -+ ); -+ -+ ExtendCap = (HcCapParams >> 8) & 0xFF; -+ // -+ // Disable the SMI in USBLEGCTLSTS firstly -+ // -+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value); -+ Value &= 0xFFFF0000; -+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value); -+ -+ // -+ // Get EHCI Ownership from legacy bios -+ // -+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value); -+ Value |= (0x1 << 24); -+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value); -+ -+ TimeOut = 40; -+ while (TimeOut--) { -+ gBS->Stall (500); -+ -+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value); -+ -+ if ((Value & 0x01010000) == 0x01000000) { -+ break; -+ } -+ } -+ } -+ } -+ } -+ } -+ } -+ } else { -+ return Status; -+ } -+ gBS->FreePool (HandleArray); -+ return EFI_SUCCESS; -+} -+ -+ -+VOID -+EFIAPI -+PlatformBdsInit ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ -+ Platform Bds init. Include the platform firmware vendor, revision -+ and so crc check. -+ -+Arguments: -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ GetSystemTablesFromHob (); -+ -+ UpdateMemoryMap (); -+ -+ // -+ // Append Usb Keyboard short form DevicePath into "ConInDev" -+ // -+ BdsLibUpdateConsoleVariable ( -+ VarConsoleInpDev, -+ (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, -+ NULL -+ ); -+} -+ -+UINT64 -+GetPciExpressBaseAddressForRootBridge ( -+ IN UINTN HostBridgeNumber, -+ IN UINTN RootBridgeNumber -+ ) -+/*++ -+ -+Routine Description: -+ This routine is to get PciExpress Base Address for this RootBridge -+ -+Arguments: -+ HostBridgeNumber - The number of HostBridge -+ RootBridgeNumber - The number of RootBridge -+ -+Returns: -+ UINT64 - PciExpressBaseAddress for this HostBridge and RootBridge -+ -+--*/ -+{ -+ EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION *PciExpressBaseAddressInfo; -+ UINTN BufferSize; -+ UINT32 Index; -+ UINT32 Number; -+ EFI_PEI_HOB_POINTERS GuidHob; -+ -+ // -+ // Get PciExpressAddressInfo Hob -+ // -+ PciExpressBaseAddressInfo = NULL; -+ BufferSize = 0; -+ GuidHob.Raw = GetFirstGuidHob (&gEfiPciExpressBaseAddressGuid); -+ if (GuidHob.Raw != NULL) { -+ PciExpressBaseAddressInfo = GET_GUID_HOB_DATA (GuidHob.Guid); -+ BufferSize = GET_GUID_HOB_DATA_SIZE (GuidHob.Guid); -+ } else { -+ return 0; -+ } -+ -+ // -+ // Search the PciExpress Base Address in the Hob for current RootBridge -+ // -+ Number = (UINT32)(BufferSize / sizeof(EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION)); -+ for (Index = 0; Index < Number; Index++) { -+ if ((PciExpressBaseAddressInfo[Index].HostBridgeNumber == HostBridgeNumber) && -+ (PciExpressBaseAddressInfo[Index].RootBridgeNumber == RootBridgeNumber)) { -+ return PciExpressBaseAddressInfo[Index].PciExpressBaseAddress; -+ } -+ } -+ -+ // -+ // Do not find the PciExpress Base Address in the Hob -+ // -+ return 0; -+} -+ -+VOID -+PatchPciRootBridgeDevicePath ( -+ IN UINTN HostBridgeNumber, -+ IN UINTN RootBridgeNumber, -+ IN PLATFORM_ROOT_BRIDGE_DEVICE_PATH *RootBridge -+ ) -+{ -+ UINT64 PciExpressBase; -+ -+ PciExpressBase = GetPciExpressBaseAddressForRootBridge (HostBridgeNumber, RootBridgeNumber); -+ -+ DEBUG ((EFI_D_INFO, "Get PciExpress Address from Hob: 0x%X\n", PciExpressBase)); -+ -+ if (PciExpressBase != 0) { -+ RootBridge->PciRootBridge.HID = EISA_PNP_ID(0x0A08); -+ } -+} -+ -+EFI_STATUS -+ConnectRootBridge ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ -+ Connect RootBridge -+ -+Arguments: -+ -+ None. -+ -+Returns: -+ -+ EFI_SUCCESS - Connect RootBridge successfully. -+ EFI_STATUS - Connect RootBridge fail. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_HANDLE RootHandle; -+ -+ // -+ // Patch Pci Root Bridge Device Path -+ // -+ PatchPciRootBridgeDevicePath (0, 0, &gPlatformRootBridge0); -+ -+ // -+ // Make all the PCI_IO protocols on PCI Seg 0 show up -+ // -+ BdsLibConnectDevicePath (gPlatformRootBridges[0]); -+ -+ Status = gBS->LocateDevicePath ( -+ &gEfiDevicePathProtocolGuid, -+ &gPlatformRootBridges[0], -+ &RootHandle -+ ); -+ DEBUG ((EFI_D_INFO, "Pci Root bridge handle is 0x%X\n", RootHandle)); -+ -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ Status = gBS->ConnectController (RootHandle, NULL, NULL, FALSE); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+PrepareLpcBridgeDevicePath ( -+ IN EFI_HANDLE DeviceHandle -+ ) -+/*++ -+ -+Routine Description: -+ -+ Add IsaKeyboard to ConIn, -+ add IsaSerial to ConOut, ConIn, ErrOut. -+ LPC Bridge: 06 01 00 -+ -+Arguments: -+ -+ DeviceHandle - Handle of PCIIO protocol. -+ -+Returns: -+ -+ EFI_SUCCESS - LPC bridge is added to ConOut, ConIn, and ErrOut. -+ EFI_STATUS - No LPC bridge is added. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_DEVICE_PATH_PROTOCOL *DevicePath; -+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; -+ -+ DevicePath = NULL; -+ Status = gBS->HandleProtocol ( -+ DeviceHandle, -+ &gEfiDevicePathProtocolGuid, -+ (VOID*)&DevicePath -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ TempDevicePath = DevicePath; -+ -+ // -+ // Register Keyboard -+ // -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnpPs2KeyboardDeviceNode); -+ -+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL); -+ -+ // -+ // Register COM1 -+ // -+ DevicePath = TempDevicePath; -+ gPnp16550ComPortDeviceNode.UID = 0; -+ -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnp16550ComPortDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode); -+ -+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL); -+ -+ // -+ // Register COM2 -+ // -+ DevicePath = TempDevicePath; -+ gPnp16550ComPortDeviceNode.UID = 1; -+ -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnp16550ComPortDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode); -+ -+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL); -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+GetGopDevicePath ( -+ IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath, -+ OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath -+ ) -+{ -+ UINTN Index; -+ EFI_STATUS Status; -+ EFI_HANDLE PciDeviceHandle; -+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; -+ EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath; -+ UINTN GopHandleCount; -+ EFI_HANDLE *GopHandleBuffer; -+ -+ if (PciDevicePath == NULL || GopDevicePath == NULL) { -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ // -+ // Initialize the GopDevicePath to be PciDevicePath -+ // -+ *GopDevicePath = PciDevicePath; -+ TempPciDevicePath = PciDevicePath; -+ -+ Status = gBS->LocateDevicePath ( -+ &gEfiDevicePathProtocolGuid, -+ &TempPciDevicePath, -+ &PciDeviceHandle -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ // -+ // Try to connect this handle, so that GOP driver could start on this -+ // device and create child handles with GraphicsOutput Protocol installed -+ // on them, then we get device paths of these child handles and select -+ // them as possible console device. -+ // -+ gBS->ConnectController (PciDeviceHandle, NULL, NULL, FALSE); -+ -+ Status = gBS->LocateHandleBuffer ( -+ ByProtocol, -+ &gEfiGraphicsOutputProtocolGuid, -+ NULL, -+ &GopHandleCount, -+ &GopHandleBuffer -+ ); -+ if (!EFI_ERROR (Status)) { -+ // -+ // Add all the child handles as possible Console Device -+ // -+ for (Index = 0; Index < GopHandleCount; Index++) { -+ Status = gBS->HandleProtocol (GopHandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID*)&TempDevicePath); -+ if (EFI_ERROR (Status)) { -+ continue; -+ } -+ if (CompareMem ( -+ PciDevicePath, -+ TempDevicePath, -+ GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH -+ ) == 0) { -+ // -+ // In current implementation, we only enable one of the child handles -+ // as console device, i.e. sotre one of the child handle's device -+ // path to variable "ConOut" -+ // In future, we could select all child handles to be console device -+ // -+ -+ *GopDevicePath = TempDevicePath; -+ -+ // -+ // Delete the PCI device's path that added by GetPlugInPciVgaDevicePath() -+ // Add the integrity GOP device path. -+ // -+ BdsLibUpdateConsoleVariable (VarConsoleOutDev, NULL, PciDevicePath); -+ BdsLibUpdateConsoleVariable (VarConsoleOutDev, TempDevicePath, NULL); -+ } -+ } -+ gBS->FreePool (GopHandleBuffer); -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+PreparePciVgaDevicePath ( -+ IN EFI_HANDLE DeviceHandle -+ ) -+/*++ -+ -+Routine Description: -+ -+ Add PCI VGA to ConOut. -+ PCI VGA: 03 00 00 -+ -+Arguments: -+ -+ DeviceHandle - Handle of PCIIO protocol. -+ -+Returns: -+ -+ EFI_SUCCESS - PCI VGA is added to ConOut. -+ EFI_STATUS - No PCI VGA device is added. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_DEVICE_PATH_PROTOCOL *DevicePath; -+ EFI_DEVICE_PATH_PROTOCOL *GopDevicePath; -+ -+ DevicePath = NULL; -+ GopDevicePath = NULL; -+ Status = gBS->HandleProtocol ( -+ DeviceHandle, -+ &gEfiDevicePathProtocolGuid, -+ (VOID*)&DevicePath -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ GetGopDevicePath (DevicePath, &GopDevicePath); -+ DevicePath = GopDevicePath; -+ -+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL); -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+PreparePciSerialDevicePath ( -+ IN EFI_HANDLE DeviceHandle -+ ) -+/*++ -+ -+Routine Description: -+ -+ Add PCI Serial to ConOut, ConIn, ErrOut. -+ PCI Serial: 07 00 02 -+ -+Arguments: -+ -+ DeviceHandle - Handle of PCIIO protocol. -+ -+Returns: -+ -+ EFI_SUCCESS - PCI Serial is added to ConOut, ConIn, and ErrOut. -+ EFI_STATUS - No PCI Serial device is added. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_DEVICE_PATH_PROTOCOL *DevicePath; -+ -+ DevicePath = NULL; -+ Status = gBS->HandleProtocol ( -+ DeviceHandle, -+ &gEfiDevicePathProtocolGuid, -+ (VOID*)&DevicePath -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode); -+ -+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL); -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+DetectAndPreparePlatformPciDevicePath ( -+ BOOLEAN DetectVgaOnly -+ ) -+/*++ -+ -+Routine Description: -+ -+ Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut -+ -+Arguments: -+ -+ DetectVgaOnly - Only detect VGA device if it's TRUE. -+ -+Returns: -+ -+ EFI_SUCCESS - PCI Device check and Console variable update successfully. -+ EFI_STATUS - PCI Device check or Console variable update fail. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ UINTN HandleCount; -+ EFI_HANDLE *HandleBuffer; -+ UINTN Index; -+ EFI_PCI_IO_PROTOCOL *PciIo; -+ PCI_TYPE00 Pci; -+ -+ // -+ // Start to check all the PciIo to find all possible device -+ // -+ HandleCount = 0; -+ HandleBuffer = NULL; -+ Status = gBS->LocateHandleBuffer ( -+ ByProtocol, -+ &gEfiPciIoProtocolGuid, -+ NULL, -+ &HandleCount, -+ &HandleBuffer -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ for (Index = 0; Index < HandleCount; Index++) { -+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID*)&PciIo); -+ if (EFI_ERROR (Status)) { -+ continue; -+ } -+ -+ // -+ // Check for all PCI device -+ // -+ Status = PciIo->Pci.Read ( -+ PciIo, -+ EfiPciIoWidthUint32, -+ 0, -+ sizeof (Pci) / sizeof (UINT32), -+ &Pci -+ ); -+ if (EFI_ERROR (Status)) { -+ continue; -+ } -+ -+ if (!DetectVgaOnly) { -+ // -+ // Here we decide whether it is LPC Bridge -+ // -+ if ((IS_PCI_LPC (&Pci)) || -+ ((IS_PCI_ISA_PDECODE (&Pci)) && (Pci.Hdr.VendorId == 0x8086) && (Pci.Hdr.DeviceId == 0x7110))) { -+ // -+ // Add IsaKeyboard to ConIn, -+ // add IsaSerial to ConOut, ConIn, ErrOut -+ // -+ DEBUG ((EFI_D_INFO, "Find the LPC Bridge device\n")); -+ PrepareLpcBridgeDevicePath (HandleBuffer[Index]); -+ continue; -+ } -+ // -+ // Here we decide which Serial device to enable in PCI bus -+ // -+ if (IS_PCI_16550SERIAL (&Pci)) { -+ // -+ // Add them to ConOut, ConIn, ErrOut. -+ // -+ DEBUG ((EFI_D_INFO, "Find the 16550 SERIAL device\n")); -+ PreparePciSerialDevicePath (HandleBuffer[Index]); -+ continue; -+ } -+ } -+ -+ // -+ // Here we decide which VGA device to enable in PCI bus -+ // -+ if (IS_PCI_VGA (&Pci)) { -+ // -+ // Add them to ConOut. -+ // -+ DEBUG ((EFI_D_INFO, "Find the VGA device\n")); -+ PreparePciVgaDevicePath (HandleBuffer[Index]); -+ continue; -+ } -+ } -+ -+ gBS->FreePool (HandleBuffer); -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+PlatformBdsConnectConsole ( -+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole -+ ) -+/*++ -+ -+Routine Description: -+ -+ Connect the predefined platform default console device. Always try to find -+ and enable the vga device if have. -+ -+Arguments: -+ -+ PlatformConsole - Predefined platform default console device array. -+ -+Returns: -+ -+ EFI_SUCCESS - Success connect at least one ConIn and ConOut -+ device, there must have one ConOut device is -+ active vga device. -+ -+ EFI_STATUS - Return the status of -+ BdsLibConnectAllDefaultConsoles () -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ UINTN Index; -+ EFI_DEVICE_PATH_PROTOCOL *VarConout; -+ EFI_DEVICE_PATH_PROTOCOL *VarConin; -+ UINTN DevicePathSize; -+ -+ // -+ // Connect RootBridge -+ // -+ ConnectRootBridge (); -+ -+ VarConout = BdsLibGetVariableAndSize ( -+ VarConsoleOut, -+ &gEfiGlobalVariableGuid, -+ &DevicePathSize -+ ); -+ VarConin = BdsLibGetVariableAndSize ( -+ VarConsoleInp, -+ &gEfiGlobalVariableGuid, -+ &DevicePathSize -+ ); -+ -+ if (VarConout == NULL || VarConin == NULL) { -+ // -+ // Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut -+ // -+ DetectAndPreparePlatformPciDevicePath (FALSE); -+ -+ // -+ // Have chance to connect the platform default console, -+ // the platform default console is the minimum device group -+ // the platform should support -+ // -+ for (Index = 0; PlatformConsole[Index].DevicePath != NULL; ++Index) { -+ // -+ // Update the console variable with the connect type -+ // -+ if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) { -+ BdsLibUpdateConsoleVariable (VarConsoleInp, PlatformConsole[Index].DevicePath, NULL); -+ } -+ if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) { -+ BdsLibUpdateConsoleVariable (VarConsoleOut, PlatformConsole[Index].DevicePath, NULL); -+ } -+ if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) { -+ BdsLibUpdateConsoleVariable (VarErrorOut, PlatformConsole[Index].DevicePath, NULL); -+ } -+ } -+ } else { -+ // -+ // Only detect VGA device and add them to ConOut -+ // -+ DetectAndPreparePlatformPciDevicePath (TRUE); -+ } -+ -+ // -+ // The ConIn devices connection will start the USB bus, should disable all -+ // Usb legacy support firstly. -+ // Caution: Must ensure the PCI bus driver has been started. Since the -+ // ConnectRootBridge() will create all the PciIo protocol, it's safe here now -+ // -+ Status = DisableUsbLegacySupport(); -+ -+ // -+ // Connect the all the default console with current cosole variable -+ // -+ Status = BdsLibConnectAllDefaultConsoles (); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+VOID -+PlatformBdsConnectSequence ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ -+ Connect with predefined platform connect sequence, -+ the OEM/IBV can customize with their own connect sequence. -+ -+Arguments: -+ -+ None. -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ UINTN Index; -+ -+ Index = 0; -+ -+ // -+ // Here we can get the customized platform connect sequence -+ // Notes: we can connect with new variable which record the -+ // last time boots connect device path sequence -+ // -+ while (gPlatformConnectSequence[Index] != NULL) { -+ // -+ // Build the platform boot option -+ // -+ BdsLibConnectDevicePath (gPlatformConnectSequence[Index]); -+ Index++; -+ } -+ -+} -+ -+VOID -+PlatformBdsGetDriverOption ( -+ IN OUT LIST_ENTRY *BdsDriverLists -+ ) -+/*++ -+ -+Routine Description: -+ -+ Load the predefined driver option, OEM/IBV can customize this -+ to load their own drivers -+ -+Arguments: -+ -+ BdsDriverLists - The header of the driver option link list. -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ UINTN Index; -+ -+ Index = 0; -+ -+ // -+ // Here we can get the customized platform driver option -+ // -+ while (gPlatformDriverOption[Index] != NULL) { -+ // -+ // Build the platform boot option -+ // -+ BdsLibRegisterNewOption (BdsDriverLists, gPlatformDriverOption[Index], NULL, L"DriverOrder"); -+ Index++; -+ } -+ -+} -+ -+VOID -+PlatformBdsDiagnostics ( -+ IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel, -+ IN BOOLEAN QuietBoot, -+ IN BASEM_MEMORY_TEST BaseMemoryTest -+ ) -+/*++ -+ -+Routine Description: -+ -+ Perform the platform diagnostic, such like test memory. OEM/IBV also -+ can customize this fuction to support specific platform diagnostic. -+ -+Arguments: -+ -+ MemoryTestLevel - The memory test intensive level -+ -+ QuietBoot - Indicate if need to enable the quiet boot -+ -+ BaseMemoryTest - A pointer to BdsMemoryTest() -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ -+ // -+ // Here we can decide if we need to show -+ // the diagnostics screen -+ // Notes: this quiet boot code should be remove -+ // from the graphic lib -+ // -+ if (QuietBoot) { -+ Status = EnableQuietBoot (PcdGetPtr(PcdLogoFile)); -+ if (EFI_ERROR (Status)) { -+ DisableQuietBoot (); -+ return; -+ } -+ -+ // -+ // Perform system diagnostic -+ // -+ Status = BaseMemoryTest (MemoryTestLevel); -+ if (EFI_ERROR (Status)) { -+ DisableQuietBoot (); -+ } -+ -+ return ; -+ } -+ // -+ // Perform system diagnostic -+ // -+ Status = BaseMemoryTest (MemoryTestLevel); -+} -+ -+VOID -+EFIAPI -+PlatformBdsPolicyBehavior ( -+ IN OUT LIST_ENTRY *DriverOptionList, -+ IN OUT LIST_ENTRY *BootOptionList, -+ IN PROCESS_CAPSULES ProcessCapsules, -+ IN BASEM_MEMORY_TEST BaseMemoryTest -+ ) -+/*++ -+ -+Routine Description: -+ -+ The function will execute with as the platform policy, current policy -+ is driven by boot mode. IBV/OEM can customize this code for their specific -+ policy action. -+ -+Arguments: -+ -+ DriverOptionList - The header of the driver option link list -+ -+ BootOptionList - The header of the boot option link list -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ UINT16 Timeout; -+ EFI_EVENT UserInputDurationTime; -+ UINTN Index; -+ EFI_INPUT_KEY Key; -+ EFI_BOOT_MODE BootMode; -+ -+ // -+ // Init the time out value -+ // -+ Timeout = PcdGet16 (PcdPlatformBootTimeOut); -+ -+ // -+ // Load the driver option as the driver option list -+ // -+ PlatformBdsGetDriverOption (DriverOptionList); -+ -+ // -+ // Get current Boot Mode -+ // -+ Status = BdsLibGetBootMode (&BootMode); -+ DEBUG ((EFI_D_ERROR, "Boot Mode:%x\n", BootMode)); -+ -+ // -+ // Go the different platform policy with different boot mode -+ // Notes: this part code can be change with the table policy -+ // -+ ASSERT (BootMode == BOOT_WITH_FULL_CONFIGURATION); -+ // -+ // Connect platform console -+ // -+ Status = PlatformBdsConnectConsole (gPlatformConsole); -+ if (EFI_ERROR (Status)) { -+ // -+ // Here OEM/IBV can customize with defined action -+ // -+ PlatformBdsNoConsoleAction (); -+ } -+ // -+ // Create a 300ms duration event to ensure user has enough input time to enter Setup -+ // -+ Status = gBS->CreateEvent ( -+ EVT_TIMER, -+ 0, -+ NULL, -+ NULL, -+ &UserInputDurationTime -+ ); -+ ASSERT (Status == EFI_SUCCESS); -+ Status = gBS->SetTimer (UserInputDurationTime, TimerRelative, 3000000); -+ ASSERT (Status == EFI_SUCCESS); -+ // -+ // Memory test and Logo show -+ // -+ PlatformBdsDiagnostics (IGNORE, TRUE, BaseMemoryTest); -+ -+ // -+ // Perform some platform specific connect sequence -+ // -+ PlatformBdsConnectSequence (); -+ -+ // -+ // Give one chance to enter the setup if we -+ // have the time out -+ // -+ // BUGBUG: hard code timeout to 5 second to show logo in graphic mode. -+ Timeout = 5; -+ if (Timeout != 0) { -+ PlatformBdsEnterFrontPage (Timeout, FALSE); -+ } -+ -+ // -+ //BdsLibConnectAll (); -+ //BdsLibEnumerateAllBootOption (BootOptionList); -+ -+ // -+ // Please uncomment above ConnectAll and EnumerateAll code and remove following first boot -+ // checking code in real production tip. -+ // -+ // In BOOT_WITH_FULL_CONFIGURATION boot mode, should always connect every device -+ // and do enumerate all the default boot options. But in development system board, the boot mode -+ // cannot be BOOT_ASSUMING_NO_CONFIGURATION_CHANGES because the machine box -+ // is always open. So the following code only do the ConnectAll and EnumerateAll at first boot. -+ // -+ Status = BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder"); -+ if (EFI_ERROR(Status)) { -+ // -+ // If cannot find "BootOrder" variable, it may be first boot. -+ // Try to connect all devices and enumerate all boot options here. -+ // -+ BdsLibConnectAll (); -+ BdsLibEnumerateAllBootOption (BootOptionList); -+ } -+ -+ // -+ // To give the User a chance to enter Setup here, if user set TimeOut is 0. -+ // BDS should still give user a chance to enter Setup -+ // Check whether the user input after the duration time has expired -+ // -+ gBS->WaitForEvent (1, &UserInputDurationTime, &Index); -+ gBS->CloseEvent (UserInputDurationTime); -+ Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key); -+ -+ if (!EFI_ERROR (Status)) { -+ // -+ // Enter Setup if user input -+ // -+ Timeout = 0xffff; -+ PlatformBdsEnterFrontPage (Timeout, FALSE); -+ } -+ -+ return ; -+ -+} -+ -+VOID -+EFIAPI -+PlatformBdsBootSuccess ( -+ IN BDS_COMMON_OPTION *Option -+ ) -+/*++ -+ -+Routine Description: -+ -+ Hook point after a boot attempt succeeds. We don't expect a boot option to -+ return, so the EFI 1.0 specification defines that you will default to an -+ interactive mode and stop processing the BootOrder list in this case. This -+ is alos a platform implementation and can be customized by IBV/OEM. -+ -+Arguments: -+ -+ Option - Pointer to Boot Option that succeeded to boot. -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ CHAR16 *TmpStr; -+ -+ // -+ // If Boot returned with EFI_SUCCESS and there is not in the boot device -+ // select loop then we need to pop up a UI and wait for user input. -+ // -+ TmpStr = Option->StatusString; -+ if (TmpStr != NULL) { -+ BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL); -+ gBS->FreePool (TmpStr); -+ } -+} -+ -+VOID -+EFIAPI -+PlatformBdsBootFail ( -+ IN BDS_COMMON_OPTION *Option, -+ IN EFI_STATUS Status, -+ IN CHAR16 *ExitData, -+ IN UINTN ExitDataSize -+ ) -+/*++ -+ -+Routine Description: -+ -+ Hook point after a boot attempt fails. -+ -+Arguments: -+ -+ Option - Pointer to Boot Option that failed to boot. -+ -+ Status - Status returned from failed boot. -+ -+ ExitData - Exit data returned from failed boot. -+ -+ ExitDataSize - Exit data size returned from failed boot. -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ CHAR16 *TmpStr; -+ -+ // -+ // If Boot returned with failed status then we need to pop up a UI and wait -+ // for user input. -+ // -+ TmpStr = Option->StatusString; -+ if (TmpStr != NULL) { -+ BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL); -+ gBS->FreePool (TmpStr); -+ } -+ -+} -+ -+EFI_STATUS -+PlatformBdsNoConsoleAction ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ -+ This function is remained for IBV/OEM to do some platform action, -+ if there no console device can be connected. -+ -+Arguments: -+ -+ None. -+ -+Returns: -+ -+ EFI_SUCCESS - Direct return success now. -+ -+--*/ -+{ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+ConvertSystemTable ( -+ IN EFI_GUID *TableGuid, -+ IN OUT VOID **Table -+ ) -+/*++ -+ -+Routine Description: -+ Convert ACPI Table /Smbios Table /MP Table if its location is lower than Address:0x100000 -+ Assumption here: -+ As in legacy Bios, ACPI/Smbios/MP table is required to place in E/F Seg, -+ So here we just check if the range is E/F seg, -+ and if Not, assume the Memory type is EfiACPIReclaimMemory/EfiACPIMemoryNVS -+ -+Arguments: -+ TableGuid - Guid of the table -+ Table - pointer to the table -+ -+Returns: -+ EFI_SUCEESS - Convert Table successfully -+ Other - Failed -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ VOID *AcpiHeader; -+ UINTN AcpiTableLen; -+ -+ // -+ // If match acpi guid (1.0, 2.0, or later), Convert ACPI table according to version. -+ // -+ AcpiHeader = (VOID*)(UINTN)(*(UINT64 *)(*Table)); -+ -+ if (CompareGuid(TableGuid, &gEfiAcpiTableGuid) || CompareGuid(TableGuid, &gEfiAcpi20TableGuid)){ -+ if (((EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)AcpiHeader)->Reserved == 0x00){ -+ // -+ // If Acpi 1.0 Table, then RSDP structure doesn't contain Length field, use structure size -+ // -+ AcpiTableLen = sizeof (EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER); -+ } else if (((EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)AcpiHeader)->Reserved >= 0x02){ -+ // -+ // If Acpi 2.0 or later, use RSDP Length fied. -+ // -+ AcpiTableLen = ((EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)AcpiHeader)->Length; -+ } else { -+ // -+ // Invalid Acpi Version, return -+ // -+ return EFI_UNSUPPORTED; -+ } -+ Status = ConvertAcpiTable (AcpiTableLen, Table); -+ return Status; -+ } -+ -+ // -+ // If matches smbios guid, convert Smbios table. -+ // -+ if (CompareGuid(TableGuid, &gEfiSmbiosTableGuid)){ -+ Status = ConvertSmbiosTable (Table); -+ return Status; -+ } -+ -+ // -+ // If the table is MP table? -+ // -+ if (CompareGuid(TableGuid, &gEfiMpsTableGuid)){ -+ Status = ConvertMpsTable (Table); -+ return Status; -+ } -+ -+ return EFI_UNSUPPORTED; -+} -+ -+ -+EFI_STATUS -+ConvertAcpiTable ( -+ IN UINTN TableLen, -+ IN OUT VOID **Table -+ ) -+/*++ -+ -+Routine Description: -+ Convert RSDP of ACPI Table if its location is lower than Address:0x100000 -+ Assumption here: -+ As in legacy Bios, ACPI table is required to place in E/F Seg, -+ So here we just check if the range is E/F seg, -+ and if Not, assume the Memory type is EfiACPIReclaimMemory/EfiACPIMemoryNVS -+ -+Arguments: -+ TableLen - Acpi RSDP length -+ Table - pointer to the table -+ -+Returns: -+ EFI_SUCEESS - Convert Table successfully -+ Other - Failed -+ -+--*/ -+{ -+ VOID *AcpiTableOri; -+ VOID *AcpiTableNew; -+ EFI_STATUS Status; -+ EFI_PHYSICAL_ADDRESS BufferPtr; -+ -+ -+ AcpiTableOri = (VOID *)(UINTN)(*(UINT64*)(*Table)); -+ if (((UINTN)AcpiTableOri < 0x100000) && ((UINTN)AcpiTableOri > 0xE0000)) { -+ BufferPtr = EFI_SYSTEM_TABLE_MAX_ADDRESS; -+ Status = gBS->AllocatePages ( -+ AllocateMaxAddress, -+ EfiACPIMemoryNVS, -+ EFI_SIZE_TO_PAGES(TableLen), -+ &BufferPtr -+ ); -+ ASSERT_EFI_ERROR (Status); -+ AcpiTableNew = (VOID *)(UINTN)BufferPtr; -+ CopyMem (AcpiTableNew, AcpiTableOri, TableLen); -+ } else { -+ AcpiTableNew = AcpiTableOri; -+ } -+ // -+ // Change configuration table Pointer -+ // -+ *Table = AcpiTableNew; -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+ConvertSmbiosTable ( -+ IN OUT VOID **Table -+ ) -+/*++ -+ -+Routine Description: -+ -+ Convert Smbios Table if the Location of the SMBios Table is lower than Addres 0x100000 -+ Assumption here: -+ As in legacy Bios, Smbios table is required to place in E/F Seg, -+ So here we just check if the range is F seg, -+ and if Not, assume the Memory type is EfiACPIMemoryNVS/EfiRuntimeServicesData -+Arguments: -+ Table - pointer to the table -+ -+Returns: -+ EFI_SUCEESS - Convert Table successfully -+ Other - Failed -+ -+--*/ -+{ -+ SMBIOS_TABLE_ENTRY_POINT *SmbiosTableNew; -+ SMBIOS_TABLE_ENTRY_POINT *SmbiosTableOri; -+ EFI_STATUS Status; -+ UINT32 SmbiosEntryLen; -+ UINT32 BufferLen; -+ EFI_PHYSICAL_ADDRESS BufferPtr; -+ -+ SmbiosTableNew = NULL; -+ SmbiosTableOri = NULL; -+ -+ // -+ // Get Smibos configuration Table -+ // -+ SmbiosTableOri = (SMBIOS_TABLE_ENTRY_POINT *)(UINTN)(*(UINT64*)(*Table)); -+ -+ if ((SmbiosTableOri == NULL) || -+ ((UINTN)SmbiosTableOri > 0x100000) || -+ ((UINTN)SmbiosTableOri < 0xF0000)){ -+ return EFI_SUCCESS; -+ } -+ // -+ // Relocate the Smibos memory -+ // -+ BufferPtr = EFI_SYSTEM_TABLE_MAX_ADDRESS; -+ if (SmbiosTableOri->SmbiosBcdRevision != 0x21) { -+ SmbiosEntryLen = SmbiosTableOri->EntryPointLength; -+ } else { -+ // -+ // According to Smbios Spec 2.4, we should set entry point length as 0x1F if version is 2.1 -+ // -+ SmbiosEntryLen = 0x1F; -+ } -+ BufferLen = SmbiosEntryLen + SYS_TABLE_PAD(SmbiosEntryLen) + SmbiosTableOri->TableLength; -+ Status = gBS->AllocatePages ( -+ AllocateMaxAddress, -+ EfiACPIMemoryNVS, -+ EFI_SIZE_TO_PAGES(BufferLen), -+ &BufferPtr -+ ); -+ ASSERT_EFI_ERROR (Status); -+ SmbiosTableNew = (SMBIOS_TABLE_ENTRY_POINT *)(UINTN)BufferPtr; -+ CopyMem ( -+ SmbiosTableNew, -+ SmbiosTableOri, -+ SmbiosEntryLen -+ ); -+ // -+ // Get Smbios Structure table address, and make sure the start address is 32-bit align -+ // -+ BufferPtr += SmbiosEntryLen + SYS_TABLE_PAD(SmbiosEntryLen); -+ CopyMem ( -+ (VOID *)(UINTN)BufferPtr, -+ (VOID *)(UINTN)(SmbiosTableOri->TableAddress), -+ SmbiosTableOri->TableLength -+ ); -+ SmbiosTableNew->TableAddress = (UINT32)BufferPtr; -+ SmbiosTableNew->IntermediateChecksum = 0; -+ SmbiosTableNew->IntermediateChecksum = -+ CalculateCheckSum8 ((UINT8*)SmbiosTableNew + 0x10, SmbiosEntryLen -0x10); -+ // -+ // Change the SMBIOS pointer -+ // -+ *Table = SmbiosTableNew; -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+ConvertMpsTable ( -+ IN OUT VOID **Table -+ ) -+/*++ -+ -+Routine Description: -+ -+ Convert MP Table if the Location of the SMBios Table is lower than Addres 0x100000 -+ Assumption here: -+ As in legacy Bios, MP table is required to place in E/F Seg, -+ So here we just check if the range is E/F seg, -+ and if Not, assume the Memory type is EfiACPIMemoryNVS/EfiRuntimeServicesData -+Arguments: -+ Table - pointer to the table -+ -+Returns: -+ EFI_SUCEESS - Convert Table successfully -+ Other - Failed -+ -+--*/ -+{ -+ UINT32 Data32; -+ UINT32 FPLength; -+ EFI_LEGACY_MP_TABLE_FLOATING_POINTER *MpsFloatingPointerOri; -+ EFI_LEGACY_MP_TABLE_FLOATING_POINTER *MpsFloatingPointerNew; -+ EFI_LEGACY_MP_TABLE_HEADER *MpsTableOri; -+ EFI_LEGACY_MP_TABLE_HEADER *MpsTableNew; -+ VOID *OemTableOri; -+ VOID *OemTableNew; -+ EFI_STATUS Status; -+ EFI_PHYSICAL_ADDRESS BufferPtr; -+ -+ // -+ // Get MP configuration Table -+ // -+ MpsFloatingPointerOri = (EFI_LEGACY_MP_TABLE_FLOATING_POINTER *)(UINTN)(*(UINT64*)(*Table)); -+ if (!(((UINTN)MpsFloatingPointerOri <= 0x100000) && -+ ((UINTN)MpsFloatingPointerOri >= 0xF0000))){ -+ return EFI_SUCCESS; -+ } -+ // -+ // Get Floating pointer structure length -+ // -+ FPLength = MpsFloatingPointerOri->Length * 16; -+ Data32 = FPLength + SYS_TABLE_PAD (FPLength); -+ MpsTableOri = (EFI_LEGACY_MP_TABLE_HEADER *)(UINTN)(MpsFloatingPointerOri->PhysicalAddress); -+ if (MpsTableOri != NULL) { -+ Data32 += MpsTableOri->BaseTableLength; -+ Data32 += MpsTableOri->ExtendedTableLength; -+ if (MpsTableOri->OemTablePointer != 0x00) { -+ Data32 += SYS_TABLE_PAD (Data32); -+ Data32 += MpsTableOri->OemTableSize; -+ } -+ } else { -+ return EFI_SUCCESS; -+ } -+ // -+ // Relocate memory -+ // -+ BufferPtr = EFI_SYSTEM_TABLE_MAX_ADDRESS; -+ Status = gBS->AllocatePages ( -+ AllocateMaxAddress, -+ EfiACPIMemoryNVS, -+ EFI_SIZE_TO_PAGES(Data32), -+ &BufferPtr -+ ); -+ ASSERT_EFI_ERROR (Status); -+ MpsFloatingPointerNew = (EFI_LEGACY_MP_TABLE_FLOATING_POINTER *)(UINTN)BufferPtr; -+ CopyMem (MpsFloatingPointerNew, MpsFloatingPointerOri, FPLength); -+ // -+ // If Mp Table exists -+ // -+ if (MpsTableOri != NULL) { -+ // -+ // Get Mps table length, including Ext table -+ // -+ BufferPtr = BufferPtr + FPLength + SYS_TABLE_PAD (FPLength); -+ MpsTableNew = (EFI_LEGACY_MP_TABLE_HEADER *)(UINTN)BufferPtr; -+ CopyMem (MpsTableNew, MpsTableOri, MpsTableOri->BaseTableLength + MpsTableOri->ExtendedTableLength); -+ -+ if ((MpsTableOri->OemTableSize != 0x0000) && (MpsTableOri->OemTablePointer != 0x0000)){ -+ BufferPtr += MpsTableOri->BaseTableLength + MpsTableOri->ExtendedTableLength; -+ BufferPtr += SYS_TABLE_PAD (BufferPtr); -+ OemTableNew = (VOID *)(UINTN)BufferPtr; -+ OemTableOri = (VOID *)(UINTN)MpsTableOri->OemTablePointer; -+ CopyMem (OemTableNew, OemTableOri, MpsTableOri->OemTableSize); -+ MpsTableNew->OemTablePointer = (UINT32)(UINTN)OemTableNew; -+ } -+ MpsTableNew->Checksum = 0; -+ MpsTableNew->Checksum = CalculateCheckSum8 ((UINT8*)MpsTableNew, MpsTableOri->BaseTableLength); -+ MpsFloatingPointerNew->PhysicalAddress = (UINT32)(UINTN)MpsTableNew; -+ MpsFloatingPointerNew->Checksum = 0; -+ MpsFloatingPointerNew->Checksum = CalculateCheckSum8 ((UINT8*)MpsFloatingPointerNew, FPLength); -+ } -+ // -+ // Change the pointer -+ // -+ *Table = MpsFloatingPointerNew; -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ Lock the ConsoleIn device in system table. All key -+ presses will be ignored until the Password is typed in. The only way to -+ disable the password is to type it in to a ConIn device. -+ -+ @param Password Password used to lock ConIn device. -+ -+ @retval EFI_SUCCESS lock the Console In Spliter virtual handle successfully. -+ @retval EFI_UNSUPPORTED Password not found -+ -+**/ -+EFI_STATUS -+EFIAPI -+LockKeyboards ( -+ IN CHAR16 *Password -+ ) -+{ -+ return EFI_UNSUPPORTED; -+} -+ -+/** -+ This function locks platform flash that is not allowed to be updated during normal boot path. -+ The flash layout is platform specific. -+ -+ **/ -+VOID -+EFIAPI -+PlatformBdsLockNonUpdatableFlash ( -+ VOID -+ ) -+{ -+ return; -+} -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h -new file mode 100644 -index 0000000000..d447f77747 ---- /dev/null -+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h -@@ -0,0 +1,288 @@ -+/*++ -+ -+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+Module Name: -+ -+ BdsPlatform.h -+ -+Abstract: -+ -+ Head file for BDS Platform specific code -+ -+--*/ -+ -+#ifndef _PLATFORM_SPECIFIC_BDS_PLATFORM_H_ -+#define _PLATFORM_SPECIFIC_BDS_PLATFORM_H_ -+ -+ -+#include <PiDxe.h> -+ -+#include <IndustryStandard/Pci.h> -+#include <IndustryStandard/Acpi.h> -+#include <IndustryStandard/SmBios.h> -+#include <IndustryStandard/LegacyBiosMpTable.h> -+ -+#include <Library/DebugLib.h> -+#include <Library/BaseMemoryLib.h> -+#include <Library/UefiBootServicesTableLib.h> -+#include <Library/MemoryAllocationLib.h> -+#include <Library/BaseLib.h> -+#include <Library/PcdLib.h> -+#include <Library/GenericBdsLib.h> -+#include <Library/PlatformBdsLib.h> -+#include <Library/HobLib.h> -+#include <Library/UefiLib.h> -+#include <Library/DxeServicesTableLib.h> -+#include <Library/DevicePathLib.h> -+ -+#include <Protocol/PciIo.h> -+ -+#include <Guid/Acpi.h> -+#include <Guid/SmBios.h> -+#include <Guid/Mps.h> -+#include <Guid/HobList.h> -+#include <Guid/PciExpressBaseAddress.h> -+#include <Guid/GlobalVariable.h> -+#include <Guid/LdrMemoryDescriptor.h> -+ -+extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[]; -+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[]; -+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[]; -+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[]; -+extern ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode; -+extern ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode; -+extern UART_DEVICE_PATH gUartDeviceNode; -+extern VENDOR_DEVICE_PATH gTerminalTypeDeviceNode; -+// -+// -+// -+#define VarConsoleInpDev L"ConInDev" -+#define VarConsoleInp L"ConIn" -+#define VarConsoleOutDev L"ConOutDev" -+#define VarConsoleOut L"ConOut" -+#define VarErrorOutDev L"ErrOutDev" -+#define VarErrorOut L"ErrOut" -+ -+#define PCI_DEVICE_PATH_NODE(Func, Dev) \ -+ { \ -+ { \ -+ HARDWARE_DEVICE_PATH, \ -+ HW_PCI_DP, \ -+ { \ -+ (UINT8) (sizeof (PCI_DEVICE_PATH)), \ -+ (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \ -+ } \ -+ }, \ -+ (Func), \ -+ (Dev) \ -+ } -+ -+#define PNPID_DEVICE_PATH_NODE(PnpId) \ -+ { \ -+ { \ -+ ACPI_DEVICE_PATH, \ -+ ACPI_DP, \ -+ { \ -+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \ -+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \ -+ } \ -+ }, \ -+ EISA_PNP_ID((PnpId)), \ -+ 0 \ -+ } -+ -+#define gPciRootBridge \ -+ PNPID_DEVICE_PATH_NODE(0x0A03) -+ -+#define gPciIsaBridge \ -+ PCI_DEVICE_PATH_NODE(0, 0x1f) -+ -+#define gP2PBridge \ -+ PCI_DEVICE_PATH_NODE(0, 0x1e) -+ -+#define gPnpPs2Keyboard \ -+ PNPID_DEVICE_PATH_NODE(0x0303) -+ -+#define gPnp16550ComPort \ -+ PNPID_DEVICE_PATH_NODE(0x0501) -+ -+#define gUart \ -+ { \ -+ { \ -+ MESSAGING_DEVICE_PATH, \ -+ MSG_UART_DP, \ -+ { \ -+ (UINT8) (sizeof (UART_DEVICE_PATH)), \ -+ (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \ -+ } \ -+ }, \ -+ 0, \ -+ 115200, \ -+ 8, \ -+ 1, \ -+ 1 \ -+ } -+ -+#define gPcAnsiTerminal \ -+ { \ -+ { \ -+ MESSAGING_DEVICE_PATH, \ -+ MSG_VENDOR_DP, \ -+ { \ -+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \ -+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \ -+ } \ -+ }, \ -+ DEVICE_PATH_MESSAGING_PC_ANSI \ -+ } -+ -+#define gEndEntire \ -+ { \ -+ END_DEVICE_PATH_TYPE, \ -+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \ -+ { \ -+ END_DEVICE_PATH_LENGTH, \ -+ 0 \ -+ } \ -+ } -+ -+#define PCI_CLASS_SCC 0x07 -+#define PCI_SUBCLASS_SERIAL 0x00 -+#define PCI_IF_16550 0x02 -+#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550) -+ -+#define EFI_SYSTEM_TABLE_MAX_ADDRESS 0xFFFFFFFF -+#define SYS_TABLE_PAD(ptr) (((~ptr) +1) & 0x07 ) -+// -+// Platform Root Bridge -+// -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_ROOT_BRIDGE_DEVICE_PATH; -+ -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ PCI_DEVICE_PATH IsaBridge; -+ ACPI_HID_DEVICE_PATH Keyboard; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_DUMMY_ISA_KEYBOARD_DEVICE_PATH; -+ -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ PCI_DEVICE_PATH IsaBridge; -+ ACPI_HID_DEVICE_PATH IsaSerial; -+ UART_DEVICE_PATH Uart; -+ VENDOR_DEVICE_PATH TerminalType; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_DUMMY_ISA_SERIAL_DEVICE_PATH; -+ -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ PCI_DEVICE_PATH VgaDevice; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_DUMMY_PCI_VGA_DEVICE_PATH; -+ -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ PCI_DEVICE_PATH PciBridge; -+ PCI_DEVICE_PATH SerialDevice; -+ UART_DEVICE_PATH Uart; -+ VENDOR_DEVICE_PATH TerminalType; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_DUMMY_PCI_SERIAL_DEVICE_PATH; -+ -+// -+// the short form device path for Usb keyboard -+// -+#define CLASS_HID 3 -+#define SUBCLASS_BOOT 1 -+#define PROTOCOL_KEYBOARD 1 -+ -+typedef struct { -+ USB_CLASS_DEVICE_PATH UsbClass; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} USB_CLASS_FORMAT_DEVICE_PATH; -+ -+extern PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0; -+ -+// -+// Platform BDS Functions -+// -+VOID -+PlatformBdsGetDriverOption ( -+ IN LIST_ENTRY *BdsDriverLists -+ ); -+ -+EFI_STATUS -+BdsMemoryTest ( -+ EXTENDMEM_COVERAGE_LEVEL Level -+ ); -+ -+EFI_STATUS -+PlatformBdsShowProgress ( -+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground, -+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground, -+ CHAR16 *Title, -+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor, -+ UINTN Progress, -+ UINTN PreviousValue -+ ); -+ -+VOID -+PlatformBdsConnectSequence ( -+ VOID -+ ); -+ -+EFI_STATUS -+ProcessCapsules ( -+ EFI_BOOT_MODE BootMode -+ ); -+ -+EFI_STATUS -+PlatformBdsConnectConsole ( -+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole -+ ); -+ -+EFI_STATUS -+PlatformBdsNoConsoleAction ( -+ VOID -+ ); -+ -+EFI_STATUS -+ConvertMpsTable ( -+ IN OUT VOID **Table -+ ); -+ -+EFI_STATUS -+ConvertSmbiosTable ( -+ IN OUT VOID **Table -+ ); -+ -+EFI_STATUS -+ConvertAcpiTable ( -+ IN UINTN TableLen, -+ IN OUT VOID **Table -+ ); -+ -+EFI_STATUS -+ConvertSystemTable ( -+ IN EFI_GUID *TableGuid, -+ IN OUT VOID **Table -+ ); -+ -+VOID -+PlatformBdsEnterFrontPage ( -+ IN UINT16 TimeoutDefault, -+ IN BOOLEAN ConnectAllHappened -+ ); -+ -+#endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_ -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -new file mode 100644 -index 0000000000..578c74afae ---- /dev/null -+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -@@ -0,0 +1,65 @@ -+## @file -+# -+# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved. -+# This program and the accompanying materials -+# are licensed and made available under the terms and conditions of the BSD License -+# which accompanies this distribution. The full text of the license may be found at -+# http://opensource.org/licenses/bsd-license.php -+# -+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+# -+# Module Name: -+# -+# PlatformBds.inf -+# -+# Abstract: -+# -+# Component description file for Bds module. -+# -+## -+ -+[Defines] -+ INF_VERSION = 0x00010005 -+ BASE_NAME = CorebootBds -+ FILE_GUID = A6F691AC-31C8-4444-854C-E2C1A6950F92 -+ MODULE_TYPE = DXE_DRIVER -+ VERSION_STRING = 1.0 -+ LIBRARY_CLASS = PlatformBdsLib|DXE_DRIVER -+ -+[Sources] -+ BdsPlatform.c -+ PlatformData.c -+ BdsPlatform.h -+ -+[Packages] -+ MdePkg/MdePkg.dec -+ MdeModulePkg/MdeModulePkg.dec -+ CorebootModulePkg/CorebootModulePkg.dec -+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec -+ -+[LibraryClasses] -+ BaseLib -+ MemoryAllocationLib -+ UefiBootServicesTableLib -+ BaseMemoryLib -+ DebugLib -+ PcdLib -+ GenericBdsLib -+ HobLib -+ UefiLib -+ DevicePathLib -+ -+[Guids] -+ gEfiGlobalVariableGuid -+ gEfiPciExpressBaseAddressGuid -+ gEfiAcpi20TableGuid -+ gEfiMpsTableGuid -+ gEfiSmbiosTableGuid -+ gEfiAcpiTableGuid -+ gLdrMemoryDescriptorGuid -+ -+[Pcd] -+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut -+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile -+ -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c b/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c -new file mode 100644 -index 0000000000..fbdcc7de81 ---- /dev/null -+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c -@@ -0,0 +1,161 @@ -+/*++ -+ -+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+Module Name: -+ -+ PlatformData.c -+ -+Abstract: -+ -+ Defined the platform specific device path which will be used by -+ platform Bbd to perform the platform policy connect. -+ -+--*/ -+ -+#include "BdsPlatform.h" -+ -+// -+// Predefined platform default time out value -+// -+UINT16 gPlatformBootTimeOutDefault = 3; -+ -+ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode = gPnpPs2Keyboard; -+ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort; -+UART_DEVICE_PATH gUartDeviceNode = gUart; -+VENDOR_DEVICE_PATH gTerminalTypeDeviceNode = gPcAnsiTerminal; -+ -+// -+// Predefined platform root bridge -+// -+PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = { -+ gPciRootBridge, -+ gEndEntire -+}; -+ -+EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[] = { -+ (EFI_DEVICE_PATH_PROTOCOL *) &gPlatformRootBridge0, -+ NULL -+}; -+ -+USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = { -+ { -+ { -+ MESSAGING_DEVICE_PATH, -+ MSG_USB_CLASS_DP, -+ { -+ (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)), -+ (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) -+ } -+ }, -+ 0xffff, // VendorId -+ 0xffff, // ProductId -+ CLASS_HID, // DeviceClass -+ SUBCLASS_BOOT, // DeviceSubClass -+ PROTOCOL_KEYBOARD // DeviceProtocol -+ }, -+ -+ { -+ END_DEVICE_PATH_TYPE, -+ END_ENTIRE_DEVICE_PATH_SUBTYPE, -+ { -+ END_DEVICE_PATH_LENGTH, -+ 0 -+ } -+ } -+}; -+ -+/* -+// -+// Platform specific Dummy ISA keyboard device path -+// -+PLATFORM_DUMMY_ISA_KEYBOARD_DEVICE_PATH gDummyIsaKeyboardDevicePath = { -+ gPciRootBridge, -+ gPciIsaBridge, -+ gPnpPs2Keyboard, -+ gEndEntire -+}; -+ -+// -+// Platform specific Dummy ISA serial device path -+// -+PLATFORM_DUMMY_ISA_SERIAL_DEVICE_PATH gDummyIsaSerialDevicePath = { -+ gPciRootBridge, -+ gPciIsaBridge, -+ gPnp16550ComPort, -+ gUart, -+ gPcAnsiTerminal, -+ gEndEntire -+}; -+ -+// -+// Platform specific Dummy PCI VGA device path -+// -+PLATFORM_DUMMY_PCI_VGA_DEVICE_PATH gDummyPciVgaDevicePath = { -+ gPciRootBridge, -+ PCI_DEVICE_PATH_NODE(0, 0x2), -+ gEndEntire -+}; -+ -+// -+// Platform specific Dummy PCI serial device path -+// -+PLATFORM_DUMMY_PCI_SERIAL_DEVICE_PATH gDummyPciSerialDevicePath = { -+ gPciRootBridge, -+ gP2PBridge, -+ PCI_DEVICE_PATH_NODE(0, 0x0), -+ gUart, -+ gPcAnsiTerminal, -+ gEndEntire -+}; -+*/ -+// -+// Predefined platform default console device path -+// -+BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = { -+ // -+ // need update dynamically -+ // -+// { -+// (EFI_DEVICE_PATH_PROTOCOL *) &gDummyIsaSerialDevicePath, -+// (CONSOLE_OUT | CONSOLE_IN | STD_ERROR) -+// }, -+// { -+// (EFI_DEVICE_PATH_PROTOCOL *) &gDummyIsaKeyboardDevicePath, -+// (CONSOLE_IN | STD_ERROR) -+// }, -+// { -+// (EFI_DEVICE_PATH_PROTOCOL *) &gDummyPciVgaDevicePath, -+// CONSOLE_OUT -+// }, -+// { -+// (EFI_DEVICE_PATH_PROTOCOL *) &gDummyPciSerialDevicePath, -+// (CONSOLE_OUT | CONSOLE_IN | STD_ERROR) -+// }, -+ { -+ (EFI_DEVICE_PATH_PROTOCOL*) &gUsbClassKeyboardDevicePath, -+ CONSOLE_IN -+ }, -+ { -+ NULL, -+ 0 -+ } -+}; -+ -+// -+// Predefined platform specific driver option -+// -+EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[] = { NULL }; -+ -+// -+// Predefined platform connect sequence -+// -+EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[] = { NULL }; -+ -diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -index a39e3999ba..623ff9c344 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf -+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -@@ -95,8 +95,9 @@ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntime - - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF UefiCpuPkg/CpuDxe/CpuDxe.inf --INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf --INF MdeModulePkg/Application/UiApp/UiApp.inf -+ -+INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf -+ - !if $(USE_HPET_TIMER) == TRUE - INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf - !else -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -index e838aca61d..a329b78f08 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -@@ -165,6 +165,7 @@ - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf -+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf -@@ -183,7 +184,7 @@ - ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf - SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf - PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf -- PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf -+ PlatformBdsLib|CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf - IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf - CbPlatformSupportLib|CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.inf - -@@ -396,13 +397,12 @@ - # - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - UefiCpuPkg/CpuDxe/CpuDxe.inf -- MdeModulePkg/Universal/BdsDxe/BdsDxe.inf -- MdeModulePkg/Application/UiApp/UiApp.inf { -+ -+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf { - <LibraryClasses> -- NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf -- NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf -- NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf -+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } -+ - !if $(USE_HPET_TIMER) == TRUE - PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf - !else -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -index c25d821fd4..790efd7810 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -@@ -165,6 +165,7 @@ - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf -+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf -@@ -183,7 +184,7 @@ - ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf - SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf - PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf -- PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf -+ PlatformBdsLib|CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf - IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf - CbPlatformSupportLib|CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.inf - -@@ -397,13 +398,12 @@ - # - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - UefiCpuPkg/CpuDxe/CpuDxe.inf -- MdeModulePkg/Universal/BdsDxe/BdsDxe.inf -- MdeModulePkg/Application/UiApp/UiApp.inf { -+ -+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf { - <LibraryClasses> -- NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf -- NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf -- NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf -+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } -+ - !if $(USE_HPET_TIMER) == TRUE - PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf - !else --- -2.13.2.932.g7449e964c-goog - diff --git a/payloads/external/tianocore/patches/03_Library_EndofDXE.patch b/payloads/external/tianocore/patches/03_Library_EndofDXE.patch deleted file mode 100644 index 02ba42b..0000000 --- a/payloads/external/tianocore/patches/03_Library_EndofDXE.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 760f1cafdd689beedc8418ab89e856b54296389c Mon Sep 17 00:00:00 2001 -From: CoolStar <coolstarorganization(a)gmail.com> -Date: Sun, 4 Dec 2016 12:07:30 -0800 -Subject: [PATCH] CorebootBdsLib: Call End of DXE event to allow booting 3rd - party efi binaries. - ---- - .../Library/CorebootBdsLib/BdsPlatform.c | 42 ++++++++++++++++++++++ - .../Library/CorebootBdsLib/PlatformBds.inf | 1 + - 2 files changed, 43 insertions(+) - -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -index b6253a17f8..cf3e5320cb 100644 ---- a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -@@ -1129,6 +1129,46 @@ Returns: - Status = BaseMemoryTest (MemoryTestLevel); - } - -+VOID -+EFIAPI -+InternalBdsEmptyCallbackFuntion ( -+ IN EFI_EVENT Event, -+ IN VOID *Context -+ ) -+{ -+ return; -+} -+ -+VOID -+InstallReadyToLock ( -+ VOID -+ ) -+{ -+ EFI_STATUS Status; -+ EFI_EVENT EndOfDxeEvent; -+ -+ DEBUG((DEBUG_INFO,"InstallReadyToLock entering......\n")); -+ // -+ // Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter -+ // Since PI1.2.1, we need signal EndOfDxe as ExitPmAuth -+ // -+ Status = gBS->CreateEventEx ( -+ EVT_NOTIFY_SIGNAL, -+ TPL_CALLBACK, -+ InternalBdsEmptyCallbackFuntion, -+ NULL, -+ &gEfiEndOfDxeEventGroupGuid, -+ &EndOfDxeEvent -+ ); -+ ASSERT_EFI_ERROR (Status); -+ gBS->SignalEvent (EndOfDxeEvent); -+ gBS->CloseEvent (EndOfDxeEvent); -+ DEBUG((DEBUG_INFO,"All EndOfDxe callbacks have returned successfully\n")); -+ -+ DEBUG((DEBUG_INFO,"InstallReadyToLock end\n")); -+ return; -+} -+ - VOID - EFIAPI - PlatformBdsPolicyBehavior ( -@@ -1164,6 +1204,8 @@ Returns: - EFI_INPUT_KEY Key; - EFI_BOOT_MODE BootMode; - -+ InstallReadyToLock(); -+ - // - // Init the time out value - // -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -index 578c74afae..992bd846bd 100644 ---- a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -@@ -58,6 +58,7 @@ - gEfiSmbiosTableGuid - gEfiAcpiTableGuid - gLdrMemoryDescriptorGuid -+ gEfiEndOfDxeEventGroupGuid - - [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut --- -2.13.2.725.g09c95d1e9-goog - diff --git a/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch b/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch deleted file mode 100644 index e90b70e..0000000 --- a/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 77c5dfcce842819215490fe63c481860fa7d752d Mon Sep 17 00:00:00 2001 -From: CoolStar <coolstarorganization(a)gmail.com> -Date: Sun, 4 Dec 2016 11:50:00 -0800 -Subject: [PATCH] CorebootPayloadPkg: Add PS/2 keyboard drivers. - ---- - CorebootPayloadPkg/CorebootPayloadPkg.fdf | 3 +++ - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 3 +++ - CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 3 +++ - 3 files changed, 9 insertions(+) - -diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -index 347e9c75ce..a347af0c9a 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf -+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -@@ -132,6 +132,9 @@ INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - # ISA Support - # - INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf -+INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf -+INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf -+INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf - - # - # Console Support -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -index 5ce823bb95..60ee064c59 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -@@ -492,6 +492,9 @@ - # ISA Support - # - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf -+ PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf -+ IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf -+ IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf - - # - # Console Support -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -index fea297a77a..167329c897 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -@@ -493,6 +493,9 @@ - # ISA Support - # - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf -+ PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf -+ IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf -+ IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf - - # - # Console Support --- -2.13.2.725.g09c95d1e9-goog - diff --git a/payloads/external/tianocore/patches/05_CorebootPayloadPkg_noserial.patch b/payloads/external/tianocore/patches/05_CorebootPayloadPkg_noserial.patch deleted file mode 100644 index 0e84b7d..0000000 --- a/payloads/external/tianocore/patches/05_CorebootPayloadPkg_noserial.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 77f75370d6fbfefb04456f6e1c32c85d4bac8bf5 Mon Sep 17 00:00:00 2001 -From: Matt Devo <matt.devillier(a)gmail.com> -Date: Thu, 23 Feb 2017 14:11:14 -0600 -Subject: [PATCH] CorebootPayloadPkg: don't use serial output - ---- - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 2 +- - CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -index 1d80fc4f5c..ce360c9e9e 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -@@ -261,7 +261,7 @@ - # - ################################################################################ - [PcdsFeatureFlag] -- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE -+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -index 52b26eb3d0..a27b0873a1 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -@@ -261,7 +261,7 @@ - # - ################################################################################ - [PcdsFeatureFlag] -- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE -+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE --- -2.13.2.725.g09c95d1e9-goog - diff --git a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch deleted file mode 100644 index e75052b..0000000 --- a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch +++ /dev/null @@ -1,26 +0,0 @@ -From ef89b11ce6f93c96fbd1753a8006dd9c3da212e0 Mon Sep 17 00:00:00 2001 -From: ReddestDream <reddestdream(a)gmail.com> -Date: Wed, 3 May 2017 00:13:28 -0400 -Subject: [PATCH] CbSupportPei: prevent lower coreboot table from being - overwritten - -Exclude the bottom 4kb from being included in System Memory HoB - -diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c -index 262e6b9..d3c5723 100755 ---- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c -+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c -@@ -261,8 +261,9 @@ CbPeiEntryPoint ( - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ), -- (EFI_PHYSICAL_ADDRESS)(0), -- (UINT64)(0xA0000) -+ // Lower 640KB, except for first 4KB where the lower coreboot pointer ("LBIO") resides -+ (EFI_PHYSICAL_ADDRESS)(0 + 0x1000), -+ (UINT64)(0xA0000 - 0x1000) - ); - - --- -2.14.0 diff --git a/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch b/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch deleted file mode 100644 index 6370efc..0000000 --- a/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 07dec11fe965e73cfef7df38af70c945b6ff21a2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur(a)aheymans.xyz> -Date: Wed, 24 Jan 2018 10:07:08 +0100 -Subject: [PATCH] CorebootPayloadPkg: Use correct BytesPerScanLine - -Fetch BytesPerScanLine from coreboot table to reflect how the actual -framebuffer is set up instead of guessing it from the horizontal -resolution. - -This fixes a garbled display when HorizontalResolution * (BitsPerPixel -/ 8) and pFbInfo->BytesPerScanLine don't match. - -Contributed-under: TianoCore Contribution Agreement 1.1 -Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> - -diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c -index 37d6def7f7..6790617033 100644 ---- a/CorebootPayloadPkg/FbGop/FbGop.c -+++ b/CorebootPayloadPkg/FbGop/FbGop.c -@@ -822,7 +822,7 @@ FbGopCheckForVbe ( - BitsPerPixel = pFbInfo->BitsPerPixel; - HorizontalResolution = pFbInfo->HorizontalResolution; - VerticalResolution = pFbInfo->VerticalResolution; -- BytesPerScanLine = HorizontalResolution * (BitsPerPixel / 8); -+ BytesPerScanLine = pFbInfo->BytesPerScanLine; - - ModeBuffer = (FB_VIDEO_MODE_DATA *) AllocatePool ( - ModeNumber * sizeof (FB_VIDEO_MODE_DATA) --- -2.16.1 - diff --git a/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch b/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch deleted file mode 100644 index 06ddd56..0000000 --- a/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch +++ /dev/null @@ -1,38 +0,0 @@ -From b652262ed0dd554c44e7b1bf7134d3458f5edef1 Mon Sep 17 00:00:00 2001 -From: Patrick Rudolph <siro(a)das-labor.org> -Date: Sun, 17 Jun 2018 08:44:51 +0200 -Subject: [PATCH] BaseTools: Fix building with -Werror=stringop-truncation - -Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> ---- - BaseTools/Source/C/GenVtf/GenVtf.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/BaseTools/Source/C/GenVtf/GenVtf.c b/BaseTools/Source/C/GenVtf/GenVtf.c -index acc142a6d1..5d77016eba 100644 ---- a/BaseTools/Source/C/GenVtf/GenVtf.c -+++ b/BaseTools/Source/C/GenVtf/GenVtf.c -@@ -129,9 +129,9 @@ Returns: - } else { - Length = strlen(Str); - if (Length < 4) { -- strncpy (TemStr + 4 - Length, Str, Length); -+ memcpy (TemStr + 4 - Length, Str, Length); - } else { -- strncpy (TemStr, Str + Length - 4, 4); -+ memcpy (TemStr, Str + Length - 4, 4); - } - - sscanf ( -@@ -1529,7 +1529,7 @@ Returns: - // - FitStartPtr = (FIT_TABLE *) RelativeAddress; - -- strncpy ((CHAR8 *) &FitStartPtr->CompAddress, FIT_SIGNATURE, 8); // "_FIT_ " -+ memcpy ((CHAR8 *) &FitStartPtr->CompAddress, FIT_SIGNATURE, 8); // "_FIT_ " - assert (((VtfInfo->CompSize & 0x00FFFFFF) % 16) == 0); - FitStartPtr->CompSize = (VtfInfo->CompSize & 0x00FFFFFF) / 16; - FitStartPtr->CompVersion = MAKE_VERSION (VtfInfo->MajorVer, VtfInfo->MinorVer); --- -2.17.0 - diff --git a/payloads/external/tianocore/patches/09_gcc7-Fix-building-with-fpermissive.patch b/payloads/external/tianocore/patches/09_gcc7-Fix-building-with-fpermissive.patch deleted file mode 100644 index 7016759..0000000 --- a/payloads/external/tianocore/patches/09_gcc7-Fix-building-with-fpermissive.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 5546ab29b2c0c2fc3a963bc71221918dc77b6152 Mon Sep 17 00:00:00 2001 -From: Patrick Rudolph <siro(a)das-labor.org> -Date: Sun, 17 Jun 2018 08:53:25 +0200 -Subject: [PATCH] gcc7: Fix building with -fpermissive - -Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> ---- - BaseTools/Source/C/VfrCompile/VfrUtilityLib.cpp | 2 +- - MdeModulePkg/Library/UefiHiiLib/HiiLib.c | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/BaseTools/Source/C/VfrCompile/VfrUtilityLib.cpp b/BaseTools/Source/C/VfrCompile/VfrUtilityLib.cpp -index 3ca57ed741..4fa066dd9f 100644 ---- a/BaseTools/Source/C/VfrCompile/VfrUtilityLib.cpp -+++ b/BaseTools/Source/C/VfrCompile/VfrUtilityLib.cpp -@@ -3372,7 +3372,7 @@ CVfrStringDB::GetVarStoreNameFormStringId ( - UINT8 BlockType; - EFI_HII_STRING_PACKAGE_HDR *PkgHeader; - -- if (mStringFileName == '\0' ) { -+ if (mStringFileName == NULL ) { - return NULL; - } - -diff --git a/MdeModulePkg/Library/UefiHiiLib/HiiLib.c b/MdeModulePkg/Library/UefiHiiLib/HiiLib.c -index 857950118f..de0aa5f7bc 100644 ---- a/MdeModulePkg/Library/UefiHiiLib/HiiLib.c -+++ b/MdeModulePkg/Library/UefiHiiLib/HiiLib.c -@@ -2181,7 +2181,7 @@ InternalHiiIfrValueAction ( - - StringPtr = ConfigAltResp; - -- while (StringPtr != L'\0') { -+ while (StringPtr != NULL) { - // - // 1. Find <ConfigHdr> GUID=...&NAME=...&PATH=... - // --- -2.17.0 - diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd index 65d22c3..d2b6364 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd @@ -1,21 +1,22 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x380000 { + SI_ALL@0x0 0x400000 { SI_DESC@0x0 0x1000 - SI_EC@0x01000 0x80000 - SI_ME@0x81000 0x2ff000 + SI_EC@0x01000 0x100000 + SI_GBE@0x101000 0x2000 + SI_ME@0x103000 0x2fd000 } - SI_BIOS@0x380000 0xc80000 { - RW_SECTION_A@0x0 0x368000 { + SI_BIOS@0x400000 0xc00000 { + RW_SECTION_A@0x0 0x328000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x317fc0 + RW_FWID_A@0x327fc0 0x40 } - RW_SECTION_B@0x368000 0x368000 { + RW_SECTION_B@0x328000 0x328000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x317fc0 + RW_FWID_B@0x327fc0 0x40 } - RW_MISC@0x6d0000 0x30000 { + RW_MISC@0x650000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -28,9 +29,9 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - SMMSTORE@0x700000 0x40000 - RW_LEGACY(CBFS)@0x740000 0x1c0000 - WP_RO@0x900000 0x380000 { + SMMSTORE@0x680000 0x40000 + RW_LEGACY(CBFS)@0x6c0000 0x1c0000 + WP_RO@0x880000 0x380000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { diff --git a/src/mainboard/intel/coffeelake_rvp/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/Makefile.inc index 2746453..4e02bce 100644 --- a/src/mainboard/intel/coffeelake_rvp/Makefile.inc +++ b/src/mainboard/intel/coffeelake_rvp/Makefile.inc @@ -16,6 +16,7 @@ bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-y += early_init.c verstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/intel/coffeelake_rvp/bootblock.c b/src/mainboard/intel/coffeelake_rvp/bootblock.c index cac219e..8917f41 100644 --- a/src/mainboard/intel/coffeelake_rvp/bootblock.c +++ b/src/mainboard/intel/coffeelake_rvp/bootblock.c @@ -24,4 +24,5 @@ pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); + wilco_ec_early_init(); } diff --git a/src/mainboard/intel/coffeelake_rvp/early_init.c b/src/mainboard/intel/coffeelake_rvp/early_init.c new file mode 100644 index 0000000..7c0ad9b --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/early_init.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pnp_def.h> +#include <baseboard/variants.h> + +#define PNP_CFG_IDX 0x2e +#define PNP_LDN_SERIAL 0x0d + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + outb(0x55, PNP_CFG_IDX); + outb(0x55, PNP_CFG_IDX); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + outb(0xaa, PNP_CFG_IDX); +} + +static void wilco_ec_serial_init(void) +{ + pnp_devfn_t dev = PNP_DEV(PNP_CFG_IDX, PNP_LDN_SERIAL); + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, PNP_IDX_IO1, cpu_to_be16(CONFIG_TTYS0_BASE)); + pnp_write_config(dev, PNP_IDX_IO0, 1); + pnp_exit_conf_state(dev); +} + +void wilco_ec_early_init(void) +{ + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + wilco_ec_serial_init(); +} diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index 7058be4..2665077 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -28,8 +28,8 @@ * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 4, 5, 6, 7 }, - .dqs_map[DDR_CH1] = { 1, 0, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, /* Baseboard uses 121, 81 and 100 rcomp resistors */ .rcomp_resistor = { 121, 81, 100 }, @@ -40,7 +40,7 @@ .rcomp_targets = { 100, 40, 20, 20, 26 }, /* Baseboard is an interleaved design */ - .dq_pins_interleaved = 1, + .dq_pins_interleaved = 0, /* Baseboard is using config 2 for vref_ca */ .vref_ca_config = 2, diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index 64ff69f..23e613e 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -36,4 +36,6 @@ struct nhlt; void variant_nhlt_init(struct nhlt *nhlt); +void wilco_ec_early_init(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb index 6bd90a5..f4bfcff 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb @@ -10,6 +10,7 @@ register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "1" + register "DebugConsent" = "3" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 256cf1b..c71ec39 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -82,8 +82,7 @@ select CONSOLE_SERIAL select BOOTBLOCK_CONSOLE select DRIVERS_UART - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250IO config UART_FOR_CONSOLE int "Index for LPSS UART port to use for console" -- To view, visit https://review.coreboot.org/28688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5449981baabcbb891e1036177307c58f5e2008ac Gerrit-Change-Number: 28688 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

1 0

Change in coreboot[master]: soc/amd/stoneyridge/romstage.c: Remove obsolete comment
by Richard Spiegel (Code Review) 19 Sep '18

19 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28687 Change subject: soc/amd/stoneyridge/romstage.c: Remove obsolete comment ...................................................................... soc/amd/stoneyridge/romstage.c: Remove obsolete comment When preparing transition of AGESA calls to romstage, I placed a comment indicating the place to move a particular call. Now that the AGESA call has been moved to romstage, the comment became obsolete. BUG=b:116095766 TEST=none. Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/romstage.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/28687/1 diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 78472d3..de22191 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -92,11 +92,6 @@ int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); int i; - /* - * When moving AGESA calls to romstage, place the call to - * bsp_agesa_call() here. - */ - console_init(); if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) -- To view, visit https://review.coreboot.org/28687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e Gerrit-Change-Number: 28687 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: mb/solidrun/solidpc: Do initial commit
by build bot (Jenkins) (Code Review) 19 Sep '18

19 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... Patch Set 5: (366 comments) https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… File src/mainboard/solidrun/solidpc/gpio.c: https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 53: // FED9C400: 80 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 54: // FED9C410: 80 03 11 00 00 00 C0 05-00 03 13 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 55: // FED9C420: 80 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 56: // FED9C430: 00 03 13 00 00 00 C0 05-80 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 67: /*SE00 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 69: /*SE02 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 70: /*SE03 */ { .pad_conf0 = 0x00130300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 71: /*SE04 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 73: /*SE06 */ { .pad_conf0 = 0x00130300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 74: /*SE07 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 78: // FED9C800: 81 03 91 00 00 00 C0 05-81 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 79: // FED9C810: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 80: // FED9C820: 80 03 11 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 81: // FED9C830: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 82: // FED9C840: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 83: // FED9C850: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 96: // NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ /* SDMMC1_D_3_CD_B */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 99: /*SE16 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 100: /*SE17 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 103: /*SE20 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 106: /*SE23 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 107: /*SE24 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 109: /*SE26 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 113: // FED9CC00: 81 03 91 00 00 00 C0 05-80 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 114: // FED9CC10: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 115: // FED9CC20: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 124: /*SE30 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 125: /*SE31 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 126: /*SE32 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 127: /*SE33 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 128: /*SE34 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 129: /*SE35 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 134: // FED9D000: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 135: // FED9D010: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 136: // FED9D020: 00 03 11 00 00 00 C0 05-02 81 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 137: // FED9D030: 00 03 11 00 00 00 C0 05-02 81 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 148: /*SE45 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 149: /*SE46 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 150: /*SE47 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 151: /*SE48 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 153: /*SE50 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 154: /*SE51 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 155: /*SE52 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 159: // FED9D400: 02 82 91 58 19 00 C0 05-02 81 91 00 00 00 C0 05 *...X............* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 160: // FED9D410: 01 82 91 4C 01 00 C0 05-81 03 91 00 00 00 C0 05 *...L............* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 161: // FED9D420: 02 81 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 162: // FED9D430: 02 81 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 163: // FED9D440: 81 03 91 00 00 00 C0 05-80 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 165: // GPI(trig_edge_low, L5, P_20K_H, non_maskable, en_rx_data, UNMASK_WAKE , NA), /* 60 SPI1_MISO */ /* PMIC_IRQ_1P8 */ /* Open drain? */ /* FIXME: InvRX_Enable - is this connected to the PMIC? */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 171: // GPIO_OUT_HIGH, /* 66 SPI1_CS1_B */ /* LAN P0 ISOLATE */ /* FIXME: check if this pin is actually used as P0 Isolate */ //FIXME: Find P1 isolate line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 176: /*SE60 */ { .pad_conf0 = 0x58918200, .pad_conf1 = 0x05C00019, .wake_mask = 1, .int_mask = 1, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 177: /*SE61 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 178: /*SE62 */ { .pad_conf0 = 0x4C918201, .pad_conf1 = 0x05C00001, .wake_mask = 0, .int_mask = 1, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 179: /*SE63 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 180: /*SE64 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 181: /*SE65 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 182: /*SE66 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 183: /*SE67 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 184: /*SE68 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 189: // FED9D800: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 190: // FED9D810: 01 82 91 14 01 00 C0 05-00 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 191: // FED9D820: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 192: // FED9D830: 00 02 91 10 04 00 C0 05-00 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 193: // FED9D840: 00 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 194: // FED9D850: 00 03 11 00 00 00 C0 05-FF FF FF FF FF FF FF FF *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 196: // Native_M1, /* 75 USB_OC1_B */ /* USB_OC1_B */ /* FIXME: pulls? */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 197: // Native_M1, /* 76 PMU_RESETBUTTON_B */ /* PMU_RESETBUTTON_B */ /* FIXME: pulls? */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 199: // Native_M1, /* 78 SDMMC3_PWR_EN_B */ /* SD_CARD_PWRDN_N */ /* FIXME: pulls? */ //FIXME: Connected? line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 201: // Native_M1, /* 80 USB_OC0_B */ /* USB_OC0_B */ /* FIXME: pulls? */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 202: // NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ /* SD_CARD_DET_N */ /* FIXME: Native M1, no pull, trig_level, invert */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 205: // Native_M1, /* 84 SDMMC1_RCLK */ /* SDMMC1_RCLK */ /* FIXME: no SPARE_PIN!? check if NC */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 206: // Native_M1, /* 85 SDMMC3_1P8_EN */ /* SD_CARD_PWR_EN */ /* FIXME: check if NC */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 208: /*SE75 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 209: /*SE76 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 210: /*SE77 */ { .pad_conf0 = 0x14918201, .pad_conf1 = 0x05C00001, .wake_mask = 1, .int_mask = 1, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 211: /*SE78 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 212: /*SE79 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 213: /*SE80 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 214: /*SE81 */ { .pad_conf0 = 0x10910300, .pad_conf1 = 0x05C00004, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 216: /*SE83 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 217: /*SE84 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 218: /*SE85 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 227: // FED84400: 01 03 91 00 00 00 C0 05-00 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 228: // FED84410: 00 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 229: // FED84420: 02 81 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 230: // FED84430: 01 03 91 00 00 00 C0 05-00 81 21 00 00 00 C0 05 *..........!.....* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 238: // Native_M1, /* 06 FST_SPI_CS0_B */ /* SPI_CS (SPI NOR on SOM) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 241: /*SW00 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 242: /*SW01 */ { .pad_conf0 = 0x00910300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 243: /*SW02 */ { .pad_conf0 = 0x00910300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 244: /*SW03 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 245: /*SW04 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 246: /*SW05 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 247: /*SW06 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 248: /*SW07 */ { .pad_conf0 = 0x00218100, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 252: // FED84800: 00 00 C0 04 00 00 C0 05-01 00 02 00 00 00 C0 04 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 253: // FED84810: 01 03 91 00 00 00 C0 05-00 00 01 00 00 00 C0 04 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 254: // FED84820: 01 03 91 00 00 00 C0 05-01 00 02 00 00 00 C0 04 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 255: // FED84830: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 258: // Native_M2, /* 16 UART1_RXD */ /* UART1_RXD */ //NOTE: set to UART0 for debugging line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 262: // Native_M2, /* 20 UART1_TXD */ /* UART1_TXD */ //NOTE: set to UART0 for debugging line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 266: /*SW15 */ GPIO_SKIP, //{ .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 267: /*SW16 */ GPIO_SKIP, //{ .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 268: /*SW17 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 270: /*SW19 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 272: /*SW21 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 273: /*SW22 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 277: // FED84C00: 01 03 12 00 00 00 C0 05-01 03 12 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 278: // FED84C10: 00 03 12 00 00 00 C0 05-00 03 12 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 279: // FED84C20: 00 03 11 00 20 00 C0 05-00 03 12 00 00 00 C0 05 *.... ...........* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 280: // FED84C30: 00 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 282: // Native_M2, /* 30 MF_HDA_CLK */ /* MF_HDA_CLK II GP_SSP_0_I2S_TXD */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 283: // Native_M2, /* 31 GPIO_SW31/MF_HDA_RSTB */ /* AUD_LINK_RST_N || I2S_0_CLK_R_AICO (AIC) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 284: // Native_M2, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ /* AUD_LINK_SDI0 (ALC282) || I2S_2_CLK_R_AICO (AIC) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 285: // Native_M2, /* 33 MF_HDA_SDO */ /* AUD_LINK_SDO_R||I2S_0_RXD_R_AICO (AIC) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 286: // GPIO_NC, /* 34 MF_HDA_DOCKRSTB */ /* I2S_2_TXD_R_AICO (AIC) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 287: // Native_M2, /* 35 MF_HDA_SYNC */ /* AUD_LINKSYNC_R|| I2S_0_FS_R_AICO (AIC) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 288: // GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ /* I2S_2_FS_R_AICO */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 289: // GPIO_NC, /* 37 MF_HDA_DOCKENB */ /* I2S_2_RXD_R_AICO(AIC) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 291: /*SW30 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 292: /*SW31 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 293: /*SW32 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 294: /*SW33 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 295: /*SW34 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 296: /*SW35 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 297: /*SW36 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 298: /*SW37 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 301: // FED85000: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 302: // FED85010: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 303: // FED85020: 01 03 91 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 304: // FED85030: 01 03 C1 00 20 00 C0 05-01 03 91 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 306: // GPIO_NC, /* 45 I2C5_SDA */ /* Touch Panel */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 307: // NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ /* I2C Audio | Touch PAD */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 309: // GPIO_NC, /* 48 I2C5_SCL */ /* Touch Panel */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 311: // NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ /* I2C Audio | Touch PAD */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 315: /*SW45 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 316: /*SW46 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 317: /*SW47 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 318: /*SW48 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 320: /*SW50 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 321: /*SW51 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 325: // FED85400: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 326: // FED85410: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 327: // FED85420: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 328: // FED85430: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 331: // GPIO_NC, /* 61 I2C0_SDA */ /* 3rd party Sensor Card */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 332: // GPIO_NC, /* 62 I2C2_SDA */ /* MIPI_CSI CAMERAS, FLASH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 334: // GPIO_NC, /* 64 I2C3_SDA */ /* MIPI_CSI CAMERAS, FLASH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 335: // GPIO_NC, /* 65 I2C0_SCL */ /* 3rd party Sensor Card */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 336: // GPIO_NC, /* 66 I2C2_SCL */ /* MIPI_CSI CAMERAS, FLASH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 337: // GPIO_NC, /* 67 I2C3_SCL */ /* MIPI_CSI CAMERAS, FLASH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 339: /*SW60 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 340: /*SW61 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 341: /*SW62 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 342: /*SW63 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 343: /*SW64 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 344: /*SW65 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 345: /*SW66 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 346: /*SW67 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 350: // FED85800: 00 80 11 00 00 00 C0 05-00 82 C1 0C 11 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 351: // FED85810: 01 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 352: // FED85820: 01 03 91 00 00 00 C0 05-02 00 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 353: // FED85830: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 355: // GPIO_NC, /* 75 SATA_GP0 */ /* TOUCH_PNL_RST_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 356: // GPIO_NC, /* 76 SATA_GP1 */ /* TOUCH_INT_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 357: // Native_M1, /* 77 SATA_LEDN */ /* SATA_LED_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 358: // Native_M1, /* 78 SATA_GP2 */ /* SATA_DEVSLP_R */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 359: // GPIO_NC, /* 79 MF_SMB_ALERTB */ /* MF_SMB_ALERTB */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 360: // Native_M1, /* 80 SATA_GP3 */ /* eMMC_RST_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 361: // GPIO_NC, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ /* MF_SMB_CLK */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 362: // GPIO_NC, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* MF_SMB_DATA */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 364: /*SW75 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 365: /*SW76 */ { .pad_conf0 = 0x0CC18200, .pad_conf1 = 0x05C00011, .wake_mask = 0, .int_mask = 1, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 366: /*SW77 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 367: /*SW78 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 369: /*SW80 */ { .pad_conf0 = 0x00110002, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 375: // FED85C00: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 376: // FED85C10: 00 03 11 00 00 00 C0 05-00 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 377: // FED85C20: 00 03 11 00 00 00 C0 05-00 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 378: // FED85C30: 00 03 11 00 00 00 C0 05-00 03 11 00 20 00 C0 05 *............ ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 380: // Native_M1, /* 90 PCIE_CLKREQ0B */ /* RTL8111G (CLKREQ_N) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 381: // Native_M1, /* 91 PCIE_CLKREQ1B */ /* NGFF(CLKREQ_N) */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 383: // Native_M1, /* 93 PCIE_CLKREQ2B */ /* On uSOM NIC CLK Request */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 385: // Native_M1, /* 95 PCIE_CLKREQ3B */ /* Tied to Micro SD */ //FIXME: What does this pin do? Is it even a CLKREQ? line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 389: /*SW90 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 390: /*SW91 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 392: /*SW93 */ { .pad_conf0 = 0x00910300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 394: /*SW95 */ { .pad_conf0 = 0x00910300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 406: // FED8C400: 02 81 11 00 00 00 C0 05-00 82 01 2C 21 00 C0 05 *...........,!...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 407: // FED8C410: 02 82 91 00 01 80 91 00-00 80 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 408: // FED8C420: 02 81 91 00 00 00 C0 05-02 81 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 409: // FED8C430: 03 82 91 00 01 80 91 00-00 81 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 410: // FED8C440: 03 82 91 00 01 80 91 00-FF FF FF FF FF FF FF FF *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 412: // GPIO_OUT_HIGH, /* 00 GPIO_DFX0 */ /* LAN P0 RESET */ //FIXME: Is this a reset? line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 422: /*N00 */ { .pad_conf0 = 0x00118102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 423: /*N01 */ { .pad_conf0 = 0x2C018200, .pad_conf1 = 0x05C00021, .wake_mask = 0, .int_mask = 1, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 425: /*N03 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 426: /*N04 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 427: /*N05 */ { .pad_conf0 = 0x00118102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 428: /*N06 */ { .pad_conf0 = 0x00918203, .pad_conf1 = 0x00918001, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 429: /*N07 */ { .pad_conf0 = 0x00918202, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 430: /*N08 */ { .pad_conf0 = 0x00918203, .pad_conf1 = 0x00918001, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 433: // FED8C800: 00 82 01 3C 01 00 C0 05-00 82 11 00 00 00 C0 05 *...<............* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 434: // FED8C810: 00 82 11 4C 01 00 C0 05-00 82 91 FC 01 00 C0 05 *...L............* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 435: // FED8C820: 01 03 16 00 00 00 C0 05-00 02 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 436: // FED8C830: 00 03 11 00 00 00 C0 05-01 03 96 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 437: // FED8C840: 00 03 91 00 00 00 C0 05-02 81 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 438: // FED8C850: 01 82 91 EC 01 00 C0 05-01 03 A1 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 439: // FED8C860: 00 82 11 00 00 00 C0 05-FF FF FF FF FF FF FF FF *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 444: // GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ /* GPIO_SUS7 */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 445: // Native_M6, /* 19 GPIO_SUS1 */ /* GPIO_SUS1 */ //NOTE: configured as PCI_WAKE1_N, but is just a pin on the headers line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 446: // Native_M1, /* 20 GPIO_SUS5 */ /* GPIO_SUS5 */ //FIXME: What's the native mode of this pin? docs only say strapping pin for Flash Descriptor Security Override line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 448: // Native_M6, /* 22 GPIO_SUS4 */ /* */ //NOTE: configired as PCI_WAKE4_N //FIXME: What's on this pin? line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 450: // Native_M6, /* 24 GPIO_SUS2 */ /* GPIO_SUS2 */ //NOTE: configured as PCI_WAKE2_N, but is just a pin on the headers line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 456: /*N15 */ { .pad_conf0 = 0x3C018200, .pad_conf1 = 0x05C00001, .wake_mask = 1, .int_mask = 1, .gpe = SCI }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 458: /*N17 */ { .pad_conf0 = 0x4C118200, .pad_conf1 = 0x05C00001, .wake_mask = 0, .int_mask = 1, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 459: /*N18 */ { .pad_conf0 = 0xFC918200, .pad_conf1 = 0x05C00001, .wake_mask = 0, .int_mask = 1, .gpe = SMI }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 460: /*N19 */ { .pad_conf0 = 0x00160301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 461: /*N20 */ { .pad_conf0 = 0x00910201, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 463: /*N22 */ { .pad_conf0 = 0x00960301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 465: /*N24 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 466: /*N25 */ { .pad_conf0 = 0xEC918201, .pad_conf1 = 0x05C00001, .wake_mask = 0, .int_mask = 1, .gpe = SCI }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 473: // FED8CC00: 01 03 A1 00 00 00 C0 05-00 03 21 00 00 00 C0 05 *..........!.....* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 474: // FED8CC10: 01 03 01 00 60 00 C0 05-00 03 00 00 20 00 C0 05 *....`....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 475: // FED8CC20: 01 03 A1 00 00 00 C0 05-01 03 A1 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 476: // FED8CC30: 00 03 01 00 00 00 C0 05-01 03 A1 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 477: // FED8CC40: 01 03 01 00 40 00 C0 05-00 03 01 00 00 00 C0 05 *....@...........* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 478: // FED8CC50: 00 03 01 00 00 00 C0 05-01 03 A1 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 493: /*N30 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 494: /*N31 */ { .pad_conf0 = 0x00210300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 495: /*N32 */ { .pad_conf0 = 0x00010301, .pad_conf1 = 0x05C00060, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 497: /*N34 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 498: /*N35 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 499: /*N36 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 500: /*N37 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 502: /*N39 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 504: /*N41 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 509: // FED8D000: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 510: // FED8D010: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 511: // FED8D020: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 512: // FED8D030: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 513: // FED8D040: 02 81 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 514: // FED8D050: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 529: /*N45 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 530: /*N46 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 531: /*N47 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 532: /*N48 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 533: /*N49 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 534: /*N50 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 535: /*N51 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 536: /*N52 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 537: /*N53 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 538: /*N54 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 539: /*N55 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 540: /*N56 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 545: // FED8D400: 00 03 01 00 00 00 C0 05-00 03 11 03 20 00 C0 05 *............ ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 546: // FED8D410: 01 03 91 00 00 00 C0 04-00 03 01 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 547: // FED8D420: 00 03 11 03 20 00 C0 05-00 03 01 00 00 00 C0 05 *.... ...........* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 548: // FED8D430: 01 03 92 00 00 00 C0 05-01 03 91 00 00 00 C0 04 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 549: // FED8D440: 01 03 11 03 20 00 C0 05-00 03 01 00 00 00 C0 05 *.... ...........* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 550: // FED8D450: 00 03 01 00 00 00 C0 05-01 03 92 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 551: // FED8D460: 00 03 01 00 00 00 C0 05-FF FF FF FF FF FF FF FF *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 555: // Native_M1, /* 62 HV_DDI2_DDC_SDA */ /* DDI2_SDA_1P8 */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 556: // Native_M1, /* 63 PANEL1_BKLTCTL */ /* PANEL1_BKLTCTL */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 557: // NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ /* DDI1_HPD */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 559: // Native_M1, /* 66 HV_DDI0_DDC_SDA */ /* DDI0_1_SDA_1P8 */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 560: // Native_M1, /* 67 HV_DDI2_DDC_SCL */ /* DDI2_SCL_1P8 */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 561: // NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ /* DDI2_HPD */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 562: // Native_M1, /* 69 PANEL1_VDDEN */ /* PANEL1_VDDEN */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 563: // Native_M1, /* 70 PANEL1_BKLTEN */ /* PANEL1_BKLTEN */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 564: // GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ /* DDI0_1_SCL_1P8 */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 567: /*N60 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 568: /*N61 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 569: /*N62 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x04C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 570: /*N63 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 571: /*N64 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 572: /*N65 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 573: /*N66 */ { .pad_conf0 = 0x00920301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 574: /*N67 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x04C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 575: /*N68 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 576: /*N69 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 577: /*N70 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 578: /*N71 */ { .pad_conf0 = 0x00920301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 588: // FED94400: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 589: // FED94410: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 590: // FED94420: 01 03 11 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 591: // FED94430: 00 03 11 00 00 00 C0 05-00 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 592: // FED94440: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 593: // FED94450: 01 03 C1 00 00 00 C0 05-01 82 91 2C 41 00 C0 05 *...........,A...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 595: // Native_M1, /* 00 PMU_SLP_S3_B */ /* PMU_SLP_S3_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 596: // Native_M1, /* 01 PMU_BATLOW_B */ /* PMU_BATLOW_B */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 597: // Native_M1, /* 02 SUS_STAT_B */ /* SUS_STAT_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 598: // Native_M1, /* 03 PMU_SLP_S0IX_B */ /* SLP_S0IX_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 599: // Native_M1, /* 04 PMU_AC_PRESENT */ /* PMU_AC_PRESENT */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 600: // Native_M1, /* 05 PMU_PLTRST_B */ /* PMU_PLTRST_B */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 601: // Native_M1, /* 06 PMU_SUSCLK */ /* PMU_SUSCLK_1P8 */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 603: // Native_M1, /* 08 PMU_PWRBTN_B */ /* PMU_PWRBTN_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 604: // Native_M1, /* 09 PMU_SLP_S4_B */ /* PMU_SLP_S4_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 605: // NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ /* PMU_WAKE_N */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 606: // GPIO_NC, /* 11 PMU_WAKE_LAN_B */ /* PMU_WAKE_LAN_N */ /* FIXME: Does this connect to onboard RTL8111? */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 608: /*E00 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 609: /*E01 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 610: /*E02 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 611: /*E03 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 612: /*E04 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 613: /*E05 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 614: /*E06 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 616: /*E08 */ { .pad_conf0 = 0X00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 617: /*E09 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 618: /*E10 */ { .pad_conf0 = 0X00C10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 619: /*E11 */ { .pad_conf0 = 0X2C918201, .pad_conf1 = 0X05C00041, .wake_mask = 1, .int_mask = 1, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 623: // FED94800: 01 03 A1 00 20 00 C0 05-02 81 11 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 624: // FED94810: 01 03 91 00 20 00 C0 05-01 03 A1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 625: // FED94820: 00 81 11 00 20 00 C0 05-01 03 A1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 626: // FED94830: 01 03 A1 00 20 00 C0 05-01 82 91 08 44 00 C0 05 *.... .......D...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 627: // FED94840: 01 03 91 00 20 00 C0 05-01 03 A1 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 628: // FED94850: 00 03 11 00 20 00 C0 05-01 03 91 00 20 00 C0 05 *.... ....... ...* line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 630: // GPIO_NC, /* 15 MF_GPIO_3 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 631: // GPIO_NC, /* 16 MF_GPIO_7 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 632: // GPIO_NC, /* 17 MF_I2C1_SCL */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 633: // GPIO_NC, /* 18 MF_GPIO_1 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 634: // GPIO_NC, /* 19 MF_GPIO_5 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 635: // GPIO_NC, /* 20 MF_GPIO_9 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 636: // GPIO_NC, /* 21 MF_GPIO_0 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 637: // GPIO_NC, /* 22 MF_GPIO_4 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 638: // GPIO_NC, /* 23 MF_GPIO_8 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 639: // GPIO_NC, /* 24 MF_GPIO_2 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 640: // GPIO_NC, /* 25 MF_GPIO_6 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 641: // GPIO_NC, /* 26 MF_I2C1_SDA */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */ line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 643: /*E15 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 644: /*E16 */ { .pad_conf0 = 0x00118102, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 646: /*E18 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 647: /*E19 */ { .pad_conf0 = 0x00118100, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 648: /*E20 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 649: /*E21 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 650: /*E22 */ { .pad_conf0 = 0x08918201, .pad_conf1 = 0x05C00044, .wake_mask = 0, .int_mask = 1, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 651: /*E23 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 652: /*E24 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/gpio… PS5, Line 653: /*E25 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… File src/mainboard/solidrun/solidpc/ramstage.c: https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 25: /* N71:HV_DDI0_DDC_SCL >> 0 2 0 00 0xFED8D458 0x00920301 0xFED8D45C 0x05C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 26: N66:HV_DDI0_DDC_SDA >> 0 2 0 00 0xFED8D430 0x00920301 0xFED8D434 0x05C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 27: N61:HV_DDI0_HPD >> 0 1 0 00 0xFED8D408 0x00110300 0xFED8D40C 0x05C00020 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 28: N64:HV_DDI1_HPD >> 0 1 0 00 0xFED8D420 0x00110301 0xFED8D424 0x05C00020 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 29: N67:HV_DDI2_DDC_SCL >> 0 1 0 00 0xFED8D438 0x00910301 0xFED8D43C 0x04C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 30: N62:HV_DDI2_DDC_SDA >> 0 1 0 00 0xFED8D410 0x00910301 0xFED8D414 0x04C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 31: N68:HV_DDI2_HPD >> 0 1 0 00 0xFED8D440 0x00110301 0xFED8D444 0x05C00020 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 32: N65:PANEL0_BKLTCTL >> 0 1 0 00 0xFED8D428 0x00010300 0xFED8D42C 0x05C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 33: N60:PANEL0_BKLTEN >> 0 1 0 00 0xFED8D400 0x00010300 0xFED8D404 0x05C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 34: N72:PANEL0_VDDEN >> 0 1 0 00 0xFED8D460 0x00010300 0xFED8D464 0x05C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 35: N63:PANEL1_BKLTCTL >> 0 1 0 00 0xFED8D418 0x00010300 0xFED8D41C 0x05C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 36: N70:PANEL1_BKLTEN >> 0 1 0 00 0xFED8D450 0x00010300 0xFED8D454 0x05C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 37: N69:PANEL1_VDDEN >> 0 1 0 00 0xFED8D448 0x00010300 0xFED8D44C 0x05C00000 line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 43: { .Name = NULL /*L"N71:HV_DDI0_DDC_SCL"*/, .Confg0 = 0x00920301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5458, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 44: { .Name = NULL /*L"N66:HV_DDI0_DDC_SDA"*/, .Confg0 = 0x00920301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5430, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 45: { .Name = NULL /*L"N61:HV_DDI0_HPD"*/, .Confg0 = 0x00110300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00020, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5408, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 46: { .Name = NULL /*L"N64:HV_DDI1_HPD"*/, .Confg0 = 0x00110301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00020, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5420, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 47: { .Name = NULL /*L"N67:HV_DDI2_DDC_SCL"*/, .Confg0 = 0x00910301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x04C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5438, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 48: { .Name = NULL /*L"N62:HV_DDI2_DDC_SDA"*/, .Confg0 = 0x00910301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x04C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5410, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 49: { .Name = NULL /*L"N68:HV_DDI2_HPD"*/, .Confg0 = 0x00110301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00020, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5440, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 50: { .Name = NULL /*L"N65:PANEL0_BKLTCTL"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5428, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 51: { .Name = NULL /*L"N60:PANEL0_BKLTEN"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5400, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 52: { .Name = NULL /*L"N72:PANEL0_VDDEN"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5460, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 53: { .Name = NULL /*L"N63:PANEL1_BKLTCTL"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5418, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 54: { .Name = NULL /*L"N70:PANEL1_BKLTEN"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5450, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 55: { .Name = NULL /*L"N69:PANEL1_VDDEN"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5448, .Misc = 0 }, line over 80 characters https://review.coreboot.org/#/c/23027/5/src/mainboard/solidrun/solidpc/rams… PS5, Line 56: { .Name = NULL /*L""*/, .Confg0 = 0xFFFFFFFF, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0xFFFFFFFF, .Confg1Changes = 0xFFFFFFFF, .Community = 0xFFFFFFFF, .MmioAddr = 0xFFFFFFFF, .Misc = 0xFFFFFFFF }, line over 80 characters -- To view, visit https://review.coreboot.org/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 19 Sep 2018 17:43:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/octopus: Create ampton variant
by build bot (Jenkins) (Code Review) 19 Sep '18

19 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28663 ) Change subject: mb/google/octopus: Create ampton variant ...................................................................... Patch Set 6: (117 comments) https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/ampton/gpio.c: https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 35: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 36: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 37: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 38: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 39: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 40: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 41: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 42: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 43: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 44: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 45: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 46: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 47: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 49: PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 51: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA6_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 52: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA7_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 53: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_CLK_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 54: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA0_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 55: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA1_VNN 0*/ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 56: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA2_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 57: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA3_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 58: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA4_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 59: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA5_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 60: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA6_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 61: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA7_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 62: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_CLK_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 63: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 64: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 65: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 70: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 71: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 72: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 79: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 80: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 81: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 82: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 85: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 86: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 89: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 90: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 92: PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 93: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 94: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 103: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 104: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 106: PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 118: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 119: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* H1_SLAVE_SPI_CS_L_R */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 120: PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 131: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 132: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 133: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 134: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 137: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 140: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 141: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 142: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 143: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 144: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 147: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 148: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 149: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 151: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 154: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 155: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 158: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 159: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 162: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 163: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 166: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 167: PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 169: PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 176: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 177: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 178: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 179: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 188: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 189: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTEN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 190: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTCTL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 193: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 194: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 195: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 198: PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 199: PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 202: PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 203: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 204: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 206: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 207: PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 211: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 226: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 227: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 229: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 230: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 231: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 232: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 233: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 234: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 237: PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_A1 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 238: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 239: PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_1 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 241: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 246: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* EN_PP3300_WLAN */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 265: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 267: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 268: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 269: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 270: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 271: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 272: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 273: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 274: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 275: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 276: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 277: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 278: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ line over 80 characters https://review.coreboot.org/#/c/28663/6/src/mainboard/google/octopus/varian… PS6, Line 279: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters -- To view, visit https://review.coreboot.org/28663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3 Gerrit-Change-Number: 28663 Gerrit-PatchSet: 6 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Sep 2018 17:27:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Update PowerLimit1 maximum value
by Sumeet R Pawnikar (Code Review) 19 Sep '18

19 Sep '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/28686 Change subject: mb/google/poppy/variants/nocturne: Update PowerLimit1 maximum value ...................................................................... mb/google/poppy/variants/nocturne: Update PowerLimit1 maximum value Increase power limit1 maximum value from 5W to 7W. This value as per recent measurement on closed system which shows better performance results. BUG=None TEST=Build and tested on Nocturne system. Performance tests show better results. Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28686/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl index c8bafb4..931cca1 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl @@ -73,7 +73,7 @@ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ - 5000, /* PowerLimitMaximum */ + 7000, /* PowerLimitMaximum */ 5000, /* TimeWindowMinimum */ 5000, /* TimeWindowMaximum */ 200 /* StepSize */ -- To view, visit https://review.coreboot.org/28686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918 Gerrit-Change-Number: 28686 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Pha...
by build bot (Jenkins) (Code Review) 19 Sep '18

19 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28669 ) Change subject: mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for Phaseer ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/28669/8/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/phaser/gpio.c: https://review.coreboot.org/#/c/28669/8/src/mainboard/google/octopus/varian… PS8, Line 64: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), line over 80 characters https://review.coreboot.org/#/c/28669/8/src/mainboard/google/octopus/varian… PS8, Line 107: }else space required after that close brace '}' -- To view, visit https://review.coreboot.org/28669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Gerrit-Change-Number: 28669 Gerrit-PatchSet: 8 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 19 Sep 2018 16:25:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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