coreboot-gerrit September 2018

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Change in coreboot[master]: mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for meep
by Wisley Chen (Code Review) 18 Sep '18

18 Sep '18

Wisley Chen has uploaded this change for review. ( https://review.coreboot.org/28658 Change subject: mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for meep ...................................................................... mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for meep Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT. BUG=b:115965629 TEST=verified it in meep proto board which rework ram id. Singed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363 --- M src/mainboard/google/octopus/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28658/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 7ecb486..91d55ac 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -112,6 +112,7 @@ config DRAM_PART_NUM_IN_CBI bool default y if BOARD_GOOGLE_PHASER + default y if BOARD_GOOGLE_MEEP config DRAM_PART_NUM_ALWAYS_IN_CBI bool @@ -125,7 +126,7 @@ default 2 if BOARD_GOOGLE_PHASER default 9 if BOARD_GOOGLE_FLEEX default 9 if BOARD_GOOGLE_BOBBA - default 9 if BOARD_GOOGLE_MEEP + default 1 if BOARD_GOOGLE_MEEP default 255 if BOARD_GOOGLE_OCTOPUS endif # BOARD_GOOGLE_OCTOPUS -- To view, visit https://review.coreboot.org/28658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363 Gerrit-Change-Number: 28658 Gerrit-PatchSet: 1 Gerrit-Owner: Wisley Chen <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: sb/intel/bd82x6x: Don't use device_t
by build bot (Jenkins) (Code Review) 18 Sep '18

18 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28657 ) Change subject: sb/intel/bd82x6x: Don't use device_t ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/28657/2/src/southbridge/intel/bd82x6x/me_8.… File src/southbridge/intel/bd82x6x/me_8.x.c: https://review.coreboot.org/#/c/28657/2/src/southbridge/intel/bd82x6x/me_8.… PS2, Line 742: static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28657/2/src/southbridge/intel/bd82x6x/me_8.… PS2, Line 742: static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) Prefer 'unsigned int' to bare use of 'unsigned' -- To view, visit https://review.coreboot.org/28657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Gerrit-Change-Number: 28657 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Sep 2018 11:38:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sb/intel/bd82x6x: Don't use device_t
by Elyes HAOUAS (Code Review) 18 Sep '18

18 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28657 to look at the new patch set (#2). Change subject: sb/intel/bd82x6x: Don't use device_t ...................................................................... sb/intel/bd82x6x: Don't use device_t Use of device_t is deprecated. Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.c 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28657/2 -- To view, visit https://review.coreboot.org/28657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Gerrit-Change-Number: 28657 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x/pch.c: Don't use device_t
by Elyes HAOUAS (Code Review) 18 Sep '18

18 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28657 Change subject: sb/intel/bd82x6x/pch.c: Don't use device_t ...................................................................... sb/intel/bd82x6x/pch.c: Don't use device_t Use of device_t is deprecated. Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/pch.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28657/1 diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 79cf6bf..bec257b 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -208,9 +208,9 @@ } /* Check if any port in set X to X+3 is enabled */ -static int pch_pcie_check_set_enabled(device_t dev) +static int pch_pcie_check_set_enabled(pci_devfn_t dev) { - device_t port; + pci_devfn_t port; int port_func; int dev_func = PCI_FUNC(dev->path.pci.devfn); @@ -258,7 +258,7 @@ static void pch_pcie_devicetree_update( struct southbridge_intel_bd82x6x_config *config) { - device_t dev; + pci_devfn_t dev; /* * hotplug map should also be updated along with their @@ -312,7 +312,7 @@ } /* Special handling for PCIe Root Port devices */ -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(pci_devfn_t dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; u32 reg32; @@ -422,7 +422,7 @@ } } -void pch_enable(device_t dev) +void pch_enable(pci_devfn_t dev) { u32 reg32; -- To view, visit https://review.coreboot.org/28657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Gerrit-Change-Number: 28657 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: nb/via/vx900: Get rid of device_t
by Elyes HAOUAS (Code Review) 18 Sep '18

18 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28655 to look at the new patch set (#2). Change subject: nb/via/vx900: Get rid of device_t ...................................................................... nb/via/vx900: Get rid of device_t Use of device_t is deprecated. Change-Id: I70dcefd5bc9864931f66bece1f044f806f5d7ae0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/via/vx900/vx900.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28655/2 -- To view, visit https://review.coreboot.org/28655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I70dcefd5bc9864931f66bece1f044f806f5d7ae0 Gerrit-Change-Number: 28655 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/via/vx900: Get rid of device_t
by Elyes HAOUAS (Code Review) 18 Sep '18

18 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28655 Change subject: nb/via/vx900: Get rid of device_t ...................................................................... nb/via/vx900: Get rid of device_t Use of device_t is deprecated. Change-Id: I70dcefd5bc9864931f66bece1f044f806f5d7ae0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/via/vx900/pci_util.c M src/northbridge/via/vx900/vx900.h 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28655/1 diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index 1674e85..76d58bb 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -16,7 +16,7 @@ #include "vx900.h" -void dump_pci_device(device_t dev) +void dump_pci_device(unsigned int dev) { int i; for (i = 0; i <= 0xff; i++) { @@ -35,7 +35,7 @@ } } -void pci_mod_config8(device_t dev, unsigned int where, +void pci_mod_config8(unsigned int dev, unsigned int where, uint8_t clr_mask, uint8_t set_mask) { uint8_t reg8 = pci_read_config8(dev, where); @@ -44,7 +44,7 @@ pci_write_config8(dev, where, reg8); } -void pci_mod_config16(device_t dev, unsigned int where, +void pci_mod_config16(unsigned int dev, unsigned int where, uint16_t clr_mask, uint16_t set_mask) { uint16_t reg16 = pci_read_config16(dev, where); @@ -53,7 +53,7 @@ pci_write_config16(dev, where, reg16); } -void pci_mod_config32(device_t dev, unsigned int where, +void pci_mod_config32(unsigned int dev, unsigned int where, uint32_t clr_mask, uint32_t set_mask) { uint32_t reg32 = pci_read_config32(dev, where); diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index cb7bca9..a2a360a 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -50,12 +50,12 @@ void pci_mod_config32(pci_devfn_t dev, unsigned int where, uint32_t clr_mask, uint32_t set_mask); #else -void dump_pci_device(device_t dev); -void pci_mod_config8(device_t dev, unsigned int where, +void dump_pci_device(struct device *dev); +void pci_mod_config8(struct device *dev, unsigned int where, uint8_t clr_mask, uint8_t set_mask); -void pci_mod_config16(device_t dev, unsigned int where, +void pci_mod_config16(struct device *dev, unsigned int where, uint16_t clr_mask, uint16_t set_mask); -void pci_mod_config32(device_t dev, unsigned int where, +void pci_mod_config32(struct device *dev, unsigned int where, uint32_t clr_mask, uint32_t set_mask); #endif -- To view, visit https://review.coreboot.org/28655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I70dcefd5bc9864931f66bece1f044f806f5d7ae0 Gerrit-Change-Number: 28655 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/intel/cannonlake: Add FSP CAR Init support for CFL
by PraveenX Hodagatta Pranesh (Code Review) 18 Sep '18

18 Sep '18

PraveenX Hodagatta Pranesh has removed Teo Boon Tiong from this change. ( https://review.coreboot.org/28581 ) Change subject: soc/intel/cannonlake: Add FSP CAR Init support for CFL ...................................................................... Removed reviewer Teo Boon Tiong. -- To view, visit https://review.coreboot.org/28581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteReviewer Gerrit-Change-Id: Ic17bc827e57df6ba0b891f906c7adac1bb5d4d73 Gerrit-Change-Number: 28581 Gerrit-PatchSet: 3 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/i82801gx/lpc.c: Don't hide pointer behind typedef
by Patrick Rudolph (Code Review) 18 Sep '18

18 Sep '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28642 ) Change subject: sb/intel/i82801gx/lpc.c: Don't hide pointer behind typedef ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I564319506870f75eab58cce535d4e3535a64a993 Gerrit-Change-Number: 28642 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Sep 2018 08:41:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/poppy/variants/rammus: Enable touchscreen function
by YanRu Chen (Code Review) 18 Sep '18

18 Sep '18

Hello Zhuohao Lee, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28598 to look at the new patch set (#5). Change subject: mainboard/google/poppy/variants/rammus: Enable touchscreen function ...................................................................... mainboard/google/poppy/variants/rammus: Enable touchscreen function On rammus, set GPIO GPP_C22 to 1 for touchscreen power on. And add touchscreen device "PNP0C50" to I2C0. BUG=b:115944726 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen workable. Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced Signed-off-by: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/rammus/gpio.c 2 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/28598/5 -- To view, visit https://review.coreboot.org/28598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced Gerrit-Change-Number: 28598 Gerrit-PatchSet: 5 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry Chou <jerry_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Statham Chu <statham_chu(a)pegatron.corp-partner.google.com>

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Change in coreboot[master]: mainboard/google/poppy/variants/rammus: Enable EN_PP3300_DX_TOUCHSCREEN
by YanRu Chen (Code Review) 18 Sep '18

18 Sep '18

Hello Zhuohao Lee, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28598 to look at the new patch set (#3). Change subject: mainboard/google/poppy/variants/rammus: Enable EN_PP3300_DX_TOUCHSCREEN ...................................................................... mainboard/google/poppy/variants/rammus: Enable EN_PP3300_DX_TOUCHSCREEN On rammus, set GPIO GPP_C22 to 1 for touchscreen power on. And add touchscreen device "PNP0C50" to I2C0. BUG=b:115944726 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen workable. Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced Signed-off-by: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/rammus/gpio.c 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/28598/3 -- To view, visit https://review.coreboot.org/28598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced Gerrit-Change-Number: 28598 Gerrit-PatchSet: 3 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-CC: Jerry Chou <jerry_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Statham Chu <statham_chu(a)pegatron.corp-partner.google.com>

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coreboot-gerrit September 2018