coreboot-gerrit September 2018

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Change in coreboot[master]: util/inteltool: Add Sunrise Point LP
by Daniel Maslowski (Code Review) 15 Sep '18

15 Sep '18

Hello Patrick Rudolph, Johanna Schander, Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28618 to look at the new patch set (#5). Change subject: util/inteltool: Add Sunrise Point LP ...................................................................... util/inteltool: Add Sunrise Point LP Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28618/5 -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 5 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: Add support for Sunsetrise Point LP to inteltool
by Felix Singer (Code Review) 15 Sep '18

15 Sep '18

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/28623 Change subject: Add support for Sunsetrise Point LP to inteltool ...................................................................... Add support for Sunsetrise Point LP to inteltool Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/ahci.c M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c M util/inteltool/powermgt.c M util/inteltool/rootcmplx.c M util/inteltool/spi.c 10 files changed, 103 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/28623/1 diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 6d539f4..22a5b01 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -67,7 +67,8 @@ } printf("\n============= AHCI Registers ==============\n\n"); - if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA) + if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA || + ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA) mmio_size = 0x800; else mmio_size = 0x400; @@ -96,7 +97,8 @@ print_port(mmio, i); } - if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA) { + if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA || + ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA) { puts("\nOther registers:"); for (i = 0x500; i < mmio_size; i += 4) { if (MMIO(i)) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index c38051c..c946b2a 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1027,6 +1027,7 @@ break; case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 2bb4edc..5dd3745 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -202,6 +202,33 @@ "GPP_E12", "USB_OC3#", "n/a", "n/a", }; +static const char *const sunrise_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATA_LED#", "n/a", "n/a", + "GPP_E9", "USB_OC0#", "n/a", "n/a", + "GPP_E10", "USB_OC1#", "n/a", "n/a", + "GPP_E11", "USB_OC2#", "n/a", "n/a", + "GPP_E12", "USB_OC3#", "n/a", "n/a", + "GPP_E13", "n/a", "n/a", "n/a", + "GPP_E14", "n/a", "n/a", "n/a", + "GPP_E15", "n/a", "n/a", "n/a", + "GPP_E16", "n/a", "n/a", "n/a", + "GPP_E17", "n/a", "n/a", "n/a", + "GPP_E18", "n/a", "n/a", "n/a", + "GPP_E19", "n/a", "n/a", "n/a", + "GPP_E20", "n/a", "n/a", "n/a", + "GPP_E21", "n/a", "n/a", "n/a", + "GPP_E22", "n/a", "n/a", "n/a", + "GPP_E23", "n/a", "n/a", "n/a", +}; + static const struct gpio_group sunrise_group_e = { .display = "------- GPIO Group GPP_E -------", .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, @@ -209,6 +236,13 @@ .pad_names = sunrise_group_e_names, }; +static const struct gpio_group sunrise_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_e_names, +}; + static const char *const sunrise_group_f_names[] = { "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", @@ -270,6 +304,17 @@ "GPP_G23", "n/a", "n/a", "n/a", }; +static const char *const sunrise_lp_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "n/a", "n/a", + "GPP_G1", "FAN_TACH_1", "n/a", "n/a", + "GPP_G2", "FAN_TACH_2", "n/a", "n/a", + "GPP_G3", "FAN_TACH_3", "n/a", "n/a", + "GPP_G4", "FAN_TACH_4", "n/a", "n/a", + "GPP_G5", "FAN_TACH_5", "n/a", "n/a", + "GPP_G6", "FAN_TACH_6", "n/a", "n/a", + "GPP_G7", "FAN_TACH_7", "n/a", "n/a", +}; + static const struct gpio_group sunrise_group_g = { .display = "------- GPIO Group GPP_G -------", .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, @@ -277,6 +322,13 @@ .pad_names = sunrise_group_g_names, }; +static const struct gpio_group sunrise_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_g_names, +}; + static const char *const sunrise_group_h_names[] = { "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", @@ -316,6 +368,10 @@ &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, }; +static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { + &sunrise_group_c, &sunrise_group_d, &sunrise_lp_group_e, +}; + static const struct gpio_community sunrise_community_cdefgh = { .name = "------- GPIO Community 1 -------", .pcr_port_id = 0xae, @@ -323,6 +379,13 @@ .groups = sunrise_community_cdefgh_groups, }; +static const struct gpio_community sunrise_lp_community_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), + .groups = sunrise_lp_community_cde_groups, +}; + static const char *const sunrise_group_gpd_names[] = { "GPD0", "BATLOW#", "n/a", "n/a", "GPD1", "ACPRESENT", "n/a", "n/a", @@ -381,6 +444,10 @@ &sunrise_group_i, }; +static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { + &sunrise_group_f, &sunrise_lp_group_g, +}; + static const struct gpio_community sunrise_community_i = { .name = "------- GPIO Community 3 -------", .pcr_port_id = 0xac, @@ -388,11 +455,24 @@ .groups = sunrise_community_i_groups, }; +static const struct gpio_community sunrise_lp_community_fg = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), + .groups = sunrise_lp_community_fg_groups, +}; + static const struct gpio_community *const sunrise_communities[] = { &sunrise_community_ab, &sunrise_community_cdefgh, &sunrise_community_gpd, &sunrise_community_i, }; +static const struct gpio_community *const sunrise_lp_communities[] = { + &sunrise_community_ab, &sunrise_lp_community_cde, + &sunrise_community_gpd, &sunrise_lp_community_fg, +}; + + static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { @@ -460,6 +540,11 @@ communities = sunrise_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP: + community_count = ARRAY_SIZE(sunrise_lp_communities); + communities = sunrise_lp_communities; + pcr_init(sb); + break; default: return; } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index d0b4279..17cc970 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -218,6 +218,8 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, "Sunrise Point Desktop Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP, + "Sunrise Point Low Power" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 5de73aa..4aed7ad 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -144,6 +144,8 @@ #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP 0x9d4e #define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_Z170 0xa145 @@ -246,6 +248,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_M 0x5914 /* Kabylake (Mobile) */ /* Intel GPUs */ #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982 diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 233d6a9..ddf643e 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -222,6 +222,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_M: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index cf4b6b6..255a9a2 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -267,6 +267,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_M: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -389,6 +390,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_M: dmi_registers = skylake_dmi_registers; size = ARRAY_SIZE(skylake_dmi_registers); dmibar_phys = pci_read_long(nb, 0x68); @@ -495,6 +497,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_M: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 45cbb33..b2033e4 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -745,6 +745,7 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; size = ARRAY_SIZE(pch_pm_registers); diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 76cb287..4e3849c 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -112,6 +112,7 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 18600b6..1336357 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -175,6 +175,7 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP: bios_cntl = pci_read_byte(sb, 0xdc); bios_cntl_register = pch_bios_cntl_registers; size = ARRAY_SIZE(pch_bios_cntl_registers); @@ -303,6 +304,7 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP: spibaroffset = ICH9_SPIBAR; rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; size = ARRAY_SIZE(spi_bar_registers); -- To view, visit https://review.coreboot.org/28623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Gerrit-Change-Number: 28623 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>

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Change in coreboot[master]: util/autoport: Add Sunrise Point LP
by Daniel Maslowski (Code Review) 15 Sep '18

15 Sep '18

Hello Patrick Rudolph, Johanna Schander, Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28618 to look at the new patch set (#4). Change subject: util/autoport: Add Sunrise Point LP ...................................................................... util/autoport: Add Sunrise Point LP Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28618/4 -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 4 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: util/autoport: Add Sunrise Point LP
by Daniel Maslowski (Code Review) 15 Sep '18

15 Sep '18

Hello Patrick Rudolph, Johanna Schander, Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28618 to look at the new patch set (#3). Change subject: util/autoport: Add Sunrise Point LP ...................................................................... util/autoport: Add Sunrise Point LP Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Signed-off-by: YOLO --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28618/3 -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: util/autoport: AddSunrise Point LP
by Daniel Maslowski (Code Review) 15 Sep '18

15 Sep '18

Hello Patrick Rudolph, Johanna Schander, Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28618 to look at the new patch set (#2). Change subject: util/autoport: AddSunrise Point LP ...................................................................... util/autoport: AddSunrise Point LP Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Signed-off-by: YOLO --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28618/2 -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: util/autoport: Add ICH6-M
by Arthur Heymans (Code Review) 15 Sep '18

15 Sep '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/28618 ) Change subject: util/autoport: Add ICH6-M ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28618/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28618/1//COMMIT_MSG@7 PS1, Line 7: util/autoport: Add ICH6-M util/inteltool -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Sep 2018 14:53:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sifive/hifive-unleashed: enable CBMEM support
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Philipp Hug has uploaded a new patch set (#2). ( https://review.coreboot.org/28622 ) Change subject: sifive/hifive-unleashed: enable CBMEM support ...................................................................... sifive/hifive-unleashed: enable CBMEM support Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/28622/2 -- To view, visit https://review.coreboot.org/28622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc Gerrit-Change-Number: 28622 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: sifive/hifive-unleashed: enable CBMEM support
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28622 Change subject: sifive/hifive-unleashed: enable CBMEM support ...................................................................... sifive/hifive-unleashed: enable CBMEM support Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/sifive/hifive-unleashed/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/28622/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index df4cf89..3767491 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -42,5 +42,7 @@ sdram_init(); + cbmem_initialize_empty(); + run_ramstage(); } -- To view, visit https://review.coreboot.org/28622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc Gerrit-Change-Number: 28622 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: soc/sifive: move ram_resource to mainboard
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28621 Change subject: soc/sifive: move ram_resource to mainboard ...................................................................... soc/sifive: move ram_resource to mainboard ram_resource is board specific and should be moved there. Change-Id: I50bd9aaaae39422e565d8bf205a6365c59299df0 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/sifive/hifive-unleashed/mainboard.c D src/soc/sifive/fu540/soc.c 2 files changed, 5 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/28621/1 diff --git a/src/mainboard/sifive/hifive-unleashed/mainboard.c b/src/mainboard/sifive/hifive-unleashed/mainboard.c index e7f7a40..baf44d4 100644 --- a/src/mainboard/sifive/hifive-unleashed/mainboard.c +++ b/src/mainboard/sifive/hifive-unleashed/mainboard.c @@ -13,12 +13,14 @@ * GNU General Public License for more details. */ -#include <device/device.h> -#include <bootblock_common.h> -#include <timestamp.h> +#include <arch/io.h> +#include <console/console.h> +#include <soc/sdram.h> +#include <symbols.h> static void mainboard_enable(struct device *dev) { + ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*KiB); } struct chip_operations mainboard_ops = { diff --git a/src/soc/sifive/fu540/soc.c b/src/soc/sifive/fu540/soc.c deleted file mode 100644 index 9405755..0000000 --- a/src/soc/sifive/fu540/soc.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Philipp Hug <philipp(a)hug.cx> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void soc_enable(struct device *dev) -{ - ram_resource(dev, 0, (uintptr_t)_dram/KiB, - sdram_size_mb()*KiB); -} -- To view, visit https://review.coreboot.org/28621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I50bd9aaaae39422e565d8bf205a6365c59299df0 Gerrit-Change-Number: 28621 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: util/autoport: Add ICH6-M
by Daniel Maslowski (Code Review) 15 Sep '18

15 Sep '18

Daniel Maslowski has posted comments on this change. ( https://review.coreboot.org/28618 ) Change subject: util/autoport: Add ICH6-M ...................................................................... Patch Set 1: > Patch Set 1: Code-Review-1 > > (1 comment) > > Signed-off-by: Must contain real name and email Which should I choose actually? I just put something random to bypass the commit hook. -- To view, visit https://review.coreboot.org/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 13:25:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit September 2018