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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by build bot (Jenkins) (Code Review) 15 Sep '18

15 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28606 ) Change subject: WIP: Port libpayload to riscv ...................................................................... Patch Set 2: (38 comments) https://review.coreboot.org/#/c/28606/2/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/28606/2/payloads/external/LinuxBoot/Makefil… PS2, Line 78: echo "BEFOR DEF" 'BEFOR' may be misspelled - perhaps 'BEFORE'? https://review.coreboot.org/#/c/28606/2/payloads/libpayload/arch/riscv/core… File payloads/libpayload/arch/riscv/coreboot.c: https://review.coreboot.org/#/c/28606/2/payloads/libpayload/arch/riscv/core… PS2, Line 42: switch(rec->tag) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/asm.h: https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 24: name: labels should not be indented https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 27: .size name, .-name space required before that '-' (ctx:VxV) https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/barrier.h: https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 57: #define mb() memory barrier without comment https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 58: #define rmb() memory barrier without comment https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 59: #define wmb() memory barrier without comment https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/cache.h: https://review.coreboot.org/#/c/28606/2/payloads/libpayload/include/riscv/a… PS2, Line 81: } void function return statements are not generally useful https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c File payloads/linuxcheck/riscv.c: https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@25 PS2, Line 25: uint32_t txdata; /* Transmit data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@25 PS2, Line 25: uint32_t txdata; /* Transmit data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@26 PS2, Line 26: uint32_t rxdata; /* Receive data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@26 PS2, Line 26: uint32_t rxdata; /* Receive data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@27 PS2, Line 27: uint32_t txctrl; /* Transmit control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@27 PS2, Line 27: uint32_t txctrl; /* Transmit control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@28 PS2, Line 28: uint32_t rxctrl; /* Receive control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@28 PS2, Line 28: uint32_t rxctrl; /* Receive control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@29 PS2, Line 29: uint32_t ie; /* UART interrupt enable */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@29 PS2, Line 29: uint32_t ie; /* UART interrupt enable */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@30 PS2, Line 30: uint32_t ip; /* UART interrupt pending */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@30 PS2, Line 30: uint32_t ip; /* UART interrupt pending */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@31 PS2, Line 31: uint32_t div; /* Baud rate divisor */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@31 PS2, Line 31: uint32_t div; /* Baud rate divisor */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@36 PS2, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@36 PS2, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@41 PS2, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@41 PS2, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@43 PS2, Line 43: while (!uart_can_tx(regs)) code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@43 PS2, Line 43: while (!uart_can_tx(regs)) please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@44 PS2, Line 44: ; /* TODO: implement a timeout */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@44 PS2, Line 44: ; /* TODO: implement a timeout */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@46 PS2, Line 46: write32(&regs->txdata, data); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/2/payloads/linuxcheck/riscv.c@46 PS2, Line 46: write32(&regs->txdata, data); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: comment Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 07:33:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28606 to look at the new patch set (#2). Change subject: WIP: Port libpayload to riscv ...................................................................... WIP: Port libpayload to riscv Work-in-progress port of libpayload to RISC-V Do not merge yet Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/barrier.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h M payloads/linuxcheck/Makefile A payloads/linuxcheck/riscv.c 22 files changed, 861 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28606/2 -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: newpatchset Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/buddy: Add board as variant of google/auron
by Matt DeVillier (Code Review) 15 Sep '18

15 Sep '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/28613 Change subject: google/buddy: Add board as variant of google/auron ...................................................................... google/buddy: Add board as variant of google/auron Add google/buddy (Acer Chromeboase 24) as a variant of google/auron, with the following changes: - add buddy-specific variant code - add handling to auron for buddy's lan init, which no other variants have - add handling to auron's mainboard ACPI due buddy having different PCIe port assigments than all other variants Ported from Chromium branch firmware-buddy-6301.202.B, commit ebb82ce [Buddy: Lock management engine + SPI descriptor] Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/Kconfig.name M src/mainboard/google/auron/Makefile.inc M src/mainboard/google/auron/acpi/mainboard.asl M src/mainboard/google/auron/mainboard.c M src/mainboard/google/auron/variant.h A src/mainboard/google/auron/variants/buddy/devicetree.cb A src/mainboard/google/auron/variants/buddy/include/variant/acpi/ec.asl A src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl A src/mainboard/google/auron/variants/buddy/include/variant/acpi/usb.asl A src/mainboard/google/auron/variants/buddy/include/variant/gpio.h A src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h A src/mainboard/google/auron/variants/buddy/include/variant/onboard.h A src/mainboard/google/auron/variants/buddy/include/variant/spd.h A src/mainboard/google/auron/variants/buddy/include/variant/thermal.h A src/mainboard/google/auron/variants/buddy/pei_data.c A src/mainboard/google/auron/variants/buddy/spd/Makefile.inc A src/mainboard/google/auron/variants/buddy/spd/spd.c A src/mainboard/google/auron/variants/buddy/variant.c 19 files changed, 932 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/28613/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index ea0e01f..095f181 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -12,7 +12,7 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_INT15 - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_BUDDY if BOARD_GOOGLE_BASEBOARD_AURON @@ -32,6 +32,7 @@ string default "auron_paine" if BOARD_GOOGLE_AURON_PAINE default "auron_yuna" if BOARD_GOOGLE_AURON_YUNA + default "buddy" if BOARD_GOOGLE_BUDDY default "gandof" if BOARD_GOOGLE_GANDOF default "lulu" if BOARD_GOOGLE_LULU default "samus" if BOARD_GOOGLE_SAMUS @@ -40,6 +41,7 @@ string default "Auron_Paine" if BOARD_GOOGLE_AURON_PAINE default "Auron_Yuna" if BOARD_GOOGLE_AURON_YUNA + default "Buddy" if BOARD_GOOGLE_BUDDY default "Gandof" if BOARD_GOOGLE_GANDOF default "Lulu" if BOARD_GOOGLE_LULU default "Samus" if BOARD_GOOGLE_SAMUS @@ -49,6 +51,7 @@ depends on CHROMEOS default "PAINE TEST A-A 8843" if BOARD_GOOGLE_AURON_PAINE default "YUNA TEST A-A 3347" if BOARD_GOOGLE_AURON_YUNA + default "BUDDY TEST A-A 6186" if BOARD_GOOGLE_BUDDY default "GANDOF TEST A-A 7705" if BOARD_GOOGLE_GANDOF default "LULU TEST A-A 7705" if BOARD_GOOGLE_LULU default "SAMUS TEST 8028" if BOARD_GOOGLE_SAMUS @@ -57,6 +60,7 @@ string default "variants/auron_paine/devicetree.cb" if BOARD_GOOGLE_AURON_PAINE default "variants/auron_yuna/devicetree.cb" if BOARD_GOOGLE_AURON_YUNA + default "variants/buddy/devicetree.cb" if BOARD_GOOGLE_BUDDY default "variants/gandof/devicetree.cb" if BOARD_GOOGLE_GANDOF default "variants/lulu/devicetree.cb" if BOARD_GOOGLE_LULU default "variants/samus/devicetree.cb" if BOARD_GOOGLE_SAMUS diff --git a/src/mainboard/google/auron/Kconfig.name b/src/mainboard/google/auron/Kconfig.name index 324c3ee..19fd4d7 100644 --- a/src/mainboard/google/auron/Kconfig.name +++ b/src/mainboard/google/auron/Kconfig.name @@ -8,6 +8,10 @@ bool "-> Auron_Yuna (Acer Chromebook 15 (C910/CB5-531))" select BOARD_GOOGLE_BASEBOARD_AURON +config BOARD_GOOGLE_BUDDY + bool "-> Buddy (Acer Chromebase 24)" + select BOARD_GOOGLE_BASEBOARD_AURON + config BOARD_GOOGLE_GANDOF bool "-> Gandof (Toshiba Chromebook 2 (2015))" select BOARD_GOOGLE_BASEBOARD_AURON diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index d54a1c0..170e168 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -23,7 +23,9 @@ romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c +ifneq ($(CONFIG_BOARD_GOOGLE_BUDDY),y) romstage-y += variants/$(VARIANT_DIR)/variant.c +endif ramstage-y += variants/$(VARIANT_DIR)/variant.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index 907590d..204c1c4 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -16,6 +16,7 @@ #include <variant/onboard.h> +#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_BUDDY) Scope (\_SB.PCI0.RP01) { Device (WLAN) @@ -34,6 +35,7 @@ } } } +#endif #include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 9eece73..2cbd0e7 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -20,9 +20,14 @@ #include "variant.h" +__weak void lan_init(void) +{ +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); + lan_init(); } static int mainboard_smbios_data(struct device *dev, int *handle, diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index 41c157f..b11ea1e 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -20,5 +20,6 @@ int variant_smbios_data(device_t dev, int *handle, unsigned long *current); void variant_romstage_entry(struct romstage_params *rp); +void lan_init(void); #endif diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb new file mode 100644 index 0000000..e662794 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/devicetree.cb @@ -0,0 +1,111 @@ +chip soc/intel/broadwell + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Disable DisplayPort C Hotplug + register "gpu_dp_c_hotplug" = "0x00" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "70" # 7ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + register "sio_acpi_mode" = "1" + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + register "s0ix_enable" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 13.0 on end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end +end diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/ec.asl diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..788fbdc --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C0) +{ + Device (RTEK) + { + Name (_HID, "10EC5650") + Name (_CID, "10EC5650") + Name (_DDN, "RTEK Codec Controller ") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x1A, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0", // ResourceSource + ) + + Interrupt (ResourceConsumer, Edge, ActiveLow){ 37 } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.PCI0.I2C1) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen") + Name (_UID, 6) + Name (ISTP, 0) /* Touchscreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x10, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +/* + * LAN connected to Root Port 3, becomes Root Port 1 after coalesce + */ +Scope (\_SB.PCI0.RP01) +{ + Device (ETH0) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { BUDDY_NIC_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BUDDY_NIC_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + } +} + +/* + * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce + */ +Scope (\_SB.PCI0.RP02) +{ + Device (WLAN) + { + Name (_ADR, 0x00000000) + + /* GPIO10 is WLAN_WAKE_L_Q */ + Name (GPIO, BOARD_WLAN_WAKE_GPIO) + + Name (_PRW, Package() { GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) + } + } + } +} diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h b/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h new file mode 100644 index 0000000..efa720f --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BUDDY_GPIO_H +#define BUDDY_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_OUT_HIGH, /* 13: BT_DISABLE_L */ + PCH_GPIO_INPUT, /* 14: EC_IN_RW */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_UNUSED, /* 43: UNUSED */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ + PCH_GPIO_UNUSED, /* 46: UNUSED */ + PCH_GPIO_UNUSED, /* 47: UNUSED */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_UNUSED, /* 49: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_PIRQ_INVERT, /* 53: CODEC_INT */ + PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB_CHARGE_EN */ + PCH_GPIO_UNUSED, /* 57: UNUSED */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_NATIVE, /* 61: SUS_STAT# */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h new file mode 100644 index 0000000..7fd9853 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000d, // Number of jacks (NID entries) + + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ + 0x00172083, + 0x00172102, + 0x001722ec, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC - Disabled */ + 0x01271cf0, // + 0x01271d11, // + 0x01271e11, // + 0x01271f41, // + + /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ + 0x01471c10, // group 1, cap 0 + 0x01471d01, // no connector, no jack detect + 0x01471e17, // speaker out, analog + 0x01471f90, // fixed function, internal, Location N/A + + /* Pin Complex (NID 0x17) MONO Out - Disabled */ + 0x01771cf0, // + 0x01771d11, // + 0x01771e11, // + 0x01771f41, // + + /* Pin Complex (NID 0x18) Disabled */ + 0x01871cf0, // + 0x01871d11, // + 0x01871e11, // + 0x01871f41, // + + /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ + 0x01971c20, // group2, cap 0 + 0x01971d10, // black, jack detect + 0x01971ea1, // Mic in, 3.5mm Jack + 0x01971f03, // connector, External left panel + + /* Pin Complex (NID 0x1A) LINE1 - Internal Mic */ + 0x01a71c11, // group 1, cap 1 + 0x01a71d01, // no connector, no jack detect + 0x01a71ea7, // mic in, analog connection + 0x01a71f90, // Fixed function, internal, Location N/A + + /* Pin Complex (NID 0x1B) LINE2 - Disabled */ + 0x01b71cf0, // + 0x01b71d11, // + 0x01b71e11, // + 0x01b71f41, // + + /* Pin Complex (NID 0x1D) PCBeep */ + 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable + 0x01d71d81, // mute spkr on hpout + 0x01d71e15, // pcbeep en able, checksum + 0x01d71f40, // no physical, Internal, Location N/A + + /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ + 0x01e71cf0, // + 0x01e71d11, // + 0x01e71e11, // + 0x01e71f41, // + + /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ + 0x02171c21, // group2, cap 1 + 0x02171d10, // black, jack detect + 0x02171e21, // HPOut, 3.5mm Jack + 0x02171f03, // connector, left panel + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470c00, /* set speaker EAPD pin to low */ + 0x01470740, /* enable speaker out */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ + 0x01470c02, /* set speaker EAPD pin to high */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h b/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h new file mode 100644 index 0000000..0b2c664 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/include/variant/onboard.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +/* defines for programming the MAC address */ +#define BUDDY_NIC_VENDOR_ID 0x10EC +#define BUDDY_NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define BUDDY_NIC_LED_MODE 0x00 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */ +#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */ +#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */ +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 + +/* NIC wake is GPIO 8 */ +#define BUDDY_NIC_WAKE_GPIO 8 + +/* WLAN wake is GPIO 10 */ +#define BOARD_WLAN_WAKE_GPIO 10 +#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */ +#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */ + +#endif diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h new file mode 100644 index 0000000..cfdaca0 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h b/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h new file mode 100644 index 0000000..ae5c8f0 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/include/variant/thermal.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 0 /* PECI */ +#define CTL_TDP_POWER_LIMIT 12 /* 12W */ +#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/ +#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */ +#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c new file mode 100644 index 0000000..159d5f6 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 1; + + /* P0: Side USB3.0 port, USB3S1 */ + pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, + USB_PORT_INTERNAL); + /* P1: Rear USB3.0 port, USB3R1 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Rear USB3.0 port, USB3R2 */ + pei_data_usb2_port(pei_data, 2, 0x0080, 1, 1, + USB_PORT_INTERNAL); + /* P3: Card Rearder, CRS1 */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P4: Rear USB2.0 port, USB2R1 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: 2D Camera */ + pei_data_usb2_port(pei_data, 5, 0x0000, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P6: VP8 */ + pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P7: WLAN & BT */ + pei_data_usb2_port(pei_data, 7, 0x0000, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + + /* P1: Side USB3.0 port, USB3S1 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: Rear USB3.0 port, USB3R1 */ + pei_data_usb3_port(pei_data, 1, 1, 0, 0); + /* P3: Rear USB3.0 port, USB3R2 */ + pei_data_usb3_port(pei_data, 2, 1, 1, 0); + /* P4: Card Rearder, CRS1 */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +} diff --git a/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc b/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc new file mode 100644 index 0000000..275d983 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c new file mode 100644 index 0000000..93e9fb2 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/pei_data.h> +#include <variant/spd.h> + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[1] = 0x00; + pei_data->spd_addresses[2] = 0xa4; + pei_data->spd_addresses[3] = 0x00; + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + /* Enable 2x refresh mode */ + pei_data->ddr_refresh_2x = 1; + pei_data->dq_pins_interleaved = 1; +} diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c new file mode 100644 index 0000000..c682e36 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <fmap.h> +#include <types.h> +#include <string.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <smbios.h> +#include <soc/pch.h> +#include <variant/onboard.h> +#include <mainboard/google/auron/variant.h> + +int variant_smbios_data(device_t dev, int *handle, + unsigned long *current) +{ + int len = 0; + + len += smbios_write_type41( + current, handle, + BOARD_TOUCHSCREEN_NAME, /* name */ + BOARD_TOUCHSCREEN_IRQ, /* instance */ + BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ + BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + return len; +} + +static unsigned int search(char *p, u8 *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(u8 *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u8 *search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, search_address, sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base) +{ + void *search_address = NULL; + size_t search_length = -1; + + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { + search_address = rdev_mmap_full(&rdev); + + if (search_address != NULL) + search_length = region_device_sz(&rdev); + } + } else { + search_address = cbfs_boot_map_with_leak("vpd.bin", + CBFS_TYPE_RAW, + &search_length); + } + + if (search_address == NULL) + printk(BIOS_ERR, "LAN: VPD not found.\n"); + else + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + /* Disable register protection */ + outb(0xc0, io_base + 0x50); + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + /* Enable register protection again */ + outb(0x00, io_base + 0x50); + } +} + +void lan_init(void) +{ + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(BUDDY_NIC_VENDOR_ID, + BUDDY_NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((BUDDY_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} -- To view, visit https://review.coreboot.org/28613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a Gerrit-Change-Number: 28613 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/auron: Clean up variant-specific romstage code
by Matt DeVillier (Code Review) 15 Sep '18

15 Sep '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/28612 Change subject: google/auron: Clean up variant-specific romstage code ...................................................................... google/auron: Clean up variant-specific romstage code Use an empty weak function for variant_romstage_entry(), rather than having separate empty functions for boards which don't utilize it. Change-Id: I7a278ed716484bea377a5dd98d4a534502c8bab6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variants/auron_paine/variant.c M src/mainboard/google/auron/variants/auron_yuna/variant.c 3 files changed, 5 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/28612/1 diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index aedc33d..aea8e21 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -25,6 +25,10 @@ #include <variant/spd.h> #include "variant.h" +__weak void variant_romstage_entry(struct romstage_params *rp) +{ +} + void mainboard_romstage_entry(struct romstage_params *rp) { struct pei_data pei_data; @@ -43,6 +47,6 @@ /* Call into the real romstage main with this board's attributes. */ romstage_common(rp); - /* Do variant-specific (read: Samus) init */ + /* Do variant-specific init */ variant_romstage_entry(rp); } diff --git a/src/mainboard/google/auron/variants/auron_paine/variant.c b/src/mainboard/google/auron/variants/auron_paine/variant.c index f1af14d..b924976 100644 --- a/src/mainboard/google/auron/variants/auron_paine/variant.c +++ b/src/mainboard/google/auron/variants/auron_paine/variant.c @@ -12,7 +12,6 @@ */ #include <smbios.h> -#include <soc/romstage.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> @@ -32,8 +31,3 @@ return len; } - -void variant_romstage_entry(struct romstage_params *rp) -{ - /* N/A for boards other than SAMUS */ -} diff --git a/src/mainboard/google/auron/variants/auron_yuna/variant.c b/src/mainboard/google/auron/variants/auron_yuna/variant.c index f1af14d..b924976 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/variant.c +++ b/src/mainboard/google/auron/variants/auron_yuna/variant.c @@ -12,7 +12,6 @@ */ #include <smbios.h> -#include <soc/romstage.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> @@ -32,8 +31,3 @@ return len; } - -void variant_romstage_entry(struct romstage_params *rp) -{ - /* N/A for boards other than SAMUS */ -} -- To view, visit https://review.coreboot.org/28612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7a278ed716484bea377a5dd98d4a534502c8bab6 Gerrit-Change-Number: 28612 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/broadwell: Add PCH_GPIO_PIRQ_INVERT definition
by Matt DeVillier (Code Review) 15 Sep '18

15 Sep '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/28611 Change subject: soc/intel/broadwell: Add PCH_GPIO_PIRQ_INVERT definition ...................................................................... soc/intel/broadwell: Add PCH_GPIO_PIRQ_INVERT definition Add definition for PCH_GPIO_PIRQ_INVERT, which is needed for google/buddy, a to-be-merged variant of google/auron. Taken from Chromium commit 70ee99b [buddy: change trigger type of gpio53] Change-Id: I21448160cee791710df51d06efa32cdfecf38c0f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/broadwell/include/soc/gpio.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/28611/1 diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index c8f0300..d5ff7bb 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -148,6 +148,11 @@ .owner = GPIO_OWNER_GPIO, \ .pirq = GPIO_PIRQ_APIC_ROUTE } +#define PCH_GPIO_PIRQ_INVERT \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ + .owner = GPIO_OWNER_GPIO, \ + .pirq = GPIO_PIRQ_APIC_ROUTE } + #define PCH_GPIO_OUT_HIGH \ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \ .owner = GPIO_OWNER_GPIO, \ -- To view, visit https://review.coreboot.org/28611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I21448160cee791710df51d06efa32cdfecf38c0f Gerrit-Change-Number: 28611 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: ec: check to see if s0ix is enabled
by Paul Moy (Code Review) 14 Sep '18

14 Sep '18

Paul Moy has uploaded this change for review. ( https://review.coreboot.org/28610 Change subject: ec: check to see if s0ix is enabled ...................................................................... ec: check to see if s0ix is enabled Before trying to set the s0ix lazy wake up mask in the EC, added a check to make sure s0ix is enabled. Change-Id: I78896ffe6312409c9f241b3b3224169c188bb265 Signed-off-by: Paul Moy <pmoy(a)chromium.org> --- M src/ec/google/chromeec/ec.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/28610/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 449eaf3..e094e9a 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -312,7 +312,11 @@ printk(BIOS_DEBUG, "Error: Set S5 LAZY WAKE mask failed\n"); if (google_chromeec_set_s3_lazy_wake_mask(s3_mask)) printk(BIOS_DEBUG, "Error: Set S3 LAZY WAKE mask failed\n"); - if (google_chromeec_set_s0ix_lazy_wake_mask(s0ix_mask)) + /* + * Only set the s0ix lazy wake mask if the mask is nonzero. A mask + * of zero means that s0ix is not enabled on the platform. + */ + if (s0ix_mask && google_chromeec_set_s0ix_lazy_wake_mask(s0ix_mask)) printk(BIOS_DEBUG, "Error: Set S0iX LAZY WAKE mask failed\n"); } -- To view, visit https://review.coreboot.org/28610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I78896ffe6312409c9f241b3b3224169c188bb265 Gerrit-Change-Number: 28610 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Moy <pmoy(a)google.com>

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Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR
by Richard Spiegel (Code Review) 14 Sep '18

14 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28608 ) Change subject: amd/stoneyridge: Sync PSP base to MSR ...................................................................... Patch Set 1: (1 comment) The idea that the TPM problem was due to a general protection fault seems to be the correct one. https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c File src/soc/amd/stoneyridge/cpu.c: https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c@123 PS1, Line 123: setup_lapic(); I did a small modification based on your code, and tested. It worked through reboot and through S3 resume. I did not saw any GPF. static void model_15_init(struct device *dev) { check_mca(); setup_lapic(); /* Per AMD, sync an undocumented MSR with the PSP base address */ msr_t psp_msr; uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; psp_msr = rdmsr(0xc00110a2); if (psp_msr.lo == 0) { psp_msr.hi = 0; //This line might not be needed. psp_msr.lo = psp_bar; wrmsr(0xc00110a2, psp_msr); } } -- To view, visit https://review.coreboot.org/28608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Gerrit-Change-Number: 28608 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Sep 2018 20:58:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/zoombini: Use Chrome EC BOARDID definition
by Karthik Ramasubramanian (Code Review) 14 Sep '18

14 Sep '18

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/28609 Change subject: mb/google/zoombini: Use Chrome EC BOARDID definition ...................................................................... mb/google/zoombini: Use Chrome EC BOARDID definition The board_id() definition is the duplicate of chrome EC board_id definition. Remove the duplicate definition and select EC_GOOGLE_CHROMEEC_BOARDID Kconfig item. BUG=b:114001972,b:114677884,b:114677887 Change-Id: Id8b7027d653649e8e5791e455652c4e893a746c2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)codeaurora.org> Tested-by: Karthikeyan Ramasubramanian <kramasub(a)codeaurora.org> --- M src/mainboard/google/zoombini/Kconfig M src/mainboard/google/zoombini/Makefile.inc D src/mainboard/google/zoombini/boardid.c 3 files changed, 1 insertion(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/28609/1 diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig index 656d8b0..249b028 100644 --- a/src/mainboard/google/zoombini/Kconfig +++ b/src/mainboard/google/zoombini/Kconfig @@ -7,6 +7,7 @@ select DRIVERS_I2C_MAX98373 select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/zoombini/Makefile.inc b/src/mainboard/google/zoombini/Makefile.inc index 241cfe2..d4e9fd4 100644 --- a/src/mainboard/google/zoombini/Makefile.inc +++ b/src/mainboard/google/zoombini/Makefile.inc @@ -19,12 +19,10 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += boardid.c romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += memory.c romstage-y += romstage.c -ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/zoombini/boardid.c b/src/mainboard/google/zoombini/boardid.c deleted file mode 100644 index 7c68265..0000000 --- a/src/mainboard/google/zoombini/boardid.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boardid.h> -#include <stddef.h> -#include <ec/google/chromeec/ec.h> - -uint32_t board_id(void) -{ - MAYBE_STATIC uint32_t id = BOARD_ID_INIT; - - if (id == BOARD_ID_INIT) { - if (google_chromeec_get_board_version(&id)) - id = BOARD_ID_UNKNOWN; - } - - return id; -} -- To view, visit https://review.coreboot.org/28609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id8b7027d653649e8e5791e455652c4e893a746c2 Gerrit-Change-Number: 28609 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>

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Change in coreboot[master]: arch/x86/acpigen: Fix comment in _ROM method generator
by Felix Held (Code Review) 14 Sep '18

14 Sep '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/28591 ) Change subject: arch/x86/acpigen: Fix comment in _ROM method generator ...................................................................... arch/x86/acpigen: Fix comment in _ROM method generator Commit 24462e6507 ("x86/acpigen: Fix ACPI _ROM method") changed the code to generate a serialized method, but didn't adjust the comment. Change-Id: Ie7dbaff13d36f31e9d627609d0f74a4e9fa5a1e9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/28591 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/arch/x86/acpigen.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index e10d307..a630ef2 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1453,7 +1453,7 @@ ASSERT(bios) ASSERT(length) - /* Method (_ROM, 2, NotSerialized) */ + /* Method (_ROM, 2, Serialized) */ acpigen_write_method_serialized("_ROM", 2); /* OperationRegion("ROMS", SYSTEMMEMORY, current, length) */ -- To view, visit https://review.coreboot.org/28591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie7dbaff13d36f31e9d627609d0f74a4e9fa5a1e9 Gerrit-Change-Number: 28591 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume
by Felix Held (Code Review) 14 Sep '18

14 Sep '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/28589 ) Change subject: nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume ...................................................................... nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume Change-Id: Icac6e696efa1721933a1963b45d608d9ae735149 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/28589 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Nathaniel Roach <nroach44(a)gmail.com> Reviewed-by: Evgeny Zinoviev <me(a)ch1p.com> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Nathaniel Roach: Looks good to me, but someone else must approve Evgeny Zinoviev: Looks good to me, but someone else must approve diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0f72d88..46d5de8 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -437,7 +437,8 @@ halt(); } - fill_smbios17(&ctrl); + if (!s3resume) + fill_smbios17(&ctrl); } void perform_raminit(int s3resume) -- To view, visit https://review.coreboot.org/28589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Icac6e696efa1721933a1963b45d608d9ae735149 Gerrit-Change-Number: 28589 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2018