coreboot-gerrit September 2018

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Change in coreboot[master]: mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree
by Arthur Heymans (Code Review) 15 Sep '18

15 Sep '18

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/28595 ) Change subject: mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree ...................................................................... mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/28595 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb 2 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index f58fae7..dba3a69 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -62,6 +62,8 @@ device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end @@ -78,6 +80,8 @@ subsystemid 0x1849 0x27cc end device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # ISA bridge subsystemid 0x1849 0x27b8 chip superio/nuvoton/nct6776 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 36335c8..f12a50b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -57,6 +57,8 @@ device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end @@ -73,6 +75,8 @@ subsystemid 0x1849 0x27cc end device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # ISA bridge subsystemid 0x1849 0x27b8 chip superio/winbond/w83627dhg -- To view, visit https://review.coreboot.org/28595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca Gerrit-Change-Number: 28595 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: configs: add sercon port and disable pxe serial console for apu{2, 3, 4, 5}
by Piotr Król (Code Review) 15 Sep '18

15 Sep '18

Piotr Król has uploaded this change for review. ( https://review.coreboot.org/28616 Change subject: configs: add sercon port and disable pxe serial console for apu{2,3,4,5} ...................................................................... configs: add sercon port and disable pxe serial console for apu{2,3,4,5} To avoid mangled characters on serial output from iPXE we have to disable serial from iPXE console. More to that to have correct serial input we have to enable SeaBIOS SERCON option with default configuration. The only limitation of this configs is that apu5 doesn't detect iPXE - that platform is not for public use so it doesn't affect anyone. Change-Id: I124705bd691b3c8dcd9a2636b17c019d02732c5a Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> --- A configs/config.pcengines_apu1 M configs/config.pcengines_apu2 A configs/config.pcengines_apu3 A configs/config.pcengines_apu4 A configs/config.pcengines_apu5 5 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/28616/1 diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1 new file mode 100644 index 0000000..e511d65 --- /dev/null +++ b/configs/config.pcengines_apu1 @@ -0,0 +1,10 @@ +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_BOARD_PCENGINES_APU1=y +CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_PXE_ROM_ID="10ec,8168" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 index 2754024..08d4d4e 100644 --- a/configs/config.pcengines_apu2 +++ b/configs/config.pcengines_apu2 @@ -4,7 +4,9 @@ CONFIG_APU2_PINMUX_UART_C=y CONFIG_APU2_PINMUX_UART_D=y CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,157b" +# CONFIG_PXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 new file mode 100644 index 0000000..7acf014 --- /dev/null +++ b/configs/config.pcengines_apu3 @@ -0,0 +1,12 @@ +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_BOARD_PCENGINES_APU3=y +CONFIG_APU2_PINMUX_UART_C=y +CONFIG_APU2_PINMUX_UART_D=y +CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_PXE_ROM_ID="8086,1539" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 new file mode 100644 index 0000000..9e7ca5a --- /dev/null +++ b/configs/config.pcengines_apu4 @@ -0,0 +1,12 @@ +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_BOARD_PCENGINES_APU4=y +CONFIG_APU2_PINMUX_UART_C=y +CONFIG_APU2_PINMUX_UART_D=y +CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_PXE_ROM_ID="8086,1539" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 new file mode 100644 index 0000000..e5ddcee --- /dev/null +++ b/configs/config.pcengines_apu5 @@ -0,0 +1,12 @@ +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_BOARD_PCENGINES_APU5=y +CONFIG_APU2_PINMUX_UART_C=y +CONFIG_APU2_PINMUX_UART_D=y +CONFIG_NO_GFX_INIT=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_PXE_ROM_ID="8086,1539" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -- To view, visit https://review.coreboot.org/28616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I124705bd691b3c8dcd9a2636b17c019d02732c5a Gerrit-Change-Number: 28616 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com>

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by build bot (Jenkins) (Code Review) 15 Sep '18

15 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28606 ) Change subject: WIP: Port libpayload to riscv ...................................................................... Patch Set 5: (39 comments) https://review.coreboot.org/#/c/28606/5/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/28606/5/payloads/external/LinuxBoot/Makefil… PS5, Line 78: echo "BEFOR DEF" 'BEFOR' may be misspelled - perhaps 'BEFORE'? https://review.coreboot.org/#/c/28606/5/payloads/libpayload/arch/riscv/core… File payloads/libpayload/arch/riscv/coreboot.c: https://review.coreboot.org/#/c/28606/5/payloads/libpayload/arch/riscv/core… PS5, Line 42: switch(rec->tag) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/asm.h: https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 24: name: labels should not be indented https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 27: .size name, .-name space required before that '-' (ctx:VxV) https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/barrier.h: https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 57: #define mb() memory barrier without comment https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 58: #define rmb() memory barrier without comment https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 59: #define wmb() memory barrier without comment https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/cache.h: https://review.coreboot.org/#/c/28606/5/payloads/libpayload/include/riscv/a… PS5, Line 81: } void function return statements are not generally useful https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/linuxcheck.c File payloads/linuxcheck/linuxcheck.c: https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/linuxcheck.c@29 PS5, Line 29: // buts("Greetings from linuxcheck, via hard-coded calls to serial functions.\n"); line over 80 characters https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c File payloads/linuxcheck/riscv-fu540.c: https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@25 PS5, Line 25: uint32_t txdata; /* Transmit data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@25 PS5, Line 25: uint32_t txdata; /* Transmit data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@26 PS5, Line 26: uint32_t rxdata; /* Receive data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@26 PS5, Line 26: uint32_t rxdata; /* Receive data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@27 PS5, Line 27: uint32_t txctrl; /* Transmit control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@27 PS5, Line 27: uint32_t txctrl; /* Transmit control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@28 PS5, Line 28: uint32_t rxctrl; /* Receive control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@28 PS5, Line 28: uint32_t rxctrl; /* Receive control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@29 PS5, Line 29: uint32_t ie; /* UART interrupt enable */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@29 PS5, Line 29: uint32_t ie; /* UART interrupt enable */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@30 PS5, Line 30: uint32_t ip; /* UART interrupt pending */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@30 PS5, Line 30: uint32_t ip; /* UART interrupt pending */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@31 PS5, Line 31: uint32_t div; /* Baud rate divisor */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@31 PS5, Line 31: uint32_t div; /* Baud rate divisor */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@36 PS5, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@36 PS5, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@41 PS5, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@41 PS5, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@43 PS5, Line 43: while (!uart_can_tx(regs)) code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@43 PS5, Line 43: while (!uart_can_tx(regs)) please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@44 PS5, Line 44: ; /* TODO: implement a timeout */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@44 PS5, Line 44: ; /* TODO: implement a timeout */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@46 PS5, Line 46: write32(&regs->txdata, data); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/5/payloads/linuxcheck/riscv-fu540.c@46 PS5, Line 46: write32(&regs->txdata, data); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: comment Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 09:18:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28606 to look at the new patch set (#5). Change subject: WIP: Port libpayload to riscv ...................................................................... WIP: Port libpayload to riscv Work-in-progress port of libpayload to RISC-V Do not merge yet Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c A payloads/libpayload/arch/riscv/sysinfo.c A payloads/libpayload/arch/riscv/timer.c A payloads/libpayload/arch/riscv/util.S A payloads/libpayload/arch/riscv/virtual.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/config.riscv A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/barrier.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h M payloads/linuxcheck/Makefile M payloads/linuxcheck/linuxcheck.c A payloads/linuxcheck/riscv-fu540.c 28 files changed, 1,137 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28606/5 -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: newpatchset Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by build bot (Jenkins) (Code Review) 15 Sep '18

15 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28606 ) Change subject: WIP: Port libpayload to riscv ...................................................................... Patch Set 4: (39 comments) https://review.coreboot.org/#/c/28606/4/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/28606/4/payloads/external/LinuxBoot/Makefil… PS4, Line 78: echo "BEFOR DEF" 'BEFOR' may be misspelled - perhaps 'BEFORE'? https://review.coreboot.org/#/c/28606/4/payloads/libpayload/arch/riscv/core… File payloads/libpayload/arch/riscv/coreboot.c: https://review.coreboot.org/#/c/28606/4/payloads/libpayload/arch/riscv/core… PS4, Line 42: switch(rec->tag) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/asm.h: https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 24: name: labels should not be indented https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 27: .size name, .-name space required before that '-' (ctx:VxV) https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/barrier.h: https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 57: #define mb() memory barrier without comment https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 58: #define rmb() memory barrier without comment https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 59: #define wmb() memory barrier without comment https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/cache.h: https://review.coreboot.org/#/c/28606/4/payloads/libpayload/include/riscv/a… PS4, Line 81: } void function return statements are not generally useful https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/linuxcheck.c File payloads/linuxcheck/linuxcheck.c: https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/linuxcheck.c@29 PS4, Line 29: // buts("Greetings from linuxcheck, via hard-coded calls to serial functions.\n"); line over 80 characters https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c File payloads/linuxcheck/riscv-fu540.c: https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@25 PS4, Line 25: uint32_t txdata; /* Transmit data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@25 PS4, Line 25: uint32_t txdata; /* Transmit data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@26 PS4, Line 26: uint32_t rxdata; /* Receive data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@26 PS4, Line 26: uint32_t rxdata; /* Receive data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@27 PS4, Line 27: uint32_t txctrl; /* Transmit control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@27 PS4, Line 27: uint32_t txctrl; /* Transmit control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@28 PS4, Line 28: uint32_t rxctrl; /* Receive control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@28 PS4, Line 28: uint32_t rxctrl; /* Receive control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@29 PS4, Line 29: uint32_t ie; /* UART interrupt enable */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@29 PS4, Line 29: uint32_t ie; /* UART interrupt enable */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@30 PS4, Line 30: uint32_t ip; /* UART interrupt pending */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@30 PS4, Line 30: uint32_t ip; /* UART interrupt pending */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@31 PS4, Line 31: uint32_t div; /* Baud rate divisor */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@31 PS4, Line 31: uint32_t div; /* Baud rate divisor */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@36 PS4, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@36 PS4, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@41 PS4, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@41 PS4, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@43 PS4, Line 43: while (!uart_can_tx(regs)) code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@43 PS4, Line 43: while (!uart_can_tx(regs)) please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@44 PS4, Line 44: ; /* TODO: implement a timeout */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@44 PS4, Line 44: ; /* TODO: implement a timeout */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@46 PS4, Line 46: write32(&regs->txdata, data); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/4/payloads/linuxcheck/riscv-fu540.c@46 PS4, Line 46: write32(&regs->txdata, data); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: comment Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 09:01:07 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28606 to look at the new patch set (#4). Change subject: WIP: Port libpayload to riscv ...................................................................... WIP: Port libpayload to riscv Work-in-progress port of libpayload to RISC-V Do not merge yet Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/config.riscv A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/barrier.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h M payloads/linuxcheck/Makefile M payloads/linuxcheck/linuxcheck.c A payloads/linuxcheck/riscv-fu540.c 24 files changed, 972 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28606/4 -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: newpatchset Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by build bot (Jenkins) (Code Review) 15 Sep '18

15 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28606 ) Change subject: WIP: Port libpayload to riscv ...................................................................... Patch Set 3: (38 comments) https://review.coreboot.org/#/c/28606/3/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/28606/3/payloads/external/LinuxBoot/Makefil… PS3, Line 78: echo "BEFOR DEF" 'BEFOR' may be misspelled - perhaps 'BEFORE'? https://review.coreboot.org/#/c/28606/3/payloads/libpayload/arch/riscv/core… File payloads/libpayload/arch/riscv/coreboot.c: https://review.coreboot.org/#/c/28606/3/payloads/libpayload/arch/riscv/core… PS3, Line 42: switch(rec->tag) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/asm.h: https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 24: name: labels should not be indented https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 27: .size name, .-name space required before that '-' (ctx:VxV) https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/barrier.h: https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 57: #define mb() memory barrier without comment https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 58: #define rmb() memory barrier without comment https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 59: #define wmb() memory barrier without comment https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/cache.h: https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/a… PS3, Line 81: } void function return statements are not generally useful https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c File payloads/linuxcheck/riscv-fu540.c: https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@25 PS3, Line 25: uint32_t txdata; /* Transmit data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@25 PS3, Line 25: uint32_t txdata; /* Transmit data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@26 PS3, Line 26: uint32_t rxdata; /* Receive data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@26 PS3, Line 26: uint32_t rxdata; /* Receive data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@27 PS3, Line 27: uint32_t txctrl; /* Transmit control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@27 PS3, Line 27: uint32_t txctrl; /* Transmit control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@28 PS3, Line 28: uint32_t rxctrl; /* Receive control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@28 PS3, Line 28: uint32_t rxctrl; /* Receive control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@29 PS3, Line 29: uint32_t ie; /* UART interrupt enable */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@29 PS3, Line 29: uint32_t ie; /* UART interrupt enable */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@30 PS3, Line 30: uint32_t ip; /* UART interrupt pending */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@30 PS3, Line 30: uint32_t ip; /* UART interrupt pending */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@31 PS3, Line 31: uint32_t div; /* Baud rate divisor */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@31 PS3, Line 31: uint32_t div; /* Baud rate divisor */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@36 PS3, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@36 PS3, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@41 PS3, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@41 PS3, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@43 PS3, Line 43: while (!uart_can_tx(regs)) code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@43 PS3, Line 43: while (!uart_can_tx(regs)) please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@44 PS3, Line 44: ; /* TODO: implement a timeout */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@44 PS3, Line 44: ; /* TODO: implement a timeout */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@46 PS3, Line 46: write32(&regs->txdata, data); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@46 PS3, Line 46: write32(&regs->txdata, data); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: comment Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Sep 2018 08:42:07 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28606 to look at the new patch set (#3). Change subject: WIP: Port libpayload to riscv ...................................................................... WIP: Port libpayload to riscv Work-in-progress port of libpayload to RISC-V Do not merge yet Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/config.riscv A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/barrier.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h M payloads/linuxcheck/Makefile A payloads/linuxcheck/riscv-fu540.c 23 files changed, 964 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28606/3 -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: newpatchset Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: adding config for riscv experimentations
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Philipp Hug has abandoned this change. ( https://review.coreboot.org/28615 ) Change subject: adding config for riscv experimentations ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ic13811ed12f36397c6e63ba4321df10f59f0e9da Gerrit-Change-Number: 28615 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: adding config for riscv experimentations
by Philipp Hug (Code Review) 15 Sep '18

15 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28615 Change subject: adding config for riscv experimentations ...................................................................... adding config for riscv experimentations Change-Id: Ic13811ed12f36397c6e63ba4321df10f59f0e9da --- A payloads/libpayload/configs/config.riscv 1 file changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/28615/1 diff --git a/payloads/libpayload/configs/config.riscv b/payloads/libpayload/configs/config.riscv new file mode 100644 index 0000000..b441c6b --- /dev/null +++ b/payloads/libpayload/configs/config.riscv @@ -0,0 +1,98 @@ +# +# Automatically generated file; DO NOT EDIT. +# Libpayload Configuration +# + +# +# Generic Options +# +# CONFIG_LP_GPL is not set +# CONFIG_LP_EXPERIMENTAL is not set +# CONFIG_LP_DEVELOPER is not set +# CONFIG_LP_CHROMEOS is not set +CONFIG_LP_COMPILER_GCC=y +# CONFIG_LP_COMPILER_LLVM_CLANG is not set +# CONFIG_LP_MEMMAP_RAM_ONLY is not set + +# +# Architecture Options +# +# CONFIG_LP_ARCH_ARM is not set +# CONFIG_LP_ARCH_X86 is not set +# CONFIG_LP_ARCH_ARM64 is not set +# CONFIG_LP_ARCH_MIPS is not set +CONFIG_LP_ARCH_RISCV=y +CONFIG_LP_HEAP_SIZE=131072 +CONFIG_LP_STACK_SIZE=16384 +CONFIG_LP_BASE_ADDRESS=0x80100000 + +# +# Standard Libraries +# +CONFIG_LP_LIBC=y +# CONFIG_LP_CURSES is not set +CONFIG_LP_CBFS=y +CONFIG_LP_LZMA=y +CONFIG_LP_LZ4=y + +# +# Console Options +# +# CONFIG_LP_SKIP_CONSOLE_INIT is not set +CONFIG_LP_CBMEM_CONSOLE=y +CONFIG_LP_SERIAL_CONSOLE=y +# CONFIG_LP_8250_SERIAL_CONSOLE is not set +# CONFIG_LP_S5P_SERIAL_CONSOLE is not set +# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set +# CONFIG_LP_IPQ40XX_SERIAL_CONSOLE is not set +# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set +# CONFIG_LP_SERIAL_SET_SPEED is not set +# CONFIG_LP_SERIAL_ACS_FALLBACK is not set +CONFIG_LP_VIDEO_CONSOLE=y +# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set +# CONFIG_LP_PC_I8042 is not set +# CONFIG_LP_PC_MOUSE is not set +# CONFIG_LP_PC_KEYBOARD is not set + +# +# Drivers +# +# CONFIG_LP_MOUSE_CURSOR is not set +# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set +CONFIG_LP_TIMER_NONE=y +# CONFIG_LP_TIMER_MCT is not set +# CONFIG_LP_TIMER_TEGRA_1US is not set +# CONFIG_LP_TIMER_IPQ806X is not set +# CONFIG_LP_TIMER_ARMADA38X is not set +# CONFIG_LP_TIMER_IPQ40XX is not set +# CONFIG_LP_TIMER_ARM64_ARCH is not set +# CONFIG_LP_TIMER_RK3288 is not set +# CONFIG_LP_TIMER_RK3399 is not set +# CONFIG_LP_TIMER_CYGNUS is not set +# CONFIG_LP_TIMER_IMG_PISTACHIO is not set +# CONFIG_LP_TIMER_MTK is not set +# CONFIG_LP_TIMER_MVMAP2315 is not set +CONFIG_LP_TIMER_GENERIC_HZ=0 +CONFIG_LP_TIMER_GENERIC_REG=0x0 +CONFIG_LP_TIMER_GENERIC_HIGH_REG=0x0 +CONFIG_LP_STORAGE=y +# CONFIG_LP_STORAGE_64BIT_LBA is not set +CONFIG_LP_STORAGE_ATA=y +CONFIG_LP_STORAGE_ATAPI=y +CONFIG_LP_USB=y +CONFIG_LP_USB_OHCI=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y +# CONFIG_LP_USB_XHCI_MTK_QUIRK is not set +# CONFIG_LP_USB_DWC2 is not set +CONFIG_LP_USB_HID=y +CONFIG_LP_USB_HUB=y +# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set +CONFIG_LP_USB_MSC=y +CONFIG_LP_USB_GEN_HUB=y +# CONFIG_LP_USB_PCI is not set +# CONFIG_LP_UDC is not set +# CONFIG_LP_BIG_ENDIAN is not set +CONFIG_LP_LITTLE_ENDIAN=y +# CONFIG_LP_IO_ADDRESS_SPACE is not set +CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y -- To view, visit https://review.coreboot.org/28615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic13811ed12f36397c6e63ba4321df10f59f0e9da Gerrit-Change-Number: 28615 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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coreboot-gerrit September 2018