coreboot-gerrit September 2018

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Change in coreboot[master]: soc/sifive/fu540: Get SDRAM controller out of reset
by Philipp Hug (Code Review) 12 Sep '18

12 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28583 to look at the new patch set (#2). Change subject: soc/sifive/fu540: Get SDRAM controller out of reset ...................................................................... soc/sifive/fu540: Get SDRAM controller out of reset Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/sifive/fu540/clock.c 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28583/2 -- To view, visit https://review.coreboot.org/28583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874 Gerrit-Change-Number: 28583 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/sifive/fu540: Implement uart_platform_refclk for UART divisor cal...
by Philipp Hug (Code Review) 12 Sep '18

12 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28584 to look at the new patch set (#2). Change subject: soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation ...................................................................... soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation After changing clock from 33.33Mhz to 1Ghz the UART divisor needs to be recalculated. Return correct tlck frequency in uart_platform_refclk. Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/sifive/fu540/uart.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28584/2 -- To view, visit https://review.coreboot.org/28584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9 Gerrit-Change-Number: 28584 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/sifive/fu540: Implement uart_platform_refclk for UART divisor cal...
by Philipp Hug (Code Review) 12 Sep '18

12 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28584 Change subject: soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation ...................................................................... soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation After changing clock from 33.33Mhz to 1Ghz the UART divisor needs to be recalculated. Return correct tlck frequency in uart_platform_refclk. Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9 --- M src/soc/sifive/fu540/uart.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28584/1 diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index c53f42d..b563be1 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -13,8 +13,11 @@ * GNU General Public License for more details. */ +#include <stddef.h> +#include <stdint.h> #include <console/uart.h> #include <soc/addressmap.h> +#include <soc/clock.h> uintptr_t uart_platform_base(int idx) { @@ -29,5 +32,9 @@ /* * The SiFive UART uses tlclk, which is coreclk/2 as input */ - return 33330000 / 2; + + if (ENV_BOOTBLOCK) + return 33330000 / 2; + else + return clock_get_coreclk_khz() * KHz / 2; } -- To view, visit https://review.coreboot.org/28584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9 Gerrit-Change-Number: 28584 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: soc/sifive/fu540: Get SDRAM controller out of reset
by Philipp Hug (Code Review) 12 Sep '18

12 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28583 Change subject: soc/sifive/fu540: Get SDRAM controller out of reset ...................................................................... soc/sifive/fu540: Get SDRAM controller out of reset Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874 --- M src/soc/sifive/fu540/clock.c 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28583/1 diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index a59a1e8..2f55bf1 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -68,6 +68,12 @@ #define PRCI_CORECLKSEL_CORECLKSEL 1 +#define PRCI_DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1) << 0) +#define PRCI_DEVICESRESET_DDR_AXI_RST_N(x) (((x) & 0x1) << 1) +#define PRCI_DEVICESRESET_DDR_AHB_RST_N(x) (((x) & 0x1) << 2) +#define PRCI_DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3) +#define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5) + /* * Set coreclk according to the SiFive FU540-C000 Manual * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/ @@ -176,5 +182,33 @@ // put DDR and ethernet in reset write32(&prci->devicesresetreg, 0); + init_pll_ddr(); + + // The following code and its comments is mostly derived from the SiFive + // u540 bootloader. + // https://github.com/sifive/freedom-u540-c000-bootloader + + // get DDR out of reset + write32(&prci->devicesresetreg, PRCI_DEVICESRESET_DDR_CTRL_RST_N(1)); + + // HACK to get the '1 full controller clock cycle'. + asm volatile ("fence"); + + // get DDR out of reset + write32(&prci->devicesresetreg, + PRCI_DEVICESRESET_DDR_CTRL_RST_N(1) | + PRCI_DEVICESRESET_DDR_AXI_RST_N(1) | + PRCI_DEVICESRESET_DDR_AHB_RST_N(1) | + PRCI_DEVICESRESET_DDR_PHY_RST_N(1)); + + // HACK to get the '1 full controller clock cycle'. + asm volatile ("fence"); + + // These take like 16 cycles to actually propagate. We can't go sending + // stuff before they come out of reset. So wait. + // TODO: Add a register to read the current reset states, or DDR Control + // device? + for (int i = 0; i < 256; i++) + asm volatile ("nop"); } -- To view, visit https://review.coreboot.org/28583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874 Gerrit-Change-Number: 28583 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: soc/sifive/fu540: Update clock settings according SiFive bootloader
by Philipp Hug (Code Review) 12 Sep '18

12 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28582 Change subject: soc/sifive/fu540: Update clock settings according SiFive bootloader ...................................................................... soc/sifive/fu540: Update clock settings according SiFive bootloader The documentation unfortunately doesn't match what SiFive uses in their FSBL. Use the same values as in FSBL to make DDR RAM work. Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/sifive/fu540/clock.c 1 file changed, 28 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28582/1 diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index a59a1e8..2651f5a 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -46,11 +46,13 @@ #define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 #define PRCI_COREPLLCFG0_RANGE_SHIFT 18 #define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 +#define PRCI_COREPLLCFG0_FSE_SHIFT 25 #define PRCI_COREPLLCFG0_DIVR_MASK (0x03f << PRCI_COREPLLCFG0_DIVR_SHIFT) #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) #define PRCI_COREPLLCFG0_DIVQ_MASK (0x007 << PRCI_COREPLLCFG0_DIVQ_SHIFT) #define PRCI_COREPLLCFG0_RANGE_MASK (0x07 << PRCI_COREPLLCFG0_RANGE_SHIFT) #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) +#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) #define PRCI_DDRPLLCFG0_LOCK (1u << 31) #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 @@ -58,11 +60,13 @@ #define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 #define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 #define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 +#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 #define PRCI_DDRPLLCFG0_DIVR_MASK (0x03f << PRCI_DDRPLLCFG0_DIVR_SHIFT) #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x007 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) #define PRCI_DDRPLLCFG0_RANGE_MASK (0x07 << PRCI_DDRPLLCFG0_RANGE_SHIFT) #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) +#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) #define PRCI_DDRPLLCFG1_MASK (1u << 31) @@ -83,18 +87,28 @@ #define PRCI_CORECLK_DIVF 59 #define PRCI_CORECLK_DIVQ 2 #define PRCI_CORECLK_RANGE 4 +#define PRCI_CORECLK_BYPASS 0 +#define PRCI_CORECLK_FSE 1 /* * Section 7.4.3: DDR and Ethernet Subsystem Clocking and Reset - * GEMGXLPLL is set up for 125 MHz output frequency. - * divr = 0, divf = 59 (4000 MHz VCO), divq = 5 DDRPLL is set up to run at the + * + * Unfortunately the documentation example doesn't match the HiFive + * Unleashed board settings. + * Configuration values taken from SiFive FSBL: + * https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/mai… + * + * GEMGXLPLL is set up for 933 MHz output frequency. + * divr = 0, divf = 55 (4000 MHz VCO), divq = 2 DDRPLL is set up to run at the * memory MT/s divided by 4. */ #define PRCI_DDRCLK_DIVR 0 -#define PRCI_DDRCLK_DIVF 59 -#define PRCI_DDRCLK_DIVQ 5 +#define PRCI_DDRCLK_DIVF 55 +#define PRCI_DDRCLK_DIVQ 2 #define PRCI_DDRCLK_RANGE 4 +#define PRCI_DDRCLK_BYPASS 0 +#define PRCI_DDRCLK_FSE 1 // 33.33 Mhz after reset #define FU540_BASE_FQY 33330 @@ -108,11 +122,14 @@ u32 c = read32(&prci->corepllcfg0); clrsetbits_le32(&c, PRCI_COREPLLCFG0_DIVR_MASK | PRCI_COREPLLCFG0_DIVF_MASK | PRCI_COREPLLCFG0_DIVQ_MASK - | PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK, + | PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK + | PRCI_COREPLLCFG0_FSE_MASK, (PRCI_CORECLK_DIVR << PRCI_COREPLLCFG0_DIVR_SHIFT) | (PRCI_CORECLK_DIVF << PRCI_COREPLLCFG0_DIVF_SHIFT) | (PRCI_CORECLK_DIVQ << PRCI_COREPLLCFG0_DIVQ_SHIFT) - | (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT)); + | (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT) + | (PRCI_CORECLK_BYPASS << PRCI_COREPLLCFG0_BYPASS_SHIFT) + | (PRCI_CORECLK_FSE << PRCI_COREPLLCFG0_FSE_SHIFT)); write32(&prci->corepllcfg0, c); // wait for PLL lock @@ -134,11 +151,14 @@ u32 c = read32(&prci->ddrpllcfg0); clrsetbits_le32(&c, PRCI_DDRPLLCFG0_DIVR_MASK | PRCI_DDRPLLCFG0_DIVF_MASK | PRCI_DDRPLLCFG0_DIVQ_MASK - | PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK, + | PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK + | PRCI_DDRPLLCFG0_FSE_MASK, (PRCI_DDRCLK_DIVR << PRCI_DDRPLLCFG0_DIVR_SHIFT) | (PRCI_DDRCLK_DIVF << PRCI_DDRPLLCFG0_DIVF_SHIFT) | (PRCI_DDRCLK_DIVQ << PRCI_DDRPLLCFG0_DIVQ_SHIFT) - | (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT)); + | (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT) + | (PRCI_DDRCLK_BYPASS << PRCI_DDRPLLCFG0_BYPASS_SHIFT) + | (PRCI_DDRCLK_FSE << PRCI_DDRPLLCFG0_FSE_SHIFT)); write32(&prci->ddrpllcfg0, c); // wait for PLL lock -- To view, visit https://review.coreboot.org/28582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650 Gerrit-Change-Number: 28582 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: soc/intel/cannonlake: Add FSP CAR Init support for CFL
by build bot (Jenkins) (Code Review) 12 Sep '18

12 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28581 ) Change subject: soc/intel/cannonlake: Add FSP CAR Init support for CFL ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28581/1/src/soc/intel/cannonlake/bootblock/… File src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S: https://review.coreboot.org/#/c/28581/1/src/soc/intel/cannonlake/bootblock/… PS1, Line 98: .long CONFIG_ROM_SIZE /* Total Firmware Length */ line over 80 characters -- To view, visit https://review.coreboot.org/28581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic17bc827e57df6ba0b891f906c7adac1bb5d4d73 Gerrit-Change-Number: 28581 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Sep 2018 08:53:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Add FSP CAR Init support for CFL
by PraveenX Hodagatta Pranesh (Code Review) 12 Sep '18

12 Sep '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/28581 Change subject: soc/intel/cannonlake: Add FSP CAR Init support for CFL ...................................................................... soc/intel/cannonlake: Add FSP CAR Init support for CFL FSP2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to Coffeelake SoC when CONFIG_FSP_CAR is selected. coffeelake CRB's RVP11 & RVP8 uses entire FSP including FSP-T to setup CAR, MP init & MTRR programming without using coreboot Enhanced-NEM mode and coreboot MP init. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup. Change-Id: Ic17bc827e57df6ba0b891f906c7adac1bb5d4d73 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S A src/soc/intel/cannonlake/exit_car_fsp.S 5 files changed, 168 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28581/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4c4dfb2..9fe311e 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -53,6 +53,20 @@ Display the user specified product data prior to memory initialization. +config CPU_MICROCODE_CBFS_LEN + hex "Microcode update region length in bytes" + depends on FSP_CAR + default 0x0 + help + The length in bytes of the microcode update region. + +config CPU_MICROCODE_CBFS_LOC + hex "Microcode update base address in CBFS" + depends on FSP_CAR + default 0x0 + help + The location (base address) in CBFS that contains the microcode update binary. + config FSP_T_CBFS string "Name of FSP-T in CBFS" depends on FSP_CAR diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d5709ad..9d6b7db 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -52,6 +52,7 @@ cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS) $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(CONFIG_FSP_T_CBFS)-type := fsp +$(CONFIG_FSP_T_CBFS)-options := --xip cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 065d92b..01aed4f 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -21,6 +21,7 @@ bootblock-y += lpc.c bootblock-y += p2sb.c bootblock-$(CONFIG_UART_DEBUG) += uart.c +bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_FSP.S romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c romstage-y += gpio.c @@ -69,6 +70,7 @@ postcar-y += gspi.c postcar-y += spi.c postcar-$(CONFIG_UART_DEBUG) += uart.c +postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S verstage-y += gspi.c verstage-y += i2c.c diff --git a/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S b/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S new file mode 100644 index 0000000..bf75d1c --- /dev/null +++ b/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> + +#include <../../../arch/x86/walkcbfs.S> + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm + +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add $0x94, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebx), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + nop + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0x545F4450 /*CFLUPD_T*/ + .long 0x554C4643 /*CFLUPD_T*/ + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ + .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "fspt.bin\x00" diff --git a/src/soc/intel/cannonlake/exit_car_fsp.S b/src/soc/intel/cannonlake/exit_car_fsp.S new file mode 100644 index 0000000..e7457e0 --- /dev/null +++ b/src/soc/intel/cannonlake/exit_car_fsp.S @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> + +/* + * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed. + * This version of chipset_teardown_car sets up the stack, then bypasses + * the rest of arch/x86/exit_car.S and calls main() itself instead of + * returning to _start. In main(), the TempRamExit FSP API is called + * to tear down the CAR and set up caching which can be overwritten + * after the API call. More info can be found in the Apollo Lake FSP + * Integration Guide included with the FSP binary. The below + * caching settings are based on an 8MiB Flash Size given as a + * parameter to TempRamInit. + * + * TempRamExit MTRR Settings: + * 0x00000000 - 0x0009FFFF | Write Back + * 0x000C0000 - Top of Low Memory | Write Back + * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect + * 0x100000000 - Top of High Memory | Write Back + */ + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov post_car_stack_top, %esp + + /* Call C code */ + call main -- To view, visit https://review.coreboot.org/28581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic17bc827e57df6ba0b891f906c7adac1bb5d4d73 Gerrit-Change-Number: 28581 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com>

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Change in coreboot[master]: src/mainboard/*/*: Set Mini-ITX boards' category to "mini"
by Angel Pons (Code Review) 12 Sep '18

12 Sep '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28580 Change subject: src/mainboard/*/*: Set Mini-ITX boards' category to "mini" ...................................................................... src/mainboard/*/*: Set Mini-ITX boards' category to "mini" Change-Id: I637792d3bf22d2e452144d44ba03cfe45b47501d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/foxconn/d41s/board_info.txt M src/mainboard/intel/d510mo/board_info.txt M src/mainboard/intel/d945gclf/board_info.txt 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28580/1 diff --git a/src/mainboard/foxconn/d41s/board_info.txt b/src/mainboard/foxconn/d41s/board_info.txt index 965fcda..821b541 100644 --- a/src/mainboard/foxconn/d41s/board_info.txt +++ b/src/mainboard/foxconn/d41s/board_info.txt @@ -1,4 +1,4 @@ -Category: desktop +Category: mini Board URL: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us00004… ROM package: DIP-8 ROM protocol: SPI diff --git a/src/mainboard/intel/d510mo/board_info.txt b/src/mainboard/intel/d510mo/board_info.txt index 192798a..9fb0f15 100644 --- a/src/mainboard/intel/d510mo/board_info.txt +++ b/src/mainboard/intel/d510mo/board_info.txt @@ -1,4 +1,4 @@ -Category: desktop +Category: mini Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/intel/d945gclf/board_info.txt b/src/mainboard/intel/d945gclf/board_info.txt index 7a122bb..c1cbee86 100644 --- a/src/mainboard/intel/d945gclf/board_info.txt +++ b/src/mainboard/intel/d945gclf/board_info.txt @@ -1,3 +1,3 @@ -Category: desktop +Category: mini Board URL: http://www.intel.com/support/motherboards/desktop/d945gclf/sb/CS-029163.htm… Release year: 2008 -- To view, visit https://review.coreboot.org/28580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I637792d3bf22d2e452144d44ba03cfe45b47501d Gerrit-Change-Number: 28580 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: This change for DVT phase and use cbi method PORTING all of the memor...
by Peichao Li (Code Review) 12 Sep '18

12 Sep '18

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/28579 Change subject: This change for DVT phase and use cbi method PORTING all of the memory particles. ...................................................................... This change for DVT phase and use cbi method PORTING all of the memory particles. BUG=b:112870780 TEST=verify it under the EVT unit and pre-test EVT unit(rework RAM ID follow the proposal) respectively. Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/28579/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3ed88bd..906aeb8 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -110,6 +110,7 @@ config DRAM_PART_NUM_IN_CBI bool + default y config DRAM_PART_NUM_ALWAYS_IN_CBI bool @@ -120,7 +121,7 @@ depends on DRAM_PART_NUM_IN_CBI && !DRAM_PART_NUM_ALWAYS_IN_CBI default 255 if BOARD_GOOGLE_YORP default 255 if BOARD_GOOGLE_BIP - default 9 if BOARD_GOOGLE_PHASER + default 2 if BOARD_GOOGLE_PHASER default 9 if BOARD_GOOGLE_FLEEX default 9 if BOARD_GOOGLE_BOBBA default 9 if BOARD_GOOGLE_MEEP -- To view, visit https://review.coreboot.org/28579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa Gerrit-Change-Number: 28579 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: GPIO support for whiskey board
by Pratikkumar V Prajapati (Code Review) 11 Sep '18

11 Sep '18

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/28367 ) Change subject: mb/intel/coffeelake_rvp: GPIO support for whiskey board ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28367/2/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/28367/2/src/mainboard/intel/coffeelake_rvp/… PS2, Line 266: #if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) : PAD_CFG_GPO(GPP_H22, 1, PLTRST), : #endif With this GPP_H22 gets programmed 2 times for WHISKEYLAKE_RVP, keep #if and #else ? -- To view, visit https://review.coreboot.org/28367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Gerrit-Change-Number: 28367 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Sep 2018 01:24:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018