coreboot-gerrit September 2018

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Change in coreboot[master]: soc/sifive: fix compiler warning
by Patrick Georgi (Code Review) 10 Sep '18

10 Sep '18

Patrick Georgi has removed a vote on this change. Change subject: soc/sifive: fix compiler warning ...................................................................... Removed Verified-1 by build bot (Jenkins) <no-reply(a)coreboot.org> -- To view, visit https://review.coreboot.org/28553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteVote Gerrit-Change-Id: Ice87c821de7650ac547394efa2a4bcc5ae1ea668 Gerrit-Change-Number: 28553 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/sifive: fix compiler warning
by Patrick Georgi (Code Review) 10 Sep '18

10 Sep '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/28553 ) Change subject: soc/sifive: fix compiler warning ...................................................................... Patch Set 1: Verified+1 Code-Review+2 -- To view, visit https://review.coreboot.org/28553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ice87c821de7650ac547394efa2a4bcc5ae1ea668 Gerrit-Change-Number: 28553 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 10 Sep 2018 20:29:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: amd/stoneyridge: Set BERT region size when no TSEG used
by Marshall Dawson (Code Review) 10 Sep '18

10 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28554 Change subject: amd/stoneyridge: Set BERT region size when no TSEG used ...................................................................... amd/stoneyridge: Set BERT region size when no TSEG used Expand the BERT reserved region size setting to account for the possibility of no TSEG configuration. This change is only for completeness, as stoneyridge must always use TSEG. Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/ramtop.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28554/1 diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index e9a0e53..72db8ec 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -38,10 +38,14 @@ } #if IS_ENABLED(CONFIG_ACPI_BERT) -/* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ -#define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE + #if CONFIG_SMM_TSEG_SIZE == 0x0 + #define BERT_REGION_MAX_SIZE 0x100000 + #else + /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ + #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE + #endif #else -#define BERT_REGION_MAX_SIZE 0 + #define BERT_REGION_MAX_SIZE 0 #endif void bert_reserved_region(void **start, size_t *size) -- To view, visit https://review.coreboot.org/28554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66 Gerrit-Change-Number: 28554 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/sifive/fu540: Makefile: include mtime_init in ramstage
by Philipp Hug (Code Review) 10 Sep '18

10 Sep '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/28551 ) Change subject: soc/sifive/fu540: Makefile: include mtime_init in ramstage ...................................................................... Patch Set 4: @Xiang This fixes a compilation issue that appeared due to your 2 CR that have been merged. Does my fix look ok to you? -- To view, visit https://review.coreboot.org/28551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Gerrit-Change-Number: 28551 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 10 Sep 2018 18:37:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/sifive: fix compiler warning
by Philipp Hug (Code Review) 10 Sep '18

10 Sep '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/28553 ) Change subject: soc/sifive: fix compiler warning ...................................................................... Patch Set 1: Please merge this. This fixes a compiler warning introduced by the recent merge of 27435. There's another issue addressed by a separate patch. -- To view, visit https://review.coreboot.org/28553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ice87c821de7650ac547394efa2a4bcc5ae1ea668 Gerrit-Change-Number: 28553 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 10 Sep 2018 18:14:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/sifive/fu540: Makefile: include mtime_init in ramstage
by Philipp Hug (Code Review) 10 Sep '18

10 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28551 to look at the new patch set (#4). Change subject: soc/sifive/fu540: Makefile: include mtime_init in ramstage ...................................................................... soc/sifive/fu540: Makefile: include mtime_init in ramstage Fix compilation issue clint.c/mtime.c is needed as well in ramstage due to CR 28372 and 28355 Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/lowrisc/lowrisc/Makefile.inc M src/soc/sifive/fu540/Makefile.inc M src/soc/ucb/riscv/Makefile.inc 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/28551/4 -- To view, visit https://review.coreboot.org/28551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Gerrit-Change-Number: 28551 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: soc/sifive: fix compiler warning
by Philipp Hug (Code Review) 10 Sep '18

10 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28553 Change subject: soc/sifive: fix compiler warning ...................................................................... soc/sifive: fix compiler warning Fix the following compiler warning on the latest toolchain: src/soc/sifive/fu540/otp.c:48:1: error: useless storage class specifier in empty declaration [-Werror] } __packed; ^ Change-Id: Ice87c821de7650ac547394efa2a4bcc5ae1ea668 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/sifive/fu540/otp.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28553/1 diff --git a/src/soc/sifive/fu540/otp.c b/src/soc/sifive/fu540/otp.c index e6900fe..73a5573 100644 --- a/src/soc/sifive/fu540/otp.c +++ b/src/soc/sifive/fu540/otp.c @@ -29,7 +29,7 @@ * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/ */ -typedef struct sifive_otp_registers { +struct sifive_otp_registers { u32 pa; /* Address input */ u32 paio; /* Program address input */ u32 pas; /* Program redundancy cell selection input */ -- To view, visit https://review.coreboot.org/28553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ice87c821de7650ac547394efa2a4bcc5ae1ea668 Gerrit-Change-Number: 28553 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: soc/sifive/fu540: Makefile: include clint.c in ramstage
by Philipp Hug (Code Review) 10 Sep '18

10 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28551 to look at the new patch set (#3). Change subject: soc/sifive/fu540: Makefile: include clint.c in ramstage ...................................................................... soc/sifive/fu540: Makefile: include clint.c in ramstage Fix compliation issue. clint.c/mtime.c is needed as well in ramstage due to CR 28372 and 28355 Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/lowrisc/lowrisc/Makefile.inc M src/soc/sifive/fu540/Makefile.inc M src/soc/ucb/riscv/Makefile.inc 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/28551/3 -- To view, visit https://review.coreboot.org/28551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Gerrit-Change-Number: 28551 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: soc/sifive/fu540: Makefile: include clint.c in ramstage
by Philipp Hug (Code Review) 10 Sep '18

10 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28551 to look at the new patch set (#2). Change subject: soc/sifive/fu540: Makefile: include clint.c in ramstage ...................................................................... soc/sifive/fu540: Makefile: include clint.c in ramstage Fix compliation issue. clint.c is needed as well in ramstage due to CR 28372 and 28355 Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/sifive/fu540/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/28551/2 -- To view, visit https://review.coreboot.org/28551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Gerrit-Change-Number: 28551 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Assignee: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: ec/google/chromeec: Add support to query the board version
by Karthik Ramasubramanian (Code Review) 10 Sep '18

10 Sep '18

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/28552 Change subject: ec/google/chromeec: Add support to query the board version ...................................................................... ec/google/chromeec: Add support to query the board version The board version is part of EC's EEPROM. Add a helper function to query the EC regarding the board version. BUG=b:114001972,114677884,114677887 Change-Id: I57e8b78f1effe30bcbc81b275708be2d07f7cb75 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/28552/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 449eaf3..8caeeec 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -607,6 +607,11 @@ return cbi_get_uint32(id, CBI_TAG_OEM_ID); } +int google_chromeec_cbi_get_board_version(uint32_t *ver) +{ + return cbi_get_uint32(ver, CBI_TAG_BOARD_VERSION); +} + int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize) { struct ec_params_get_cbi p = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 2c6f1d6..32a6af1 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -74,6 +74,7 @@ */ int google_chromeec_cbi_get_oem_id(uint32_t *id); int google_chromeec_cbi_get_sku_id(uint32_t *id); +int google_chromeec_cbi_get_board_version(uint32_t *ver); int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); /* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */ -- To view, visit https://review.coreboot.org/28552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I57e8b78f1effe30bcbc81b275708be2d07f7cb75 Gerrit-Change-Number: 28552 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>

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coreboot-gerrit September 2018