coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

1 participants
886 discussions

Change in coreboot[master]: soc/sifive/fu540: Makefile: include clint.c in ramstage
by Philipp Hug (Code Review) 10 Sep '18

10 Sep '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/28551 ) Change subject: soc/sifive/fu540: Makefile: include clint.c in ramstage ...................................................................... Patch Set 1: Looks like merging both 28372 and 28355 together broke the build. This fixes the build issue. -- To view, visit https://review.coreboot.org/28551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Gerrit-Change-Number: 28551 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Assignee: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 10 Sep 2018 17:36:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/sifive/fu540: Makefile: include clint.c in ramstage
by Philipp Hug (Code Review) 10 Sep '18

10 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28551 Change subject: soc/sifive/fu540: Makefile: include clint.c in ramstage ...................................................................... soc/sifive/fu540: Makefile: include clint.c in ramstage Fix compliation issue. clint.c is needed as well in ramstage due to CR 28372 and 28355 Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 --- M src/soc/sifive/fu540/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/28551/1 diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 12b814a..b991783 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -24,6 +24,7 @@ romstage-y += otp.c ramstage-y += uart.c +ramstage-y += clint.c ramstage-y += media.c ramstage-y += sdram.c ramstage-y += cbmem.c -- To view, visit https://review.coreboot.org/28551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Gerrit-Change-Number: 28551 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

1 0

Change in coreboot[master]: Documentation: Disable auto_doc_ref
by Tom Hiller (Code Review) 10 Sep '18

10 Sep '18

Tom Hiller has posted comments on this change. ( https://review.coreboot.org/28550 ) Change subject: Documentation: Disable auto_doc_ref ...................................................................... Patch Set 1: Code-Review+1 Specifying the minimum versions in the documentation is a good idea. I am sorry for all of the problems pushing the update Sphinx has caused. Who ever is tasked with maintain the doc.coreboot.org Jenkins container should be reminded to rebuild it when this is merged. -- To view, visit https://review.coreboot.org/28550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9319985b504c4215c33ebbeb9c38317b9efcb283 Gerrit-Change-Number: 28550 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 10 Sep 2018 17:09:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Documentation: Disable auto_doc_ref
by Patrick Rudolph (Code Review) 10 Sep '18

10 Sep '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28550 Change subject: Documentation: Disable auto_doc_ref ...................................................................... Documentation: Disable auto_doc_ref According to recommonmark's documentation the enable_auto_doc_ref is deprecated. This is not true, as it's broken with Sphinx 1.6+ commit 12d639873953847de31ec99742b42e50e89ed58c. recommonmark bug report is here: https://github.com/rtfd/recommonmark/issues/73 Instead of using this feature, which doesn't support top level directories in the relative document path anyway, use the TOC tree or inline RST code. Disable auto_doc_ref and document how to reference documents. Change-Id: I9319985b504c4215c33ebbeb9c38317b9efcb283 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/conf.py M Documentation/getting_started/writing_documentation.md 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/28550/1 diff --git a/Documentation/conf.py b/Documentation/conf.py index ff1ad9d..07868fa 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -183,7 +183,7 @@ from recommonmark.transform import AutoStructify app.add_config_value('recommonmark_config', { 'enable_auto_toc_tree': True, - 'enable_auto_doc_ref': True, + 'enable_auto_doc_ref': False, # broken in Sphinx 1.6+ 'enable_eval_rst': True, 'url_resolver': lambda url: '/' + url }, True) diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index 027def9..d57244a 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -20,6 +20,9 @@ You will also need python-recommonmark for sphinx to be able to handle markdown documenation. +The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and +recommonmark 0.4.0. + ### Optional Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly! @@ -47,6 +50,11 @@ 12. Shouldn't cover implementation details; for details, the code is the reference. +## Referencing markdown documents + +Starting with Sphinx 1.6 recommonmark's *auto_doc_ref* feature is broken. +To reference documents use the TOC tree or inline RST code. + ## Markdown and Tables Under Sphinx markdown tables are not supported. Therefore you can use following -- To view, visit https://review.coreboot.org/28550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9319985b504c4215c33ebbeb9c38317b9efcb283 Gerrit-Change-Number: 28550 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nocturne: Update passive temperature thresholds
by Sumeet R Pawnikar (Code Review) 10 Sep '18

10 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28549 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nocturne: Update passive temperature thresholds ...................................................................... mb/google/poppy/variants/nocturne: Update passive temperature thresholds Update passive temperature threshold values for ambient and charger sensors. BUG=b:114678869 BRANCH=None TEST=Build coreboot for Nocturne board. Change-Id: I002cd21adfc50369356f81bee4c70ccbb55a6941 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/28549/2 -- To view, visit https://review.coreboot.org/28549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I002cd21adfc50369356f81bee4c70ccbb55a6941 Gerrit-Change-Number: 28549 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nocturne: Update passive temperature thresholds
by Sumeet R Pawnikar (Code Review) 10 Sep '18

10 Sep '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/28549 Change subject: mb/google/poppy/variants/nocturne: Update passive temperature thresholds ...................................................................... mb/google/poppy/variants/nocturne: Update passive temperature thresholds Update passive temperature threshold values for ambient and charger sensors. Change-Id: I002cd21adfc50369356f81bee4c70ccbb55a6941 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/28549/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl index c8bafb4..049839f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl @@ -19,12 +19,12 @@ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Ambient" -#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_PASSIVE 55 #define DPTF_TSR0_CRITICAL 90 #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "Charger" -#define DPTF_TSR1_PASSIVE 48 +#define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 90 #define DPTF_TSR2_SENSOR_ID 3 -- To view, visit https://review.coreboot.org/28549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I002cd21adfc50369356f81bee4c70ccbb55a6941 Gerrit-Change-Number: 28549 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

1 0

Change in coreboot[master]: google/grunt: Update ELAN TP/TS device ACPI nodes
by Kevin Chiu (Code Review) 10 Sep '18

10 Sep '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/28548 Change subject: google/grunt: Update ELAN TP/TS device ACPI nodes ...................................................................... google/grunt: Update ELAN TP/TS device ACPI nodes change ELAN TP/TS I2C irq to EDGE trigger to prevent any missing in interrupt handler. BUG=b:79996636 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I84c193b59aaa3b068f4cdc519d902fce6fb840c7 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28548/1 diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 513bd4e..991e7a1 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -130,7 +130,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)" register "wake" = "7" device i2c 15 on end end @@ -152,7 +152,7 @@ register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" -- To view, visit https://review.coreboot.org/28548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I84c193b59aaa3b068f4cdc519d902fce6fb840c7 Gerrit-Change-Number: 28548 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

1 0

Change in coreboot[master]: riscv: temporarily block multiple-threads
by build bot (Jenkins) (Code Review) 10 Sep '18

10 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27358 ) Change subject: riscv: temporarily block multiple-threads ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/#/c/27358/26/src/arch/riscv/include/arch/smp/sm… File src/arch/riscv/include/arch/smp/smp.h: https://review.coreboot.org/#/c/27358/26/src/arch/riscv/include/arch/smp/sm… PS26, Line 46: for (int i = 0; i < 32; i++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia0eeed51e0952c66a9a9f25a90105fe471ffa70e Gerrit-Change-Number: 27358 Gerrit-PatchSet: 26 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 10 Sep 2018 09:18:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: Enabled USB Power on Leaf Hill CRB.
by build bot (Jenkins) (Code Review) 10 Sep '18

10 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28547 ) Change subject: Enabled USB Power on Leaf Hill CRB. ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/#/c/28547/1/src/mainboard/intel/leafhill/brd_gp… File src/mainboard/intel/leafhill/brd_gpio.h: https://review.coreboot.org/#/c/28547/1/src/mainboard/intel/leafhill/brd_gp… PS1, Line 51: /// Added feature to enable USB power for USB devices, specifically keyboard and mouse. line over 80 characters https://review.coreboot.org/#/c/28547/1/src/mainboard/intel/leafhill/brd_gp… PS1, Line 51: /// Added feature to enable USB power for USB devices, specifically keyboard and mouse. code indent should use tabs where possible https://review.coreboot.org/#/c/28547/1/src/mainboard/intel/leafhill/brd_gp… PS1, Line 52: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_23, 1, DEEP, DN_20K, TxLASTRxE, SAME), /// Feature: LB USB Power in LFH line over 80 characters https://review.coreboot.org/#/c/28547/1/src/mainboard/intel/leafhill/brd_gp… PS1, Line 52: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_23, 1, DEEP, DN_20K, TxLASTRxE, SAME), /// Feature: LB USB Power in LFH code indent should use tabs where possible https://review.coreboot.org/#/c/28547/1/src/mainboard/intel/leafhill/brd_gp… PS1, Line 52: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_23, 1, DEEP, DN_20K, TxLASTRxE, SAME), /// Feature: LB USB Power in LFH please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I808d48789506123d544647ef3eefc0ea064d89a2 Gerrit-Change-Number: 28547 Gerrit-PatchSet: 1 Gerrit-Owner: Jose S. Cofreros Jr. <josh.cofreros(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 10 Sep 2018 08:33:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: Enabled USB Power on Leaf Hill CRB.
by Jose S. Cofreros Jr. (Code Review) 10 Sep '18

10 Sep '18

Jose S. Cofreros Jr. has uploaded this change for review. ( https://review.coreboot.org/28547 Change subject: Enabled USB Power on Leaf Hill CRB. ...................................................................... Enabled USB Power on Leaf Hill CRB. 1) Enabled USB Power on Leaf Hill CRB to use keyboard and mouse. Verified on Windows 10 Pro 10.0.17134 Build 17134. 2) Modified the following documentation that is blocking the original intent of this commit. - Verify that the word 'coreboot' is lowercase (lint-stable-021-coreboot-lowercase) - Documentation/Intel/SoC/quark.html - Documentation/Intel/SoC/soc.html - Documentation/Intel/development.html - Documentation/Intel/index.html Change-Id: I808d48789506123d544647ef3eefc0ea064d89a2 Signed-off-by: Jose S. Cofreros Jr <josh.cofreros(a)gmail.com> --- M Documentation/Intel/SoC/quark.html M Documentation/Intel/SoC/soc.html M Documentation/Intel/development.html M Documentation/Intel/index.html M src/mainboard/intel/leafhill/brd_gpio.h 5 files changed, 31 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/28547/1 diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index c3eead2..1575c07 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -19,7 +19,7 @@ <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> <li><a target="_blank" href="../Board/board.html">Board</a> support</li> <li><a target="_blank" href="#QuarkFsp">Quark™ FSP</a></li> - <li><a target="_blank" href="#CorebootPayloadPkg">CorebootPayloadPkg</a></li> + <li><a target="_blank" href="#corebootPayloadPkg">corebootPayloadPkg</a></li> </ul> </td> </tr> @@ -49,23 +49,23 @@ <hr> -<h2><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h2> +<h2><a name="corebootPayloadPkg">Quark™ EDK2 corebootPayloadPkg</a></h2> <p> Build Instructions: </p> <ol> <li>Set up <a href="#BuildEnvironment">build environment</a></li> <li>Linux (assumes GCC48): -<pre><code>build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -a IA32 \ +<pre><code>build -p corebootPayloadPkg/corebootPayloadPkgIa32.dsc -a IA32 \ -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 \ -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL \ -DMAX_LOGICAL_PROCESSORS=1 -ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd +ls Build/corebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd </code></pre> </li> <li>Windows (assumes Visual Studio 2015): -<pre><code>build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -a IA32 -t VS2015x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL -DMAX_LOGICAL_PROCESSORS=1 -dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd +<pre><code>build -p corebootPayloadPkg\corebootPayloadPkgIa32.dsc -a IA32 -t VS2015x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL -DMAX_LOGICAL_PROCESSORS=1 +dir Build\corebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd </code></pre> </li> <li>In the .config for coreboot, set the following Kconfig values: diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 29b819e..a796b85 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -572,18 +572,18 @@ <hr> <h2><a name="AcpiTables">ACPI Tables</a></h2> <p> - One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. + One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#corebootPayloadPkg">corebootPayloadPkg</a>. </p> <h3>FADT</h3> <p> The EDK2 module - CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbP…">CbParseLib.c</a> + corebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootModulePkg/Library/CbP…">CbParseLib.c</a> requires that the FADT contains the values in the table below. These values are placed into a HOB identified by - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootMod…">gUefiAcpiBoardInfoGuid</a> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootModulePkg/corebootMod…">gUefiAcpiBoardInfoGuid</a> by routine - CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPe…">CbPeiEntryPoint</a>. + corebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootModulePkg/CbSupportPe…">CbPeiEntryPoint</a>. </p> <table border="1"> <tr bgcolor="#c0ffc0"> @@ -600,9 +600,9 @@ <td>gpe0_blk<br>gpe0_blk_len</td> <td>Gpe0Blk<br>Gpe0BlkLen</td> <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbP…">PmGpeEnBase</a> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootModulePkg/Library/CbP…">PmGpeEnBase</a> </td> - <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a></td> + <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Re…">Shutdown</a></td> <td>4.8.4.1</td> </tr> <tr> @@ -610,8 +610,8 @@ <td>Pm1aCntBlk</td> <td>PmCtrlRegBase</td> <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a><br> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Suspend</a> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Re…">Shutdown</a><br> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Re…">Suspend</a> </td> <td>4.8.3.2.1</td> </tr> @@ -619,7 +619,7 @@ <td>pm1a_evt_blk</td> <td>Pm1aEvtBlk</td> <td>PmEvtBase</td> - <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a></td> + <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Re…">Shutdown</a></td> <td>4.8.3.1.1</td> </tr> <tr> @@ -627,7 +627,7 @@ <td>PmTmrBlk</td> <td>PmTimerRegBase</td> <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Ac…">Timer</a> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Ac…">Timer</a> </td> <td>4.8.3.3</td> </tr> @@ -636,9 +636,9 @@ <td>ResetReg.Address</td> <td>ResetRegAddress</td> <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Cold</a> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Re…">Cold</a> and - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Warm</a> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Re…">Warm</a> resets </td> <td>4.3.3.6</td> @@ -648,9 +648,9 @@ <td>ResetValue</td> <td>ResetValue</td> <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Cold</a> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Re…">Cold</a> and - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Warm</a> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/corebootPayloadPkg/Library/Re…">Warm</a> resets </td> <td>4.8.3.6</td> @@ -680,7 +680,7 @@ <hr> <h2><a name="LegacyHardware">Legacy Hardware</a></h2> <p> - One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. + One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#corebootPayloadPkg">corebootPayloadPkg</a>. </p> <table border="1"> diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 24b2fa9..08617c9 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -150,12 +150,12 @@ <tr> <td>8254 Programmable Interval Timer</td> <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> - <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> + <td><a target="_blank" href="SoC/quark.html#corebootPayloadPkg">corebootPayloadPkg</a> gets to shell prompt</td> </tr> <tr> <td>8259 Programmable Interrupt Controller</td> <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> - <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> + <td><a target="_blank" href="SoC/quark.html#corebootPayloadPkg">corebootPayloadPkg</a> gets to shell prompt</td> </tr> <tr> <td>Cache-as-RAM</td> @@ -374,4 +374,4 @@ <hr> <p>Modified: 4 March 2016</p> </body> -</html> \ No newline at end of file +</html> diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index b4daa96..d5f32a4 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -10,7 +10,7 @@ <h2>Intel® x86 Boards</h2> <ul> <li><a target="_blank" href="Board/galileo.html">Galileo</a></li> - <li><a target="_blank" href="http://wiki.minnowboard.org/Coreboot">MinnowBoard MAX</a></li> + <li><a target="_blank" href="http://wiki.minnowboard.org/coreboot">MinnowBoard MAX</a></li> </ul> <h2>Intel® x86 SoCs</h2> @@ -37,7 +37,7 @@ <hr> <h2>Payload Development</h2> <ul> - <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> + <li><a target="_blank" href="SoC/quark.html#corebootPayloadPkg">corebootPayloadPkg</a> <ul> <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Pr…">EDK II Development Process</a></li> <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20pa…">White Papers</a></li> diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h index 18d130b..ca99f11 100644 --- a/src/mainboard/intel/leafhill/brd_gpio.h +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -46,4 +46,9 @@ PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + +#ifdef CONFIG_BOARD_INTEL_LEAFHILL + /// Added feature to enable USB power for USB devices, specifically keyboard and mouse. + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_23, 1, DEEP, DN_20K, TxLASTRxE, SAME), /// Feature: LB USB Power in LFH +#endif }; -- To view, visit https://review.coreboot.org/28547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I808d48789506123d544647ef3eefc0ea064d89a2 Gerrit-Change-Number: 28547 Gerrit-PatchSet: 1 Gerrit-Owner: Jose S. Cofreros Jr. <josh.cofreros(a)gmail.com>

1 0

← Newer
1
...
65
66
67
68
69
70
71
...
89
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2018