coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: northbridge: Use 'unsigned int' to bare use of 'unsigned'
by Elyes HAOUAS (Code Review) 20 Sep '18

20 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28702 to look at the new patch set (#3). Change subject: northbridge: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... northbridge: Use 'unsigned int' to bare use of 'unsigned' Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/lx/raminit.h M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.h M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/gma.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c 17 files changed, 30 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28702/3 -- To view, visit https://review.coreboot.org/28702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Gerrit-Change-Number: 28702 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/glados/variants/sentry: Remove unnneded whitespace
by Elyes HAOUAS (Code Review) 20 Sep '18

20 Sep '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/28703 ) Change subject: mb/google/glados/variants/sentry: Remove unnneded whitespace ...................................................................... mb/google/glados/variants/sentry: Remove unnneded whitespace Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/glados/variants/sentry/Makefile.inc 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/28703/2 -- To view, visit https://review.coreboot.org/28703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1 Gerrit-Change-Number: 28703 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mbgoogle/glados/variants/sentry: Remove unnneded whitespace
by Elyes HAOUAS (Code Review) 20 Sep '18

20 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28703 Change subject: mbgoogle/glados/variants/sentry: Remove unnneded whitespace ...................................................................... mbgoogle/glados/variants/sentry: Remove unnneded whitespace Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/glados/variants/sentry/Makefile.inc 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/28703/1 diff --git a/src/mainboard/google/glados/variants/sentry/Makefile.inc b/src/mainboard/google/glados/variants/sentry/Makefile.inc index 0ebf605..a60bcae 100644 --- a/src/mainboard/google/glados/variants/sentry/Makefile.inc +++ b/src/mainboard/google/glados/variants/sentry/Makefile.inc @@ -19,22 +19,22 @@ SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Dual Channel 4GB +SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Dual Channel 4GB SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0001 Dual Channel 4GB -SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF # 0b0010 Dual Channel 4GB -SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 Dual Channel 8GB +SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF # 0b0010 Dual Channel 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 Dual Channel 8GB SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b0100 Dual Channel 8GB -SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0101 Dual Channel 8GB -SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR-NUD # 0b0110 Dual Channel 4GB -SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0111 Dual Channel 8GB -SPD_SOURCES += empty # 0b1000 -SPD_SOURCES += empty # 0b1001 -SPD_SOURCES += empty # 0b1010 -SPD_SOURCES += empty # 0b1011 -SPD_SOURCES += empty # 0b1100 -SPD_SOURCES += empty # 0b1101 -SPD_SOURCES += empty # 0b1110 -SPD_SOURCES += empty # 0b1111 +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0101 Dual Channel 8GB +SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR-NUD # 0b0110 Dual Channel 4GB +SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0111 Dual Channel 8GB +SPD_SOURCES += empty # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += empty # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += empty # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) -- To view, visit https://review.coreboot.org/28703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1 Gerrit-Change-Number: 28703 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/google/octopus: Create ampton variant
by build bot (Jenkins) (Code Review) 20 Sep '18

20 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28663 ) Change subject: mb/google/octopus: Create ampton variant ...................................................................... Patch Set 7: (117 comments) https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/ampton/gpio.c: https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 35: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 36: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 37: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 38: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 39: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 40: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 41: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 42: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 43: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 44: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 45: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 46: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 47: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 49: PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 51: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA6_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 52: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA7_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 53: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_CLK_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 54: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA0_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 55: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA1_VNN 0*/ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 56: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA2_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 57: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA3_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 58: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA4_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 59: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA5_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 60: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA6_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 61: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA7_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 62: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_CLK_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 63: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 64: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 65: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 70: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 71: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 72: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 79: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 80: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 81: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 82: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 85: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 86: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 89: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 90: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 92: PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 93: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 94: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 103: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 104: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 106: PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 118: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 119: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* H1_SLAVE_SPI_CS_L_R */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 120: PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 131: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 132: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 133: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 134: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 137: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 140: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 141: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 142: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 143: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 144: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 147: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 148: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 149: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 151: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 154: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 155: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 158: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 159: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 162: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 163: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 166: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 167: PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 169: PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 176: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 177: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 178: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 179: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 188: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 189: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTEN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 190: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTCTL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 193: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 194: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 195: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 198: PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 199: PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 202: PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 203: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 204: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 206: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 207: PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 211: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 226: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 227: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 229: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 230: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 231: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 232: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 233: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 234: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 237: PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_A1 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 238: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 239: PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_1 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 241: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 246: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* EN_PP3300_WLAN */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 265: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 267: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 268: PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 269: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 270: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 271: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 272: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 273: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 274: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 275: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 276: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 277: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 278: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ line over 80 characters https://review.coreboot.org/#/c/28663/7/src/mainboard/google/octopus/varian… PS7, Line 279: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters -- To view, visit https://review.coreboot.org/28663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3 Gerrit-Change-Number: 28663 Gerrit-PatchSet: 7 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 20 Sep 2018 17:26:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"
by Enrico Granata (Code Review) 20 Sep '18

20 Sep '18

Enrico Granata has posted comments on this change. ( https://review.coreboot.org/28690 ) Change subject: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" ...................................................................... Patch Set 1: Please solve the linter issue -- To view, visit https://review.coreboot.org/28690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Gerrit-Change-Number: 28690 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Sep 2018 17:21:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"
by Enrico Granata (Code Review) 20 Sep '18

20 Sep '18

Enrico Granata has posted comments on this change. ( https://review.coreboot.org/28690 ) Change subject: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" ...................................................................... Patch Set 1: Code-Review-1 -- To view, visit https://review.coreboot.org/28690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Gerrit-Change-Number: 28690 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Sep 2018 17:20:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: {device, drivers}: Use 'unsigned int' to bare use of 'unsigned'
by Elyes HAOUAS (Code Review) 20 Sep '18

20 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28700 to look at the new patch set (#2). Change subject: {device,drivers}: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... {device,drivers}: Use 'unsigned int' to bare use of 'unsigned' Change-Id: Iebb043a6fbc5803fbb7cad2f35b43917e10d09d4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_device.c M src/drivers/ricoh/rce822/rce822.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/28700/2 -- To view, visit https://review.coreboot.org/28700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iebb043a6fbc5803fbb7cad2f35b43917e10d09d4 Gerrit-Change-Number: 28700 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: {device, drivers}: Use 'unsigned int' to bare use of 'unsigned'
by build bot (Jenkins) (Code Review) 20 Sep '18

20 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28700 ) Change subject: {device,drivers}: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28700/1/src/drivers/ricoh/rce822/rce822.c File src/drivers/ricoh/rce822/rce822.c: https://review.coreboot.org/#/c/28700/1/src/drivers/ricoh/rce822/rce822.c@42 PS1, Line 42: static void rce822_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) line over 80 characters -- To view, visit https://review.coreboot.org/28700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iebb043a6fbc5803fbb7cad2f35b43917e10d09d4 Gerrit-Change-Number: 28700 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Sep 2018 15:53:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: northbridge: Use 'unsigned int' to bare use of 'unsigned'
by Elyes HAOUAS (Code Review) 20 Sep '18

20 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28702 Change subject: northbridge: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... northbridge: Use 'unsigned int' to bare use of 'unsigned' Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/lx/raminit.h M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.h M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/gma.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c 17 files changed, 29 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28702/1 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index ef54de5..2843b92 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -32,7 +32,7 @@ struct mem_controller; extern void activate_spd_rom(const struct mem_controller *ctrl); -extern int spd_read_byte(unsigned device, unsigned address); +extern int spd_read_byte(unsigned int device, unsigned int address); void fam15h_switch_dct(uint32_t dev, uint8_t dct) { diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h index 3a5d571..d106862 100644 --- a/src/northbridge/amd/lx/raminit.h +++ b/src/northbridge/amd/lx/raminit.h @@ -30,6 +30,6 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl); /* mainboard specific */ -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); #endif diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 6d351a3..b625a80 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -76,7 +76,7 @@ } static void intel_set_subsystem(struct device *dev, - unsigned vendor, unsigned device) + unsigned int vendor, unsigned int device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index eae8935..1581b82 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -35,6 +35,6 @@ /* Mainboard exports this. */ -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 27153f8..72b2761 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -173,7 +173,8 @@ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index 2cfd1f3..cba5869 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -66,8 +66,8 @@ gnvs_ptr->aslb = aslb; } -static void gma_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index b192161..111c201 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -248,8 +248,8 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 5335fbb..b86e2b3 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -788,7 +788,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 8f60da4..efc9fa3 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -494,8 +494,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index d8b4b66..52710bb 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -103,8 +103,8 @@ } } -static void minihd_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void minihd_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index f61a478..0453246 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -408,8 +408,8 @@ mc_add_dram_resources(dev, &index); } -static void intel_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 6e2d404..b89215d 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -623,7 +623,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 8f55e3c..4c6cdd4 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -191,7 +191,8 @@ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 02100e9..eb67c65 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -304,7 +304,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index a050e06..5adf865 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -102,7 +102,7 @@ __asm__ __volatile__("": : :"memory"); } -static inline int spd_read_byte(unsigned device, unsigned address) +static inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 042c2a9..cd8f7b9 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -669,7 +669,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7863810..cb0e5db 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -287,7 +287,8 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, -- To view, visit https://review.coreboot.org/28702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Gerrit-Change-Number: 28702 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: mb: Use 'unsigned int' to bare use of 'unsigned'
by Elyes HAOUAS (Code Review) 20 Sep '18

20 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28701 Change subject: mb: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... mb: Use 'unsigned int' to bare use of 'unsigned' Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c 24 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/28701/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index e59773f..e73a0e7 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -54,7 +54,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d4397b2..5ee1fd6 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -49,7 +49,7 @@ #include "cpu/amd/quadcore/quadcore.c" void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e5766c8..0e2db04 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -55,7 +55,7 @@ #include "cpu/amd/quadcore/quadcore.c" void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index ed5a6cb..ad3157f 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -51,7 +51,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; static void memreset_setup(void) diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 89d170c..89e72eb 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -53,7 +53,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index f203dd1..d18c2ad 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -32,7 +32,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) -int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 3410762..1d616a6 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -54,10 +54,10 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); } diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index cc198c6..036f136 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -59,10 +59,10 @@ #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 95fe630..98bb1ca 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -54,10 +54,10 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); } diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 6392f8f..4e05f0f 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -55,7 +55,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index dd61c8f..b4f6293 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -56,7 +56,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index e3f3f3c..fb1a134 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -55,7 +55,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index e2ce482..d91776c 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -54,7 +54,7 @@ #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 98bc00f..680d279 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -52,7 +52,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 81d4c6b..642f70b 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -52,7 +52,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 9f4dd44..923cfbc 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -55,7 +55,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 116a53a..fc922f4 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -57,7 +57,7 @@ #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -71,7 +71,7 @@ outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 866a9a8..5693cee 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -54,7 +54,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 760fc13..1041696 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -59,7 +59,7 @@ #endif void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 0b5d935..7848e9e 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -49,12 +49,12 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c360389..d5506df 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -53,12 +53,12 @@ #define SUPERIO_DEV PNP_DEV(0x2e, 0) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index ddbb97c..f438400 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -55,7 +55,7 @@ #define SMBUS_SWITCH2 0x72 void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -64,7 +64,7 @@ smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 6850995..a3d3cea 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -51,7 +51,7 @@ #include "cpu/amd/quadcore/quadcore.c" void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 373ff71..0b47f9d 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -49,12 +49,12 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -- To view, visit https://review.coreboot.org/28701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Gerrit-Change-Number: 28701 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit September 2018