coreboot-gerrit September 2018

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Change in coreboot[master]: sb/intel/bd82x6x: Don't use device_t
by Martin Roth (Code Review) 21 Sep '18

21 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28657 ) Change subject: sb/intel/bd82x6x: Don't use device_t ...................................................................... sb/intel/bd82x6x: Don't use device_t Use of device_t is deprecated. Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28657 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h 4 files changed, 20 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 70ba301..da1c7e4 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -115,7 +115,7 @@ } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -543,7 +543,7 @@ #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -610,7 +610,7 @@ } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -640,7 +640,7 @@ } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -687,14 +687,14 @@ } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -736,7 +736,7 @@ } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 9011787..1a59dc4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -117,7 +117,7 @@ } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -523,7 +523,7 @@ #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -597,7 +597,7 @@ } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -627,7 +627,7 @@ } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -674,14 +674,14 @@ } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; @@ -739,7 +739,7 @@ } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 79cf6bf..00265d0 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -208,9 +208,9 @@ } /* Check if any port in set X to X+3 is enabled */ -static int pch_pcie_check_set_enabled(device_t dev) +static int pch_pcie_check_set_enabled(struct device *dev) { - device_t port; + struct device *port; int port_func; int dev_func = PCI_FUNC(dev->path.pci.devfn); @@ -258,7 +258,7 @@ static void pch_pcie_devicetree_update( struct southbridge_intel_bd82x6x_config *config) { - device_t dev; + struct device *dev; /* * hotplug map should also be updated along with their @@ -312,7 +312,7 @@ } /* Special handling for PCIe Root Port devices */ -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; u32 reg32; @@ -422,7 +422,7 @@ } } -void pch_enable(device_t dev) +void pch_enable(struct device *dev) { u32 reg32; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 65aac55..66f5727 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -64,7 +64,7 @@ #if !defined(__PRE_RAM__) #if !defined(__SIMPLE_DEVICE__) #include "chip.h" -void pch_enable(device_t dev); +void pch_enable(struct device *dev); #endif int pch_silicon_revision(void); int pch_silicon_type(void); -- To view, visit https://review.coreboot.org/28657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Gerrit-Change-Number: 28657 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/quark/uart.c: Don't use device_t
by Martin Roth (Code Review) 21 Sep '18

21 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28677 ) Change subject: soc/intel/quark/uart.c: Don't use device_t ...................................................................... soc/intel/quark/uart.c: Don't use device_t Use of device_t is deprecated. Change-Id: Ia50aa96901b979b947fd4d269b077814c06f60c6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28677 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/quark/uart.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c index b4af08e..0d86284 100644 --- a/src/soc/intel/quark/uart.c +++ b/src/soc/intel/quark/uart.c @@ -21,7 +21,7 @@ #include <device/pci_ids.h> #include <soc/pci_devs.h> -static void uart_read_resources(device_t dev) +static void uart_read_resources(struct device *dev) { struct resource *res; -- To view, visit https://review.coreboot.org/28677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia50aa96901b979b947fd4d269b077814c06f60c6 Gerrit-Change-Number: 28677 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: include/device/pnp.h: Don't use device_t
by Martin Roth (Code Review) 21 Sep '18

21 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28676 ) Change subject: include/device/pnp.h: Don't use device_t ...................................................................... include/device/pnp.h: Don't use device_t Use of device_t is deprecated. Change-Id: I9364c9681dd89f09480368a997f6d1f04cde1488 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28676 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/include/device/pnp.h 1 file changed, 18 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index d753013..69e0f8f 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -10,21 +10,21 @@ #ifndef __SIMPLE_DEVICE__ /* Primitive PNP resource manipulation */ -void pnp_write_config(device_t dev, u8 reg, u8 value); -u8 pnp_read_config(device_t dev, u8 reg); -void pnp_set_logical_device(device_t dev); -void pnp_set_enable(device_t dev, int enable); -int pnp_read_enable(device_t dev); -void pnp_set_iobase(device_t dev, u8 index, u16 iobase); -void pnp_set_irq(device_t dev, u8 index, u8 irq); -void pnp_set_drq(device_t dev, u8 index, u8 drq); +void pnp_write_config(struct device *dev, u8 reg, u8 value); +u8 pnp_read_config(struct device *dev, u8 reg); +void pnp_set_logical_device(struct device *dev); +void pnp_set_enable(struct device *dev, int enable); +int pnp_read_enable(struct device *dev); +void pnp_set_iobase(struct device *dev, u8 index, u16 iobase); +void pnp_set_irq(struct device *dev, u8 index, u8 irq); +void pnp_set_drq(struct device *dev, u8 index, u8 drq); /* PNP device operations */ -void pnp_read_resources(device_t dev); -void pnp_set_resources(device_t dev); -void pnp_enable_resources(device_t dev); -void pnp_enable(device_t dev); -void pnp_alt_enable(device_t dev); +void pnp_read_resources(struct device *dev); +void pnp_set_resources(struct device *dev); +void pnp_enable_resources(struct device *dev); +void pnp_enable(struct device *dev); +void pnp_alt_enable(struct device *dev); extern struct device_operations pnp_ops; @@ -60,16 +60,16 @@ #define PNP_MSCE 0x800000 u16 io0, io1, io2, io3; }; -struct resource *pnp_get_resource(device_t dev, unsigned int index); +struct resource *pnp_get_resource(struct device *dev, unsigned int index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); struct pnp_mode_ops { - void (*enter_conf_mode)(device_t dev); - void (*exit_conf_mode)(device_t dev); + void (*enter_conf_mode)(struct device *dev); + void (*exit_conf_mode)(struct device *dev); }; -void pnp_enter_conf_mode(device_t dev); -void pnp_exit_conf_mode(device_t dev); +void pnp_enter_conf_mode(struct device *dev); +void pnp_exit_conf_mode(struct device *dev); /* PNP indexed I/O operations */ -- To view, visit https://review.coreboot.org/28676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9364c9681dd89f09480368a997f6d1f04cde1488 Gerrit-Change-Number: 28676 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Don't use device_t
by Martin Roth (Code Review) 21 Sep '18

21 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28693 ) Change subject: soc/intel/skylake: Don't use device_t ...................................................................... soc/intel/skylake: Don't use device_t Use of device_t is deprecated. Change-Id: Ifd1471a9cd76d2cea72262ed81b7071f31f7b375 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28693 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/intel/skylake/include/soc/pch.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index 18b030d..e9e2f2f 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -23,7 +23,7 @@ void pch_log_state(void); #if ENV_RAMSTAGE -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif #endif /* _SOC_PCH_H_ */ -- To view, visit https://review.coreboot.org/28693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ifd1471a9cd76d2cea72262ed81b7071f31f7b375 Gerrit-Change-Number: 28693 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/broadwell: Don't use device_t
by Martin Roth (Code Review) 21 Sep '18

21 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28692 ) Change subject: soc/broadwell: Don't use device_t ...................................................................... soc/broadwell: Don't use device_t Use of device_t is deprecated. Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28692 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/intel/broadwell/include/soc/pch.h M src/soc/intel/broadwell/include/soc/xhci.h M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/xhci.c 4 files changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index 690af9f..19ba2e0b 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -43,6 +43,6 @@ int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_log_state(void); -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h index cf1b135..33e4c2d 100644 --- a/src/soc/intel/broadwell/include/soc/xhci.h +++ b/src/soc/intel/broadwell/include/soc/xhci.h @@ -51,7 +51,7 @@ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ #ifdef __SMM__ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); #endif #endif diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index a8b25cf..c5df1ad 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -77,7 +77,7 @@ #ifndef __PRE_RAM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -92,7 +92,7 @@ } /* Set bit in Function Disable register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ @@ -183,7 +183,7 @@ } } -void broadwell_pch_enable_dev(device_t dev) +void broadwell_pch_enable_dev(struct device *dev) { u32 reg32; diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 75a63cf..8b4c7b1 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -25,7 +25,7 @@ #include <soc/cpu.h> #ifdef __SMM__ -static u8 *usb_xhci_mem_base(device_t dev) +static u8 *usb_xhci_mem_base(pci_devfn_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -36,7 +36,7 @@ return (u8 *)(mem_base & ~0xf); } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(pci_devfn_t dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -69,7 +69,7 @@ * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(pci_devfn_t dev, int all) { u32 status, port_disabled; int timeout, port; @@ -140,7 +140,7 @@ } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { u16 reg16; u32 reg32; -- To view, visit https://review.coreboot.org/28692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f Gerrit-Change-Number: 28692 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/riscv/include/arch: Don't use device_t
by Martin Roth (Code Review) 21 Sep '18

21 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28691 ) Change subject: arch/riscv/include/arch: Don't use device_t ...................................................................... arch/riscv/include/arch: Don't use device_t Use of device_t is deprecated. Change-Id: If52de0d87b02419090b29a7cf1952905d3f975f6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28691 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/riscv/include/arch/cpu.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index d2f42a8..4ee580c 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -31,7 +31,7 @@ struct thread; struct cpu_info { - device_t cpu; + struct device *cpu; unsigned long index; #if IS_ENABLED(CONFIG_COOP_MULTITASKING) struct thread *thread; -- To view, visit https://review.coreboot.org/28691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If52de0d87b02419090b29a7cf1952905d3f975f6 Gerrit-Change-Number: 28691 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/broadwell: Don't use device_t
by Jonathan Neuschäfer (Code Review) 21 Sep '18

21 Sep '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28692 ) Change subject: soc/broadwell: Don't use device_t ...................................................................... Patch Set 1: Code-Review+2 Looks good to me, thanks. -- To view, visit https://review.coreboot.org/28692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f Gerrit-Change-Number: 28692 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Sep 2018 12:02:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/amd: Use 'unsigned int' to bare use of 'unsigned'
by build bot (Jenkins) (Code Review) 21 Sep '18

21 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28709 ) Change subject: sb/amd: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... Patch Set 1: (11 comments) https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… File src/southbridge/amd/amd8111/amd8111_smbus.h: https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 66: static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 112: static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device, Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 113: unsigned value) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 155: static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device, Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 202: static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device, Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 241: static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device, Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 242: unsigned cmd, u8 bytes, u8 *buf) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 298: static int do_smbus_block_write(unsigned smbus_io_base, unsigned int device, Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/amd8111… PS1, Line 299: unsigned cmd, u8 bytes, const u8 *buf) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/early_s… File src/southbridge/amd/amd8111/early_smbus.c: https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/early_s… PS1, Line 63: static inline int smbus_block_read(unsigned int device, unsigned cmd, u8 bytes, Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28709/1/src/southbridge/amd/amd8111/early_s… PS1, Line 69: static inline int smbus_block_write(unsigned int device, unsigned cmd, u8 bytes, Prefer 'unsigned int' to bare use of 'unsigned' -- To view, visit https://review.coreboot.org/28709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05f9ea97ea80ac7a8f34845c59bd66e424ba2991 Gerrit-Change-Number: 28709 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Sep 2018 09:43:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sb/amd: Use 'unsigned int' to bare use of 'unsigned'
by Elyes HAOUAS (Code Review) 21 Sep '18

21 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28709 Change subject: sb/amd: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... sb/amd: Use 'unsigned int' to bare use of 'unsigned' Change-Id: I05f9ea97ea80ac7a8f34845c59bd66e424ba2991 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/amd8111/ac97.c M src/southbridge/amd/amd8111/acpi.c M src/southbridge/amd/amd8111/amd8111_smbus.h M src/southbridge/amd/amd8111/early_smbus.c M src/southbridge/amd/amd8111/ide.c M src/southbridge/amd/amd8111/lpc.c M src/southbridge/amd/amd8111/nic.c M src/southbridge/amd/amd8111/smbus.c M src/southbridge/amd/amd8111/usb.c M src/southbridge/amd/amd8111/usb2.c M src/southbridge/amd/cs5536/cs5536.h M src/southbridge/amd/cs5536/early_smbus.c 12 files changed, 44 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/28709/1 diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c index ce5911f..9e458ea 100644 --- a/src/southbridge/amd/amd8111/ac97.c +++ b/src/southbridge/amd/amd8111/ac97.c @@ -20,8 +20,8 @@ #include <device/pci_ops.h> #include "amd8111.h" -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 0948683..d2a9160 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -36,7 +36,7 @@ static int lsmbus_recv_byte(struct device *dev) { - unsigned device; + unsigned int device; struct resource *res; device = dev->path.i2c.device; @@ -47,7 +47,7 @@ static int lsmbus_send_byte(struct device *dev, uint8_t val) { - unsigned device; + unsigned int device; struct resource *res; device = dev->path.i2c.device; @@ -59,7 +59,7 @@ static int lsmbus_read_byte(struct device *dev, uint8_t address) { - unsigned device; + unsigned int device; struct resource *res; device = dev->path.i2c.device; @@ -70,7 +70,7 @@ static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val) { - unsigned device; + unsigned int device; struct resource *res; device = dev->path.i2c.device; @@ -82,7 +82,7 @@ static int lsmbus_block_read(struct device *dev, uint8_t cmd, u8 bytes, u8 *buffer) { - unsigned device; + unsigned int device; struct resource *res; device = dev->path.i2c.device; @@ -94,7 +94,7 @@ static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes, const u8 *buffer) { - unsigned device; + unsigned int device; struct resource *res; device = dev->path.i2c.device; @@ -217,8 +217,8 @@ } -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x7c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 944c601..33856b3 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -63,7 +63,7 @@ return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device) { unsigned global_status_register; unsigned byte; @@ -109,7 +109,8 @@ return byte; } -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned value) +static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device, + unsigned value) { unsigned global_status_register; @@ -151,7 +152,8 @@ } -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device, + unsigned int address) { unsigned global_status_register; unsigned byte; @@ -197,7 +199,8 @@ return byte; } -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device, + unsigned int address, unsigned char val) { unsigned global_status_register; @@ -235,7 +238,8 @@ return 0; } -static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 bytes, u8 *buf) +static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device, + unsigned cmd, u8 bytes, u8 *buf) { unsigned global_status_register; unsigned i; @@ -291,7 +295,8 @@ return i; } -static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +static int do_smbus_block_write(unsigned smbus_io_base, unsigned int device, + unsigned cmd, u8 bytes, const u8 *buf) { unsigned global_status_register; unsigned i; diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index f2aa34c..4925c86 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -39,32 +39,35 @@ printk(BIOS_SPEW, "SMBus controller enabled\n"); } -static inline int smbus_recv_byte(unsigned device) +static inline int smbus_recv_byte(unsigned int device) { return do_smbus_recv_byte(SMBUS_IO_BASE, device); } -static inline int smbus_send_byte(unsigned device, unsigned char val) +static inline int smbus_send_byte(unsigned int device, unsigned char val) { return do_smbus_send_byte(SMBUS_IO_BASE, device, val); } -static inline int smbus_read_byte(unsigned device, unsigned address) +static inline int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +static inline int smbus_write_byte(unsigned int device, unsigned int address, + unsigned char val) { return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } -static inline int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf) +static inline int smbus_block_read(unsigned int device, unsigned cmd, u8 bytes, + u8 *buf) { return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); } -static inline int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +static inline int smbus_block_write(unsigned int device, unsigned cmd, u8 bytes, + const u8 *buf) { return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); } diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index 9b6577a..420e28e 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -53,8 +53,8 @@ pci_write_config16(dev, 0x42, word); } -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 53dbf98..eab885d 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -124,8 +124,8 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index edfc584..30601fd 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -75,8 +75,8 @@ printk(BIOS_DEBUG, "Done\n"); } -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0xc8, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c index 5ff17b8..375234e 100644 --- a/src/southbridge/amd/amd8111/smbus.c +++ b/src/southbridge/amd/amd8111/smbus.c @@ -23,8 +23,8 @@ #include "amd8111.h" -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x44, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c index 62e4111..0b5a038 100644 --- a/src/southbridge/amd/amd8111/usb.c +++ b/src/southbridge/amd/amd8111/usb.c @@ -22,8 +22,8 @@ #include "amd8111.h" -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c index be25609..5d0d663 100644 --- a/src/southbridge/amd/amd8111/usb2.c +++ b/src/southbridge/amd/amd8111/usb2.c @@ -23,8 +23,8 @@ #if 0 -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index 4083f4f..06c504a 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -445,7 +445,7 @@ void cs5536_early_setup(void); void cs5536_enable_smbus(void); -int smbus_read_byte(unsigned device, unsigned address); +int smbus_read_byte(unsigned int device, unsigned int address); #else void chipsetinit(void); #endif diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c index ed2b942..a1cf50b 100644 --- a/src/southbridge/amd/cs5536/early_smbus.c +++ b/src/southbridge/amd/cs5536/early_smbus.c @@ -33,7 +33,7 @@ } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -- To view, visit https://review.coreboot.org/28709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I05f9ea97ea80ac7a8f34845c59bd66e424ba2991 Gerrit-Change-Number: 28709 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Add tdp_pl1_override value
by Sumeet R Pawnikar (Code Review) 21 Sep '18

21 Sep '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/28708 Change subject: mb/google/poppy/variants/nocturne: Add tdp_pl1_override value ...................................................................... mb/google/poppy/variants/nocturne: Add tdp_pl1_override value Add tdp_pl1_override value as 7W. BUG=None BRANCH=None TEST=Build coreboot for Nocturne board Change-Id: I16d3894da68bc3be6eff526062f9a88ef2df60c7 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/28708/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 3359a77..70a379c 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -66,6 +66,7 @@ # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" + register "tdp_pl1_override" = "7" register "tdp_pl2_override" = "18" register "psys_pmax" = "45" register "tcc_offset" = "10" -- To view, visit https://review.coreboot.org/28708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I16d3894da68bc3be6eff526062f9a88ef2df60c7 Gerrit-Change-Number: 28708 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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