coreboot-gerrit September 2018

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Change in coreboot[master]: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"
by Seunghwan Kim (Code Review) 21 Sep '18

21 Sep '18

Seunghwan Kim has posted comments on this change. ( https://review.coreboot.org/28690 ) Change subject: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" ...................................................................... Patch Set 2: Thanks for early cherry-picking of this! -- To view, visit https://review.coreboot.org/28690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Gerrit-Change-Number: 28690 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Sep 2018 00:26:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"
by Enrico Granata (Code Review) 21 Sep '18

21 Sep '18

Enrico Granata has posted comments on this change. ( https://review.coreboot.org/28690 ) Change subject: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" ...................................................................... Patch Set 2: Code-Review+1 Assuming it passes Jenkins, LGTM - we cherry-picked for FW-qual already so we should be good to go. Thanks! -- To view, visit https://review.coreboot.org/28690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Gerrit-Change-Number: 28690 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Sep 2018 00:20:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"
by Seunghwan Kim (Code Review) 21 Sep '18

21 Sep '18

Hello Enrico Granata, build bot (Jenkins), Enrico Granata, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28690 to look at the new patch set (#2). Change subject: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" ...................................................................... Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" This reverts commit aef592d9b66aa18d83b0a211ead26013ff1f7d98. Reason for revert: b:113303916 Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28690/2 -- To view, visit https://review.coreboot.org/28690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Gerrit-Change-Number: 28690 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lowrisc: Remove the Nexys4DDR port
by Jonathan Neuschäfer (Code Review) 20 Sep '18

20 Sep '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28706 Change subject: mb/lowrisc: Remove the Nexys4DDR port ...................................................................... mb/lowrisc: Remove the Nexys4DDR port This board doesn't support the newest RISC-V Privileged Architecture spec (1.10), and it's based on an FPGA so it's a moving target. Now that there's actual RISC-V silicon out there (from SiFive), mb/lowrisc/nexys4ddr will only continue to bitrot. Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M MAINTAINERS D src/mainboard/lowrisc/Kconfig D src/mainboard/lowrisc/Kconfig.name D src/mainboard/lowrisc/nexys4ddr/Kconfig D src/mainboard/lowrisc/nexys4ddr/Kconfig.name D src/mainboard/lowrisc/nexys4ddr/Makefile.inc D src/mainboard/lowrisc/nexys4ddr/board_info.txt D src/mainboard/lowrisc/nexys4ddr/devicetree.cb D src/mainboard/lowrisc/nexys4ddr/mainboard.c D src/mainboard/lowrisc/nexys4ddr/memlayout.ld D src/mainboard/lowrisc/nexys4ddr/rom_media.c D src/mainboard/lowrisc/nexys4ddr/romstage.c D src/mainboard/lowrisc/nexys4ddr/uart.c D src/soc/lowrisc/Kconfig D src/soc/lowrisc/lowrisc/Kconfig D src/soc/lowrisc/lowrisc/Makefile.inc D src/soc/lowrisc/lowrisc/cbmem.c M util/release/genrelnotes 18 files changed, 1 insertion(+), 322 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28706/1 diff --git a/MAINTAINERS b/MAINTAINERS index ca8a6f2..4d27129 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -124,10 +124,8 @@ M: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> S: Maintained F: src/arch/riscv/ -F: src/soc/lowrisc F: src/soc/ucb/ F: src/mainboard/emulation/*-riscv/ -F: src/mainboard/lowrisc POWER8 ARCHITECTURE M: Ronald Minnich <rminnich(a)gmail.com> diff --git a/src/mainboard/lowrisc/Kconfig b/src/mainboard/lowrisc/Kconfig deleted file mode 100644 index ba0fbe7..0000000 --- a/src/mainboard/lowrisc/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if VENDOR_LOWRISC - -choice - prompt "Mainboard model" - -source "src/mainboard/lowrisc/*/Kconfig.name" - -endchoice - -source "src/mainboard/lowrisc/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "lowrisc" - -endif # VENDOR_LOWRISC diff --git a/src/mainboard/lowrisc/Kconfig.name b/src/mainboard/lowrisc/Kconfig.name deleted file mode 100644 index 4c992fc..0000000 --- a/src/mainboard/lowrisc/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_LOWRISC - bool "lowrisc" diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig deleted file mode 100644 index 5a6bfb2..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 Google Inc. -## -## This software is licensed under the terms of the GNU General Public -## License version 2, as published by the Free Software Foundation, and -## may be copied, distributed, and modified under those terms. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. - -if BOARD_LOWRISC_NEXYS4DDR - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select SOC_LOWRISC_LOWRISC - select BOARD_ROMSIZE_KB_4096 - select DRIVERS_UART_8250MEM - select BOOT_DEVICE_NOT_SPI_FLASH - select UART_OVERRIDE_REFCLK - -config MAINBOARD_DIR - string - default lowrisc/nexys4ddr - -config MAINBOARD_PART_NUMBER - string - default "LOWRISC NEXYS4DDR" - -config MAX_CPUS - int - default 1 - -endif # BOARD_LOWRISC_NEXYS4DDR diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name deleted file mode 100644 index f99b3cc..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LOWRISC_NEXYS4DDR - bool "nexys4ddr" diff --git a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc deleted file mode 100644 index abd341c..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 Google Inc. -## -## This software is licensed under the terms of the GNU General Public -## License version 2, as published by the Free Software Foundation, and -## may be copied, distributed, and modified under those terms. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. - -bootblock-y += uart.c -bootblock-y += rom_media.c -romstage-y += romstage.c -romstage-y += uart.c -romstage-y += rom_media.c -ramstage-y += uart.c -ramstage-y += rom_media.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/lowrisc/nexys4ddr/board_info.txt b/src/mainboard/lowrisc/nexys4ddr/board_info.txt deleted file mode 100644 index a305030..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Board name: lowrisc nexys4ddr -Category: eval -Board URL: https://www.google.com/search?q=Tutorial+for+the+debug+preview+of+lowRISC&o… diff --git a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb deleted file mode 100644 index e857276..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 Google, Inc. -## -## This software is licensed under the terms of the GNU General Public -## License version 2, as published by the Free Software Foundation, and -## may be copied, distributed, and modified under those terms. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. - -chip soc/ucb/riscv - device cpu_cluster 0 on end - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing - end -end diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c deleted file mode 100644 index 3ef8337..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/mainboard.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <device/device.h> -#include <symbols.h> - -static void mainboard_enable(struct device *dev) -{ - uintptr_t ram_base; - size_t ram_size; - - /* FIXME: These values shouldn't necessarily be hardcoded */ - ram_base = 0x80000000; - ram_size = 128 * MiB; - ram_resource(dev, 0, ram_base / KiB, ram_size / KiB); - - cbmem_initialize_empty(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld deleted file mode 100644 index 86f3667..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <memlayout.h> - -#include <arch/header.ld> - -#define START 0x80000000 - -SECTIONS -{ - DRAM_START(START) - BOOTBLOCK(START, 64K) - STACK(START + 8M, 64K) - ROMSTAGE(START + 8M + 64K, 128K) - PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) - /* hole at (START + 8M + 200K, 56K) */ - RAMSTAGE(START + 8M + 256K, 256K) -} diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c deleted file mode 100644 index 7d4ed00..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/rom_media.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <boot_device.h> -#include <symbols.h> - -/* - * _dram is the start of RAM. We currently need to load coreboot.rom into - * RAM. The actual "rom" code on the FPGAs is in a block ram. - */ -static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &boot_dev.rdev; -} diff --git a/src/mainboard/lowrisc/nexys4ddr/romstage.c b/src/mainboard/lowrisc/nexys4ddr/romstage.c deleted file mode 100644 index c918c83..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/romstage.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <program_loading.h> -#include <console/console.h> - -void main(void) -{ - console_init(); - run_ramstage(); -} diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c deleted file mode 100644 index 7758db3..0000000 --- a/src/mainboard/lowrisc/nexys4ddr/uart.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <console/uart.h> -#include <arch/io.h> -#include <boot/coreboot_tables.h> - -uintptr_t uart_platform_base(int idx) -{ - return (uintptr_t) 0x42000000; -} - -/* The clock which the UART is based on */ -unsigned int uart_platform_refclk(void) -{ - return 25 * MHz; -} diff --git a/src/soc/lowrisc/Kconfig b/src/soc/lowrisc/Kconfig deleted file mode 100644 index a514135..0000000 --- a/src/soc/lowrisc/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -# Load all chipsets -source "src/soc/lowrisc/*/Kconfig" diff --git a/src/soc/lowrisc/lowrisc/Kconfig b/src/soc/lowrisc/lowrisc/Kconfig deleted file mode 100644 index 8b35231..0000000 --- a/src/soc/lowrisc/lowrisc/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -config SOC_LOWRISC_LOWRISC - select ARCH_RISCV - select ARCH_BOOTBLOCK_RISCV - select ARCH_VERSTAGE_RISCV - select ARCH_ROMSTAGE_RISCV - select ARCH_RAMSTAGE_RISCV - select BOOTBLOCK_CONSOLE - select DRIVERS_UART_8250MEM_32 - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER - select RISCV_USE_ARCH_TIMER - bool - default n - -if SOC_LOWRISC_LOWRISC - -config RISCV_ARCH - string - default "rv64imafd" - -config RISCV_ABI - string - default "lp64d" - -config RISCV_CODEMODEL - string - default "medany" - -endif diff --git a/src/soc/lowrisc/lowrisc/Makefile.inc b/src/soc/lowrisc/lowrisc/Makefile.inc deleted file mode 100644 index ccd9a16..0000000 --- a/src/soc/lowrisc/lowrisc/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -ifeq ($(CONFIG_SOC_LOWRISC_LOWRISC),y) - -bootblock-y += mtime.c -romstage-y += cbmem.c -ramstage-y += cbmem.c -ramstage-y += mtime.c - -endif diff --git a/src/soc/lowrisc/lowrisc/cbmem.c b/src/soc/lowrisc/lowrisc/cbmem.c deleted file mode 100644 index a212666..0000000 --- a/src/soc/lowrisc/lowrisc/cbmem.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - uintptr_t base; - size_t size; - - /* FIXME: These values shouldn't necessarily be hardcoded */ - base = 0x80000000; - size = 128 * MiB; - - return (void *)(base + size); -} diff --git a/util/release/genrelnotes b/util/release/genrelnotes index dfdf21e..3038eb3 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -349,7 +349,7 @@ get_log_dedupe "RISC-V" \ "$(for codedir in $(grep -rl "_RISCV" --include=Kconfig | grep -v 'payloads/\|drivers/\|vendorcode/\|console' ); do dirname "$codedir"; done | grep -v '^src$')" \ - "riscv\|risc-v\|lowrisc\|sifive" + "riscv\|risc-v\|sifive" get_log_dedupe "MIPS" \ "$(for codedir in $(grep -rl "_MIPS" --include=Kconfig | \ -- To view, visit https://review.coreboot.org/28706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Gerrit-Change-Number: 28706 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specific
by Richard Spiegel (Code Review) 20 Sep '18

20 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28705 Change subject: soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specific ...................................................................... soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specific STAPM programming was created inside function OemCustomizeInitEarly(). It should be SOC specific, and called by agesawarpper just before the call to OemCustomizeInitEarly(). BUG=b:116196626 TEST=build and boot grunt Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 27 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28705/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 74578c2..cdc1fe0 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -149,27 +149,8 @@ /*---------------------------------------------------------------------------*/ VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { - const struct soc_amd_stoneyridge_config *cfg; - const struct device *dev = dev_find_slot(0, GNB_DEVFN); - struct _PLATFORM_CONFIGURATION *platform; - InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow; InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; - if (!dev || !dev->chip_info) { - printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" - " config, STAPM unchanged\n"); - return; - } - cfg = dev->chip_info; - platform = &InitEarly->PlatformConfig; - if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) { - platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; - platform->PlatStapmConfig.CfgStapmTimeConstant = - cfg->stapm_time; - platform->PkgPwrLimitDC = cfg->stapm_power; - platform->PkgPwrLimitAC = cfg->stapm_power; - platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; - } } diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 9429366..713f76c 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -63,5 +63,6 @@ void SetFchMidParams(FCH_INTERFACE *params); void SetNbMidParams(GNB_MID_CONFIGURATION *params); void set_board_env_params(GNB_ENV_CONFIGURATION *params); +void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly); #endif /* __AGESAWRAPPER_H__ */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 5cd04ba..7ef2bda 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -31,6 +31,8 @@ #include <amdblocks/image.h> #include <amdblocks/BiosCallOuts.h> #include <soc/southbridge.h> +#include <soc/northbridge.h> +#include <soc/cpu.h> void __weak SetMemParams(AMD_POST_PARAMS *PostParams) {} void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -129,6 +131,7 @@ AMD_EARLY_PARAMS *EarlyParams = create_struct(&AmdParamStruct); + soc_customize_init_early(EarlyParams); OemCustomizeInitEarly(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_START); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index de22191..a5acaf6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -222,3 +222,26 @@ break; } } + +void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) +{ + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = dev_find_slot(0, GNB_DEVFN); + struct _PLATFORM_CONFIGURATION *platform; + + if (!dev || !dev->chip_info) { + printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" + " config, STAPM unchanged\n"); + return; + } + cfg = dev->chip_info; + platform = &InitEarly->PlatformConfig; + if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) { + platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; + platform->PlatStapmConfig.CfgStapmTimeConstant = + cfg->stapm_time; + platform->PkgPwrLimitDC = cfg->stapm_power; + platform->PkgPwrLimitAC = cfg->stapm_power; + platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; + } +} -- To view, visit https://review.coreboot.org/28705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047 Gerrit-Change-Number: 28705 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: src/cpu/via/nano: Remove unneeded include
by Martin Roth (Code Review) 20 Sep '18

20 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28704 ) Change subject: src/cpu/via/nano: Remove unneeded include ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I656b11add77012271ccc0c80dfcf97d20937dba2 Gerrit-Change-Number: 28704 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Sep 2018 19:39:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: northbridge: Use 'unsigned int' to bare use of 'unsigned'
by Martin Roth (Code Review) 20 Sep '18

20 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28702 ) Change subject: northbridge: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/28702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Gerrit-Change-Number: 28702 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Sep 2018 19:39:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb: Use 'unsigned int' to bare use of 'unsigned'
by Martin Roth (Code Review) 20 Sep '18

20 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28701 ) Change subject: mb: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Gerrit-Change-Number: 28701 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Sep 2018 19:37:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb: Use 'unsigned int' to bare use of 'unsigned'
by Martin Roth (Code Review) 20 Sep '18

20 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28701 ) Change subject: mb: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... Patch Set 2: Fantastic! Thank you! -- To view, visit https://review.coreboot.org/28701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Gerrit-Change-Number: 28701 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 20 Sep 2018 19:37:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/cpu/via/nano: Remove unneeded include
by Elyes HAOUAS (Code Review) 20 Sep '18

20 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28704 Change subject: src/cpu/via/nano: Remove unneeded include ...................................................................... src/cpu/via/nano: Remove unneeded include Change-Id: I656b11add77012271ccc0c80dfcf97d20937dba2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/via/nano/update_ucode.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28704/1 diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index 09f4d76..ef70d23 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -16,7 +16,6 @@ #ifndef __UPDATE_UCODE_H #define __UPDATE_UCODE_H -#include <console/console.h> #include <cpu/cpu.h> #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 -- To view, visit https://review.coreboot.org/28704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I656b11add77012271ccc0c80dfcf97d20937dba2 Gerrit-Change-Number: 28704 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit September 2018