coreboot-gerrit August 2018

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Change in coreboot[master]: src/arch/arm/armv7: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27920 Change subject: src/arch/arm/armv7: Fix typo ...................................................................... src/arch/arm/armv7: Fix typo Change-Id: I5838fdef41a2d84c3ec0ba4d9b2de5058530a2b9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/27920/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 304e43f..15e05cf 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -240,7 +240,7 @@ { TS_AGESA_S3_FINAL_DONE, "back from AmdS3FinalRestore" }, /* Intel ME related timestamps */ - { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"}, + { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgment of raminit"}, { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, /* FSP related timestamps */ -- To view, visit https://review.coreboot.org/27920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5838fdef41a2d84c3ec0ba4d9b2de5058530a2b9 Gerrit-Change-Number: 27920 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/arch: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27919 Change subject: src/arch: Fix typo ...................................................................... src/arch: Fix typo Change-Id: I24d219b4ce6033f64886e22973ca8716113d319f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/thread.c M src/arch/x86/thread.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/27919/1 diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c index 751745b..9c1c1bb 100644 --- a/src/arch/arm/armv7/thread.c +++ b/src/arch/arm/armv7/thread.c @@ -70,7 +70,7 @@ void __attribute__((naked)) switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack) { - /* Defintions for those of us not totally familiar with ARM: + /* Definitions for those of us not totally familiar with ARM: * R15 -- PC, R14 -- LR, R13 -- SP * R0-R3 need not be saved, nor R12. * on entry, the only saved state is in LR -- the old PC. diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c index 0a11141..b1cd99f 100644 --- a/src/arch/x86/thread.c +++ b/src/arch/x86/thread.c @@ -47,7 +47,7 @@ stack = push_stack(stack, (uintptr_t)arg); stack = push_stack(stack, (uintptr_t)0); stack = push_stack(stack, (uintptr_t)thread_entry); - /* Make room for the registers. Ignore intial values. */ + /* Make room for the registers. Ignore initial values. */ stack -= sizeof(struct pushad_regs); t->stack_current = stack; -- To view, visit https://review.coreboot.org/27919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I24d219b4ce6033f64886e22973ca8716113d319f Gerrit-Change-Number: 27919 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/cpu: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27918 Change subject: src/cpu: Fix typo ...................................................................... src/cpu: Fix typo Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_206ax/finalize.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/cpu/x86/16bit/entry16.inc 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27918/1 diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c index 53a6cc9..2d5973b 100644 --- a/src/cpu/intel/fsp_model_206ax/finalize.c +++ b/src/cpu/intel/fsp_model_206ax/finalize.c @@ -69,7 +69,7 @@ msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - /* Lock TM interupts - route thermal events to all processors */ + /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); /* Lock memory configuration to protect SMM */ diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index ba25387..ce22e62 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -72,7 +72,7 @@ msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - /* Lock TM interupts - route thermal events to all processors */ + /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); /* Lock memory configuration to protect SMM */ diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 5e7b3d8..8425f6a 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -52,6 +52,6 @@ if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); - /* Lock TM interupts - route thermal events to all processors */ + /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); } diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 50f4977..7d3cc2e 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -70,7 +70,7 @@ msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - /* Lock TM interupts - route thermal events to all processors */ + /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); /* Lock memory configuration to protect SMM */ diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index a87ce75..5a9739c 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -89,7 +89,7 @@ * must be loaded at or above 0xffff0000 or below 0x100000. * * The linker scripts computes gdtptr16_offset by simply returning - * the low 16 bits. This means that the intial segment used + * the low 16 bits. This means that the initial segment used * when start is called must be 64K aligned. This should not * restrict the address as the ip address can be anything. * -- To view, visit https://review.coreboot.org/27918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Gerrit-Change-Number: 27918 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/device: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27917 Change subject: src/device: Fix typo ...................................................................... src/device: Fix typo Change-Id: I65e57b37db9649b30ca25b2150f21ebffee73105 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/cardbus_device.c M src/device/oprom/x86emu/prim_ops.c M src/device/oprom/yabel/mem.c M src/device/oprom/yabel/vbe.c 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/27917/1 diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index 2924f89..b572e85 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -75,7 +75,7 @@ if (resource) { min_size = resource->size; /* - * Always allocate at least the miniumum size to a + * Always allocate at least the minimum size to a * cardbus bridge in case a new card is plugged in. */ if (resource->size < min_size) diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index 8b2c38a..3c4a8ca 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -68,7 +68,7 @@ * * By inspection, one gets: cc = ab + r'(a + b) * -* That represents alot of operations, but NO CHOICE.... +* That represents a lot of operations, but NO CHOICE.... * * Borrow Chain Calculation. * diff --git a/src/device/oprom/yabel/mem.c b/src/device/oprom/yabel/mem.c index 86d9982..49b6c4f 100644 --- a/src/device/oprom/yabel/mem.c +++ b/src/device/oprom/yabel/mem.c @@ -365,7 +365,7 @@ unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%x, %x): access to VGA Memory\n", __func__, addr, val); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -390,7 +390,7 @@ unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%x, %x): access to VGA Memory\n", __func__, addr, val); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); @@ -435,7 +435,7 @@ unsigned long translated_addr = addr; u8 translated = biosemu_dev_translate_address(IORESOURCE_MEM, &translated_addr); if (translated != 0) { - //translation successfull, access VGA Memory (BAR or Legacy...) + //translation successful, access VGA Memory (BAR or Legacy...) DEBUG_PRINTF_MEM("%s(%x, %x): access to VGA Memory\n", __func__, addr, val); //DEBUG_PRINTF_MEM("%s(%08x): translated_addr: %llx\n", __func__, addr, translated_addr); diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index c8b99d5..872ca15 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -502,7 +502,7 @@ vbe_get_ddc_info(&ddc_info); #if 0 - DEBUG_PRINTF_VBE("DDC: edid_tranfer_time: %d\n", + DEBUG_PRINTF_VBE("DDC: edid_transfer_time: %d\n", ddc_info.edid_transfer_time); DEBUG_PRINTF_VBE("DDC: ddc_level: %x\n", ddc_info.ddc_level); DEBUG_PRINTF_VBE("DDC: EDID:\n"); -- To view, visit https://review.coreboot.org/27917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I65e57b37db9649b30ca25b2150f21ebffee73105 Gerrit-Change-Number: 27917 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/drivers: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27916 Change subject: src/drivers: Fix typo ...................................................................... src/drivers: Fix typo Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/def_callouts.c M src/drivers/elog/elog.c M src/drivers/i2c/designware/dw_i2c.c M src/drivers/i2c/ww_ring/ww_ring.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/gma/i915_reg.h M src/drivers/intel/gma/opregion.c M src/drivers/maxim/max77802/max77802.h M src/drivers/net/chip.h M src/drivers/pc80/tpm/tis.c M src/drivers/ti/tps65913/tps65913rtc.c M src/drivers/xgi/common/vb_setmode.c 14 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/27916/1 diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 21530a1..3ef715f 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -91,7 +91,7 @@ // // Perform the RESET based upon the ResetType. In case of - // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // WARM_RESET_WHENEVER and COLD_RESET_WHENEVER, the request will go to // AmdResetManager. During the critical condition, where reset is required // immediately, the reset will be invoked directly by writing 0x04 to port // 0xCF9 (Reset Port). diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index d41457d..6fc4053 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -670,7 +670,7 @@ } if (region_device_sz(rdev) < 4*KiB) { - printk(BIOS_WARNING, "ELOG: Needs a minium size of 4KiB: %zu\n", + printk(BIOS_WARNING, "ELOG: Needs a minimum size of 4KiB: %zu\n", region_device_sz(rdev)); return -1; } diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 12284b6..d190d86 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -360,7 +360,7 @@ } /* The assumption is that the host controller is disabled -- either - after running this function or from performing the intialization + after running this function or from performing the initialization sequence in dw_i2c_init(). */ /* Set target slave address */ diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c index 61dfae7..306ac4d 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.c +++ b/src/drivers/i2c/ww_ring/ww_ring.c @@ -74,7 +74,7 @@ #define LP55231_RESET_VALUE 0xff /* - * The controller has 192 bytes of SRAM for code/data, availabe as six 32 byte + * The controller has 192 bytes of SRAM for code/data, available as six 32 byte * pages. */ #define LP55231_PROG_PAGE_SIZE 32 @@ -119,7 +119,7 @@ while (max_attempts--) { rv = i2c_transfer(ledc->i2c_bus, segs, seg_count); - /* Accessing reset regsiter is expected to fail. */ + /* Accessing reset register is expected to fail. */ if (!rv || reset) break; } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 51f9a75..0f13efe 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -128,7 +128,7 @@ params->pei_data->saved_data_size = region_device_sz(&rdev); params->pei_data->saved_data = rdev_mmap_full(&rdev); - /* Assum boot device is memory mapped. */ + /* Assume boot device is memory mapped. */ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); } else if (params->pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index f36f6de..8f4dc1e 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -36,7 +36,7 @@ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) fspm_display_upd_values(fspm_old_upd, fspm_new_upd); - /* Display the call entry point and paramters */ + /* Display the call entry point and parameters */ if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) return; printk(BIOS_SPEW, "Calling FspMemoryInit: 0x%p\n", memory_init); diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 123db30..5ed3801 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -107,7 +107,7 @@ * * This function is responsible for loading and executing the notify code from * the FSP-S binary. It expects that fsp_silicon_init() has already been called - * succesfully, and that the FSP-S binary is still loaded into memory. + * successfully, and that the FSP-S binary is still loaded into memory. */ #endif /* _FSP2_0_API_H_ */ diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index ae774a5..01c73f2 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -1636,9 +1636,9 @@ #define BLM_PIPE_C (2 << 29) /* ivb + */ #define BLM_PIPE(pipe) ((pipe) << 29) #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ -#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) +#define BLM_PHASE_IN_INTERRUPT_STATUS (1 << 26) #define BLM_PHASE_IN_ENABLE (1 << 25) -#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) +#define BLM_PHASE_IN_INTERRUPT_ENABL (1 << 24) #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) #define BLM_PHASE_IN_COUNT_SHIFT (8) diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 70cbccc..5def085 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -318,7 +318,7 @@ opregion->header.size = sizeof(igd_opregion_t) / 1024; /* - * Left-shift version field to accomodate Intel Windows driver quirk + * Left-shift version field to accommodate Intel Windows driver quirk * when not using a VBIOS. * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver. * diff --git a/src/drivers/maxim/max77802/max77802.h b/src/drivers/maxim/max77802/max77802.h index af2a80c..1284a1d 100644 --- a/src/drivers/maxim/max77802/max77802.h +++ b/src/drivers/maxim/max77802/max77802.h @@ -227,7 +227,7 @@ /* * MAX77802_REG_PMIC_BBAT set to - * Back up batery charger on and + * Back up battery charger on and * limit voltage setting to 3.5v */ #define MAX77802_BBCHOSTEN (1 << 0) diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 81dbefa..383614f 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -19,7 +19,7 @@ unsigned wake; /* Wake pin for ACPI _PRW */ /* * There maybe many NIC cards in a system. - * This paramter is for driver to identify what + * This parameter is for driver to identify what * the device number is and the valid range is [1-10]. */ uint8_t device_index; diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 495bb4a..67aff43 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -743,7 +743,7 @@ /* Set TPM interrupt vector */ tpm_write_int_vector(vector, locality); - /* Set TPM interupt polarity and disable interrupts */ + /* Set TPM interrupt polarity and disable interrupts */ tpm_write_int_polarity(polarity, locality); /* Close connection if it was opened */ diff --git a/src/drivers/ti/tps65913/tps65913rtc.c b/src/drivers/ti/tps65913/tps65913rtc.c index 0c19b16..b25fe35 100644 --- a/src/drivers/ti/tps65913/tps65913rtc.c +++ b/src/drivers/ti/tps65913/tps65913rtc.c @@ -29,7 +29,7 @@ TPS65913_WEEKS_REG = 0x06, TPS65913_RTC_CTRL_REG = 0x10, TPS65913_RTC_STATUS_REG = 0x11, - TPS65913_RTC_INTERRUPS_REG = 0x12, + TPS65913_RTC_INTERRUPTS_REG = 0x12, }; enum { diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index 1678b75..9ea8e79 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -958,7 +958,7 @@ data = xgifb_reg_get(pVBInfo->P3c4, 0x3D); data &= 0xfe; - xgifb_reg_set(pVBInfo->P3c4, 0x3D, data); /* diable auto-threshold */ + xgifb_reg_set(pVBInfo->P3c4, 0x3D, data); /* disable auto-threshold */ xgifb_reg_set(pVBInfo->P3c4, 0x08, 0x34); data = xgifb_reg_get(pVBInfo->P3c4, 0x09); -- To view, visit https://review.coreboot.org/27916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140 Gerrit-Change-Number: 27916 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/ec/google/chromeec: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27915 Change subject: src/ec/google/chromeec: Fix typo ...................................................................... src/ec/google/chromeec: Fix typo Change-Id: Ia05c9c5233319fe74d81c1f1db6ca3c2d875f9e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/ec_commands.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27915/1 diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 730be09..bafaa89 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -426,7 +426,7 @@ * parent structure that the alignment will still be true given the packing of * the parent structure. This is particularly important if the sub-structure * will be passed as a pointer to another function, since that function will - * not know about the misaligment caused by the parent structure's packing. + * not know about the misalignment caused by the parent structure's packing. * * Also be very careful using __packed - particularly when nesting non-packed * structures inside packed ones. In fact, DO NOT use __packed directly; -- To view, visit https://review.coreboot.org/27915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia05c9c5233319fe74d81c1f1db6ca3c2d875f9e7 Gerrit-Change-Number: 27915 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/include: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27914 Change subject: src/include: Fix typo ...................................................................... src/include: Fix typo Change-Id: Iff445dccf29957078b8308d73fb302d03cf47d31 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/bootblock_common.h M src/include/types.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/27914/1 diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 0f6c5e4..7af0ceb 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -24,7 +24,7 @@ /* * These are defined as weak no-ops that can be overridden by mainboard/SoC. * The 'early' variants are called prior to console initialization. Also, the - * SoC functions are called prior to the mainboard fucntions. + * SoC functions are called prior to the mainboard functions. */ void decompressor_soc_init(void); void bootblock_mainboard_early_init(void); diff --git a/src/include/types.h b/src/include/types.h index 7307cd5..b76c95b 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -34,7 +34,7 @@ * 100. */ enum cb_err { - CB_SUCCESS = 0, /**< Call completed succesfully */ + CB_SUCCESS = 0, /**< Call completed successfully */ CB_ERR = -1, /**< Generic error code */ CB_ERR_ARG = -2, /**< Invalid argument */ -- To view, visit https://review.coreboot.org/27914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iff445dccf29957078b8308d73fb302d03cf47d31 Gerrit-Change-Number: 27914 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src/lib: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27913 Change subject: src/lib: Fix typo ...................................................................... src/lib: Fix typo Change-Id: Ie5bf036a63a254dd95b45a0823086c8079eeafe2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/device_tree.c M src/lib/region_file.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27913/1 diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 00b36fd..a905dbf 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -751,7 +751,7 @@ * Write an arbitrary sized big-endian integer into a pointer. * * @param dest Pointer to the DT property data buffer to write. - * @param src The integer to write (in CPU endianess). + * @param src The integer to write (in CPU endianness). * @param length the length of the destination integer in bytes. */ void dt_write_int(u8 *dest, u64 src, size_t length) diff --git a/src/lib/region_file.c b/src/lib/region_file.c index 9d103f2..e42c2af 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -465,7 +465,7 @@ break; } - /* No more state changes and data commited. */ + /* No more state changes and data committed. */ if (f->slot > RF_ONLY_METADATA && prev_slot != f->slot) break; } -- To view, visit https://review.coreboot.org/27913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie5bf036a63a254dd95b45a0823086c8079eeafe2 Gerrit-Change-Number: 27913 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src/mainboard: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27912 Change subject: src/mainboard: Fix typo ...................................................................... src/mainboard: Fix typo Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/resourcemap.c M src/mainboard/amd/bimini_fam10/mainboard.c M src/mainboard/amd/bimini_fam10/resourcemap.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/mahogany_fam10/resourcemap.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c M src/mainboard/amd/south_station/mainboard.c M src/mainboard/amd/tilapia_fam10/resourcemap.c M src/mainboard/amd/torpedo/gpio.h M src/mainboard/amd/torpedo/platform_cfg.h M src/mainboard/amd/union_station/mainboard.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/kcma-d8/resourcemap.c M src/mainboard/asus/kfsn4-dre/resourcemap.c M src/mainboard/asus/kgpe-d16/resourcemap.c M src/mainboard/asus/m4a78-em/mainboard.c M src/mainboard/asus/m4a78-em/resourcemap.c M src/mainboard/asus/m4a785-m/mainboard.c M src/mainboard/asus/m4a785-m/resourcemap.c M src/mainboard/asus/m5a88-v/resourcemap.c M src/mainboard/avalue/eax-785e/resourcemap.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/mainboard/gigabyte/ma785gm/resourcemap.c M src/mainboard/gigabyte/ma785gmt/resourcemap.c M src/mainboard/gigabyte/ma78gm/resourcemap.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/urara/urara_boardid.h M src/mainboard/iei/kino-780am2-fam10/resourcemap.c M src/mainboard/jetway/nf81-t56n-lf/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/jetway/pa78vm5/resourcemap.c M src/mainboard/msi/ms9652_fam10/resourcemap.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/mptable.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/mainboard/siemens/mc_tcu3/ptn3460.h M src/mainboard/supermicro/h8dmr_fam10/resourcemap.c M src/mainboard/supermicro/h8qme_fam10/resourcemap.c M src/mainboard/supermicro/h8scm_fam10/resourcemap.c M src/mainboard/tyan/s2912_fam10/resourcemap.c 50 files changed, 61 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27912/1 diff --git a/src/mainboard/advansus/a785e-i/resourcemap.c b/src/mainboard/advansus/a785e-i/resourcemap.c index 4f2c074..19181fb 100644 --- a/src/mainboard/advansus/a785e-i/resourcemap.c +++ b/src/mainboard/advansus/a785e-i/resourcemap.c @@ -119,7 +119,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 572405d..6372c4b 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -29,7 +29,7 @@ volatile u8 *gpio_reg; - pm_iowrite(0xEA, 0x01); /* diable the PCIB */ + pm_iowrite(0xEA, 0x01); /* disable the PCIB */ /* Disable Gec */ byte = pm_ioread(0xF6); byte |= 1; diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c index dbd6341..b647f48 100644 --- a/src/mainboard/amd/bimini_fam10/resourcemap.c +++ b/src/mainboard/amd/bimini_fam10/resourcemap.c @@ -120,7 +120,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c index 020bc27..ebe20ac 100644 --- a/src/mainboard/amd/db-ft3b-lc/mptable.c +++ b/src/mainboard/amd/db-ft3b-lc/mptable.c @@ -30,7 +30,7 @@ struct mp_config_table *mc; int bus_isa; - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c index 92b4d27..7cc635c 100644 --- a/src/mainboard/amd/lamar/mptable.c +++ b/src/mainboard/amd/lamar/mptable.c @@ -44,7 +44,7 @@ struct mp_config_table *mc; int bus_isa; - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c index 95d009a..acdf645 100644 --- a/src/mainboard/amd/mahogany_fam10/resourcemap.c +++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index c21e0ea..95aec3d 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -85,7 +85,7 @@ */ /* * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because PCI INT_PIN swizzling isnt implemented to match + * but because PCI INT_PIN swizzling isn't implemented to match * the IDSEL (dev 3) of the slot, the table is adjusted for the * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index ccf0958..9e92ae8 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -39,7 +39,7 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index fd14a80..0e47c52 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -119,7 +119,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index d069838..1587d32 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <southbridge/amd/sb800/sb800.h> -#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "SBPLATFORM.h" /* Platform Specific Definitions */ /** * Southstation using SB GPIO 17/18 to control the Red/Green LED diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c index d696c4d..5a43814 100644 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c @@ -119,7 +119,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index 04897f5..938de53 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -298,8 +298,8 @@ #define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE #define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE // option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT +#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active +#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT #define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA #define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK #define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 72a97d1..622fffe 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -329,7 +329,7 @@ /** * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER * @li 0 - Auto : Detect Azalia controller automatically. - * @li 1 - Diable : Disable Azalia controller. + * @li 1 - Disable : Disable Azalia controller. * @li 2 - Enable : Enable Azalia controller. */ #define INCHIP_AZALIA_CONTROLLER 2 diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 8c71fd6..7ed27d8 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <southbridge/amd/sb800/sb800.h> -#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "SBPLATFORM.h" /* Platform Specific Definitions */ /********************************************** * Enable the dedicated functions of the board. diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c index bc7853b..82be639 100644 --- a/src/mainboard/asus/am1i-a/mptable.c +++ b/src/mainboard/asus/am1i-a/mptable.c @@ -39,7 +39,7 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c index 0de14ad..60bc3a7 100644 --- a/src/mainboard/asus/kcma-d8/resourcemap.c +++ b/src/mainboard/asus/kcma-d8/resourcemap.c @@ -124,7 +124,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, @@ -379,7 +379,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c index f4e549b..9644201 100644 --- a/src/mainboard/asus/kfsn4-dre/resourcemap.c +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -124,7 +124,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c index dcd7f77..c4dea39 100644 --- a/src/mainboard/asus/kgpe-d16/resourcemap.c +++ b/src/mainboard/asus/kgpe-d16/resourcemap.c @@ -124,7 +124,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, @@ -379,7 +379,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 8a017a0..b39f9db 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -76,7 +76,7 @@ /* * justify the dev3 is exist or not * NOTE: This just copied from AMD Tilapia code. - * It is completly unknown if it will work at all for this board. + * It is completely unknown if it will work at all for this board. */ int is_dev3_present(void) { diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c index 95d009a..acdf645 100644 --- a/src/mainboard/asus/m4a78-em/resourcemap.c +++ b/src/mainboard/asus/m4a78-em/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 23ead56..00a12cc 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -86,7 +86,7 @@ /* * justify the dev3 is exist or not * NOTE: This just copied from AMD Tilapia code. - * It is completly unknown it it will work at all for ASUS M4A785-M. + * It is completely unknown it it will work at all for ASUS M4A785-M. */ int is_dev3_present(void) { diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c index 95d009a..acdf645 100644 --- a/src/mainboard/asus/m4a785-m/resourcemap.c +++ b/src/mainboard/asus/m4a785-m/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c index 2978bab..2987b7c 100644 --- a/src/mainboard/asus/m5a88-v/resourcemap.c +++ b/src/mainboard/asus/m5a88-v/resourcemap.c @@ -119,7 +119,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c index 4f2c074..19181fb 100644 --- a/src/mainboard/avalue/eax-785e/resourcemap.c +++ b/src/mainboard/avalue/eax-785e/resourcemap.c @@ -119,7 +119,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c index bc42bb0..42d8431 100644 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ b/src/mainboard/bap/ode_e20XX/mptable.c @@ -38,7 +38,7 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index 1124ad9..dcf4321 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -38,7 +38,7 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 01d67c4..8f8b735 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -84,7 +84,7 @@ */ /* * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because PCI INT_PIN swizzling isnt implemented to match + * but because PCI INT_PIN swizzling isn't implemented to match * the IDSEL (dev 3) of the slot, the table is adjusted for the * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index ccf0958..9e92ae8 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -39,7 +39,7 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index d91d77a..857365b 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -36,7 +36,7 @@ write32(pl111 + 1, height - 1); /* registers 2, 3 and 5 are ignored by qemu. Set them correctly if we ever go for real hw. */ - /* framebuffer adress offset. Has to be in vram. */ + /* framebuffer address offset. Has to be in vram. */ write32(pl111 + 4, framebuffer); write32(pl111 + 7, 0); write32(pl111 + 10, 0xff); diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c index 95d009a..acdf645 100644 --- a/src/mainboard/gigabyte/ma785gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c index 95d009a..acdf645 100644 --- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gmt/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c index 95d009a..acdf645 100644 --- a/src/mainboard/gigabyte/ma78gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma78gm/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index bc42bb0..42d8431 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -38,7 +38,7 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index 33efdf7..24c9034 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -88,7 +88,7 @@ if (error) { printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); - die("Failed to intialize PMIC.\n"); + die("Failed to initialize PMIC.\n"); } } diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 1268df2..751b40b 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -241,7 +241,7 @@ exception_init(); if (power_init_failed) - die("Failed to intialize power.\n"); + die("Failed to initialize power.\n"); /* re-initialize PMIC I2C channel after (re-)setting system clocks */ i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h index bc61085..7c7c045 100644 --- a/src/mainboard/google/urara/urara_boardid.h +++ b/src/mainboard/google/urara/urara_boardid.h @@ -17,7 +17,7 @@ #define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ /* - * List of URARA derivatives board ID defintions. They are stored in uint8_t + * List of URARA derivatives board ID definitions. They are stored in uint8_t * across the code, using #defines here not to imply any specific size. */ #define URARA_BOARD_ID_BUB 0 diff --git a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c index 95d009a..acdf645 100644 --- a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c +++ b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 205b655..567a586 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -87,7 +87,7 @@ */ /* * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because PCI INT_PIN swizzling isnt implemented to match + * but because PCI INT_PIN swizzling isn't implemented to match * the IDSEL (dev 3) of the slot, the table is adjusted for the * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 92564c2..a933f60 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -42,7 +42,7 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/jetway/pa78vm5/resourcemap.c b/src/mainboard/jetway/pa78vm5/resourcemap.c index d6c8608..58b681f 100644 --- a/src/mainboard/jetway/pa78vm5/resourcemap.c +++ b/src/mainboard/jetway/pa78vm5/resourcemap.c @@ -122,7 +122,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c index 610baf3..825f5ae 100644 --- a/src/mainboard/msi/ms9652_fam10/resourcemap.c +++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c @@ -122,7 +122,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 290a0ed..de94937 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -91,7 +91,7 @@ */ /* * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because of PCI INT_PIN swizzle isnt implemented to match + * but because of PCI INT_PIN swizzle isn't implemented to match * the IDSEL (dev 3) of the slot, the table is adjusted for the * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index b183d8d..94a7d6f 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -39,7 +39,7 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index dff5fbd..772ee31 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -24,7 +24,7 @@ struct mp_config_table *mc; int bus_isa; - /* Intialize the MP_Table */ + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 347bc9c..89bc293 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -38,7 +38,7 @@ return 1; } - status = i2c_init(PTN_I2C_CONTROLER); + status = i2c_init(PTN_I2C_CONTROLLER); if (status) return (PTN_BUS_ERROR | status); @@ -66,7 +66,7 @@ /* Select this table to be emulated */ ptn_select_edid(6); /* Read PTN configuration data */ - status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, + status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, (u8*)&cfg, PTN_CONFIG_LEN); if (status) return (PTN_BUS_ERROR | status); @@ -94,7 +94,7 @@ cfg.backlight_ctrl = 0; /* Enable backlight control */ /* Write back configuration data to PTN3460 */ - status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, + status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, (u8*)&cfg, PTN_CONFIG_LEN); if (status) return (PTN_BUS_ERROR | status); @@ -114,13 +114,13 @@ if (edid_num > PTN_MAX_EDID_NUM) return PTN_INVALID_EDID; /* First enable access to the desired EDID table */ - status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, + status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, &edid_num, 1); if (status) return (PTN_BUS_ERROR | status); /* Now we can simply read back EDID-data */ - status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF, + status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF, data, PTN_EDID_LEN); if (status) return (PTN_BUS_ERROR | status); @@ -140,13 +140,13 @@ if (edid_num > PTN_MAX_EDID_NUM) return PTN_INVALID_EDID; /* First enable access to the desired EDID table */ - status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, + status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, &edid_num, 1); if (status) return (PTN_BUS_ERROR | status); /* Now we can simply write EDID-data to ptn3460 */ - status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF, + status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF, data, PTN_EDID_LEN); if (status) return (PTN_BUS_ERROR | status); @@ -168,7 +168,7 @@ return PTN_INVALID_EDID; /* Enable emulation of the desired EDID table */ val = (edid_num << 1) | 1; - status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, + status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, &val, 1); if (status) return (PTN_BUS_ERROR | status); @@ -191,7 +191,7 @@ flash.cmd = 0x01; /* perform erase and flash cycle */ flash.magic = 0x7845; /* Magic number to protect flash operation */ flash.trigger = 0x56; /* This value starts flash operation */ - status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF, + status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF, (u8*)&flash, PTN_FLASH_CFG_LEN); if (status) { return (PTN_BUS_ERROR | status); diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h index e662f61..5988c93 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.h +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h @@ -21,7 +21,7 @@ #include "lcd_panel.h" #define PTN_SLAVE_ADR 0x20 -#define PTN_I2C_CONTROLER 0 +#define PTN_I2C_CONTROLLER 0 #define PTN_EDID_OFF 0x00 #define PTN_EDID_LEN 0x80 diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c index b35d3e5..d4cbc93 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c @@ -122,7 +122,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c index b35d3e5..d4cbc93 100644 --- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c @@ -122,7 +122,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c index 95d009a..acdf645 100644 --- a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index bc03d21..10c97f5 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -122,7 +122,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that + * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, -- To view, visit https://review.coreboot.org/27912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Gerrit-Change-Number: 27912 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src/northbridge: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27911 Change subject: src/northbridge: Fix typo ...................................................................... src/northbridge: Fix typo Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/resourcemap.c M src/northbridge/amd/amdht/h3ffeat.h M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c 10 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/27911/1 diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index b744e96..5102b0b 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -314,7 +314,7 @@ // for 0x98 index and 0x9c data for DCT0 // for 0x198 index and 0x19c data for DCT1 -// even at ganged mode, 0x198/0x19c will be used for channnel B +// even at ganged mode, 0x198/0x19c will be used for channel B #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 #define DCAO_DctOffset_SHIFT 0 @@ -368,9 +368,9 @@ #define DODCC_ProcOdt_75_OHMS 2 /* - for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs - for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0 - F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1 + for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs + for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 + F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 So Socket F with Four Logical DIMM will only support DDR2 800 ? */ /* there are index +100 ===> for DIMM1 diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 5db6886..362872b 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit + * This field defines the upp address bits of a 40-bit * address that defines the end of a memory-mapped * I/O region n */ diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index 59e8feb..2cf4bd1 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -157,7 +157,7 @@ */ sPortDescriptor PortList[MAX_PLATFORM_LINKS*2]; - /* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */ + /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */ u8 sysDegree[MAX_NODES]; /* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */ BOOL sysMatrix[MAX_NODES][MAX_NODES]; @@ -169,7 +169,7 @@ u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */ u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */ - /* Data for non-coherent initilization */ + /* Data for non-coherent initialization */ u8 AutoBusCurrent; u8 UsedCfgMapEntires; diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 5f656f5..6542ae4 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1116,7 +1116,7 @@ * @param[in] *nb = this northbridge * @return = true - The link has the following status * LinkCon = 1, Link is connected - * InitComplete = 1,Link initilization is complete + * InitComplete = 1,Link initialization is complete * NC = 1, Link is coherent * UniP-cLDT = 0, Link is not Uniprocessor cLDT * LinkConPend = 0 Link connection is not pending diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 4c33a2f..388f064 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -846,7 +846,7 @@ dword &= (0x1 << 7); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94, dword); - /* Restore DRAM Adddress/Timing Control Register */ + /* Restore DRAM Address/Timing Control Register */ write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x04, data->f2x9cx04); } else { /* Disable PHY auto-compensation engine */ diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 66730fc..3d9ff3e 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -169,7 +169,7 @@ break; case NV_SPDCHK_RESTRT: val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */ - //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */ + //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */ //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */ if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS) diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 0e95341..5af3e16 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -107,7 +107,7 @@ } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 15ba7f4..7ee7198 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -59,7 +59,7 @@ } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index d116709..62855c2 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -95,7 +95,7 @@ } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 49afdc3..1f1c13f 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -93,7 +93,7 @@ } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) -- To view, visit https://review.coreboot.org/27911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I00094028036f33892362b935899e1bceef1da625 Gerrit-Change-Number: 27911 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit August 2018